1*ff2aa649SSascha Bischoff // SPDX-License-Identifier: GPL-2.0-only 2*ff2aa649SSascha Bischoff 3*ff2aa649SSascha Bischoff #include <kvm/arm_vgic.h> 4*ff2aa649SSascha Bischoff #include <linux/irqchip/arm-vgic-info.h> 5*ff2aa649SSascha Bischoff 6*ff2aa649SSascha Bischoff #include "vgic.h" 7*ff2aa649SSascha Bischoff 8*ff2aa649SSascha Bischoff /* 9*ff2aa649SSascha Bischoff * Probe for a vGICv5 compatible interrupt controller, returning 0 on success. 10*ff2aa649SSascha Bischoff * Currently only supports GICv3-based VMs on a GICv5 host, and hence only 11*ff2aa649SSascha Bischoff * registers a VGIC_V3 device. 12*ff2aa649SSascha Bischoff */ vgic_v5_probe(const struct gic_kvm_info * info)13*ff2aa649SSascha Bischoffint vgic_v5_probe(const struct gic_kvm_info *info) 14*ff2aa649SSascha Bischoff { 15*ff2aa649SSascha Bischoff u64 ich_vtr_el2; 16*ff2aa649SSascha Bischoff int ret; 17*ff2aa649SSascha Bischoff 18*ff2aa649SSascha Bischoff if (!info->has_gcie_v3_compat) 19*ff2aa649SSascha Bischoff return -ENODEV; 20*ff2aa649SSascha Bischoff 21*ff2aa649SSascha Bischoff kvm_vgic_global_state.type = VGIC_V5; 22*ff2aa649SSascha Bischoff kvm_vgic_global_state.has_gcie_v3_compat = true; 23*ff2aa649SSascha Bischoff 24*ff2aa649SSascha Bischoff /* We only support v3 compat mode - use vGICv3 limits */ 25*ff2aa649SSascha Bischoff kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; 26*ff2aa649SSascha Bischoff 27*ff2aa649SSascha Bischoff kvm_vgic_global_state.vcpu_base = 0; 28*ff2aa649SSascha Bischoff kvm_vgic_global_state.vctrl_base = NULL; 29*ff2aa649SSascha Bischoff kvm_vgic_global_state.can_emulate_gicv2 = false; 30*ff2aa649SSascha Bischoff kvm_vgic_global_state.has_gicv4 = false; 31*ff2aa649SSascha Bischoff kvm_vgic_global_state.has_gicv4_1 = false; 32*ff2aa649SSascha Bischoff 33*ff2aa649SSascha Bischoff ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config); 34*ff2aa649SSascha Bischoff kvm_vgic_global_state.ich_vtr_el2 = (u32)ich_vtr_el2; 35*ff2aa649SSascha Bischoff 36*ff2aa649SSascha Bischoff /* 37*ff2aa649SSascha Bischoff * The ListRegs field is 5 bits, but there is an architectural 38*ff2aa649SSascha Bischoff * maximum of 16 list registers. Just ignore bit 4... 39*ff2aa649SSascha Bischoff */ 40*ff2aa649SSascha Bischoff kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; 41*ff2aa649SSascha Bischoff 42*ff2aa649SSascha Bischoff ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); 43*ff2aa649SSascha Bischoff if (ret) { 44*ff2aa649SSascha Bischoff kvm_err("Cannot register GICv3-legacy KVM device.\n"); 45*ff2aa649SSascha Bischoff return ret; 46*ff2aa649SSascha Bischoff } 47*ff2aa649SSascha Bischoff 48*ff2aa649SSascha Bischoff static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif); 49*ff2aa649SSascha Bischoff kvm_info("GCIE legacy system register CPU interface\n"); 50*ff2aa649SSascha Bischoff 51*ff2aa649SSascha Bischoff return 0; 52*ff2aa649SSascha Bischoff } 53