1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bsearch.h> 14 #include <linux/cacheinfo.h> 15 #include <linux/debugfs.h> 16 #include <linux/kvm_host.h> 17 #include <linux/mm.h> 18 #include <linux/printk.h> 19 #include <linux/uaccess.h> 20 21 #include <asm/arm_pmuv3.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cputype.h> 24 #include <asm/debug-monitors.h> 25 #include <asm/esr.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_emulate.h> 28 #include <asm/kvm_hyp.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/perf_event.h> 32 #include <asm/sysreg.h> 33 34 #include <trace/events/kvm.h> 35 36 #include "sys_regs.h" 37 #include "vgic/vgic.h" 38 39 #include "trace.h" 40 41 /* 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 49 u64 val); 50 51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 52 const struct sys_reg_desc *r) 53 { 54 kvm_inject_undefined(vcpu); 55 return false; 56 } 57 58 static bool bad_trap(struct kvm_vcpu *vcpu, 59 struct sys_reg_params *params, 60 const struct sys_reg_desc *r, 61 const char *msg) 62 { 63 WARN_ONCE(1, "Unexpected %s\n", msg); 64 print_sys_reg_instr(params); 65 return undef_access(vcpu, params, r); 66 } 67 68 static bool read_from_write_only(struct kvm_vcpu *vcpu, 69 struct sys_reg_params *params, 70 const struct sys_reg_desc *r) 71 { 72 return bad_trap(vcpu, params, r, 73 "sys_reg read to write-only register"); 74 } 75 76 static bool write_to_read_only(struct kvm_vcpu *vcpu, 77 struct sys_reg_params *params, 78 const struct sys_reg_desc *r) 79 { 80 return bad_trap(vcpu, params, r, 81 "sys_reg write to read-only register"); 82 } 83 84 #define PURE_EL2_SYSREG(el2) \ 85 case el2: { \ 86 *el1r = el2; \ 87 return true; \ 88 } 89 90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \ 91 case el2: { \ 92 *xlate = fn; \ 93 *el1r = el1; \ 94 return true; \ 95 } 96 97 static bool get_el2_to_el1_mapping(unsigned int reg, 98 unsigned int *el1r, u64 (**xlate)(u64)) 99 { 100 switch (reg) { 101 PURE_EL2_SYSREG( VPIDR_EL2 ); 102 PURE_EL2_SYSREG( VMPIDR_EL2 ); 103 PURE_EL2_SYSREG( ACTLR_EL2 ); 104 PURE_EL2_SYSREG( HCR_EL2 ); 105 PURE_EL2_SYSREG( MDCR_EL2 ); 106 PURE_EL2_SYSREG( HSTR_EL2 ); 107 PURE_EL2_SYSREG( HACR_EL2 ); 108 PURE_EL2_SYSREG( VTTBR_EL2 ); 109 PURE_EL2_SYSREG( VTCR_EL2 ); 110 PURE_EL2_SYSREG( RVBAR_EL2 ); 111 PURE_EL2_SYSREG( TPIDR_EL2 ); 112 PURE_EL2_SYSREG( HPFAR_EL2 ); 113 PURE_EL2_SYSREG( HCRX_EL2 ); 114 PURE_EL2_SYSREG( HFGRTR_EL2 ); 115 PURE_EL2_SYSREG( HFGWTR_EL2 ); 116 PURE_EL2_SYSREG( HFGITR_EL2 ); 117 PURE_EL2_SYSREG( HDFGRTR_EL2 ); 118 PURE_EL2_SYSREG( HDFGWTR_EL2 ); 119 PURE_EL2_SYSREG( HAFGRTR_EL2 ); 120 PURE_EL2_SYSREG( CNTVOFF_EL2 ); 121 PURE_EL2_SYSREG( CNTHCTL_EL2 ); 122 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1, 123 translate_sctlr_el2_to_sctlr_el1 ); 124 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1, 125 translate_cptr_el2_to_cpacr_el1 ); 126 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1, 127 translate_ttbr0_el2_to_ttbr0_el1 ); 128 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL ); 129 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1, 130 translate_tcr_el2_to_tcr_el1 ); 131 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL ); 132 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL ); 133 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL ); 134 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL ); 135 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL ); 136 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL ); 137 MAPPED_EL2_SYSREG(TCR2_EL2, TCR2_EL1, NULL ); 138 MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); 139 MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); 140 MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); 141 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); 142 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); 143 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); 144 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL ); 145 MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL ); 146 default: 147 return false; 148 } 149 } 150 151 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 152 { 153 u64 val = 0x8badf00d8badf00d; 154 u64 (*xlate)(u64) = NULL; 155 unsigned int el1r; 156 157 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 158 goto memory_read; 159 160 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 161 if (!is_hyp_ctxt(vcpu)) 162 goto memory_read; 163 164 /* 165 * CNTHCTL_EL2 requires some special treatment to 166 * account for the bits that can be set via CNTKCTL_EL1. 167 */ 168 switch (reg) { 169 case CNTHCTL_EL2: 170 if (vcpu_el2_e2h_is_set(vcpu)) { 171 val = read_sysreg_el1(SYS_CNTKCTL); 172 val &= CNTKCTL_VALID_BITS; 173 val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; 174 return val; 175 } 176 break; 177 } 178 179 /* 180 * If this register does not have an EL1 counterpart, 181 * then read the stored EL2 version. 182 */ 183 if (reg == el1r) 184 goto memory_read; 185 186 /* 187 * If we have a non-VHE guest and that the sysreg 188 * requires translation to be used at EL1, use the 189 * in-memory copy instead. 190 */ 191 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 192 goto memory_read; 193 194 /* Get the current version of the EL1 counterpart. */ 195 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val)); 196 if (reg >= __SANITISED_REG_START__) 197 val = kvm_vcpu_apply_reg_masks(vcpu, reg, val); 198 199 return val; 200 } 201 202 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 203 if (unlikely(is_hyp_ctxt(vcpu))) 204 goto memory_read; 205 206 if (__vcpu_read_sys_reg_from_cpu(reg, &val)) 207 return val; 208 209 memory_read: 210 return __vcpu_sys_reg(vcpu, reg); 211 } 212 213 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 214 { 215 u64 (*xlate)(u64) = NULL; 216 unsigned int el1r; 217 218 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) 219 goto memory_write; 220 221 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) { 222 if (!is_hyp_ctxt(vcpu)) 223 goto memory_write; 224 225 /* 226 * Always store a copy of the write to memory to avoid having 227 * to reverse-translate virtual EL2 system registers for a 228 * non-VHE guest hypervisor. 229 */ 230 __vcpu_sys_reg(vcpu, reg) = val; 231 232 switch (reg) { 233 case CNTHCTL_EL2: 234 /* 235 * If E2H=0, CNHTCTL_EL2 is a pure shadow register. 236 * Otherwise, some of the bits are backed by 237 * CNTKCTL_EL1, while the rest is kept in memory. 238 * Yes, this is fun stuff. 239 */ 240 if (vcpu_el2_e2h_is_set(vcpu)) 241 write_sysreg_el1(val, SYS_CNTKCTL); 242 return; 243 } 244 245 /* No EL1 counterpart? We're done here.? */ 246 if (reg == el1r) 247 return; 248 249 if (!vcpu_el2_e2h_is_set(vcpu) && xlate) 250 val = xlate(val); 251 252 /* Redirect this to the EL1 version of the register. */ 253 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r)); 254 return; 255 } 256 257 /* EL1 register can't be on the CPU if the guest is in vEL2. */ 258 if (unlikely(is_hyp_ctxt(vcpu))) 259 goto memory_write; 260 261 if (__vcpu_write_sys_reg_to_cpu(val, reg)) 262 return; 263 264 memory_write: 265 __vcpu_sys_reg(vcpu, reg) = val; 266 } 267 268 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 269 #define CSSELR_MAX 14 270 271 /* 272 * Returns the minimum line size for the selected cache, expressed as 273 * Log2(bytes). 274 */ 275 static u8 get_min_cache_line_size(bool icache) 276 { 277 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0); 278 u8 field; 279 280 if (icache) 281 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr); 282 else 283 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr); 284 285 /* 286 * Cache line size is represented as Log2(words) in CTR_EL0. 287 * Log2(bytes) can be derived with the following: 288 * 289 * Log2(words) + 2 = Log2(bytes / 4) + 2 290 * = Log2(bytes) - 2 + 2 291 * = Log2(bytes) 292 */ 293 return field + 2; 294 } 295 296 /* Which cache CCSIDR represents depends on CSSELR value. */ 297 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) 298 { 299 u8 line_size; 300 301 if (vcpu->arch.ccsidr) 302 return vcpu->arch.ccsidr[csselr]; 303 304 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD); 305 306 /* 307 * Fabricate a CCSIDR value as the overriding value does not exist. 308 * The real CCSIDR value will not be used as it can vary by the 309 * physical CPU which the vcpu currently resides in. 310 * 311 * The line size is determined with get_min_cache_line_size(), which 312 * should be valid for all CPUs even if they have different cache 313 * configuration. 314 * 315 * The associativity bits are cleared, meaning the geometry of all data 316 * and unified caches (which are guaranteed to be PIPT and thus 317 * non-aliasing) are 1 set and 1 way. 318 * Guests should not be doing cache operations by set/way at all, and 319 * for this reason, we trap them and attempt to infer the intent, so 320 * that we can flush the entire guest's address space at the appropriate 321 * time. The exposed geometry minimizes the number of the traps. 322 * [If guests should attempt to infer aliasing properties from the 323 * geometry (which is not permitted by the architecture), they would 324 * only do so for virtually indexed caches.] 325 * 326 * We don't check if the cache level exists as it is allowed to return 327 * an UNKNOWN value if not. 328 */ 329 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4); 330 } 331 332 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) 333 { 334 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4; 335 u32 *ccsidr = vcpu->arch.ccsidr; 336 u32 i; 337 338 if ((val & CCSIDR_EL1_RES0) || 339 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD)) 340 return -EINVAL; 341 342 if (!ccsidr) { 343 if (val == get_ccsidr(vcpu, csselr)) 344 return 0; 345 346 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT); 347 if (!ccsidr) 348 return -ENOMEM; 349 350 for (i = 0; i < CSSELR_MAX; i++) 351 ccsidr[i] = get_ccsidr(vcpu, i); 352 353 vcpu->arch.ccsidr = ccsidr; 354 } 355 356 ccsidr[csselr] = val; 357 358 return 0; 359 } 360 361 static bool access_rw(struct kvm_vcpu *vcpu, 362 struct sys_reg_params *p, 363 const struct sys_reg_desc *r) 364 { 365 if (p->is_write) 366 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 367 else 368 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 369 370 return true; 371 } 372 373 /* 374 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 375 */ 376 static bool access_dcsw(struct kvm_vcpu *vcpu, 377 struct sys_reg_params *p, 378 const struct sys_reg_desc *r) 379 { 380 if (!p->is_write) 381 return read_from_write_only(vcpu, p, r); 382 383 /* 384 * Only track S/W ops if we don't have FWB. It still indicates 385 * that the guest is a bit broken (S/W operations should only 386 * be done by firmware, knowing that there is only a single 387 * CPU left in the system, and certainly not from non-secure 388 * software). 389 */ 390 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 391 kvm_set_way_flush(vcpu); 392 393 return true; 394 } 395 396 static bool access_dcgsw(struct kvm_vcpu *vcpu, 397 struct sys_reg_params *p, 398 const struct sys_reg_desc *r) 399 { 400 if (!kvm_has_mte(vcpu->kvm)) 401 return undef_access(vcpu, p, r); 402 403 /* Treat MTE S/W ops as we treat the classic ones: with contempt */ 404 return access_dcsw(vcpu, p, r); 405 } 406 407 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 408 { 409 switch (r->aarch32_map) { 410 case AA32_LO: 411 *mask = GENMASK_ULL(31, 0); 412 *shift = 0; 413 break; 414 case AA32_HI: 415 *mask = GENMASK_ULL(63, 32); 416 *shift = 32; 417 break; 418 default: 419 *mask = GENMASK_ULL(63, 0); 420 *shift = 0; 421 break; 422 } 423 } 424 425 /* 426 * Generic accessor for VM registers. Only called as long as HCR_TVM 427 * is set. If the guest enables the MMU, we stop trapping the VM 428 * sys_regs and leave it in complete control of the caches. 429 */ 430 static bool access_vm_reg(struct kvm_vcpu *vcpu, 431 struct sys_reg_params *p, 432 const struct sys_reg_desc *r) 433 { 434 bool was_enabled = vcpu_has_cache_enabled(vcpu); 435 u64 val, mask, shift; 436 437 BUG_ON(!p->is_write); 438 439 get_access_mask(r, &mask, &shift); 440 441 if (~mask) { 442 val = vcpu_read_sys_reg(vcpu, r->reg); 443 val &= ~mask; 444 } else { 445 val = 0; 446 } 447 448 val |= (p->regval & (mask >> shift)) << shift; 449 vcpu_write_sys_reg(vcpu, val, r->reg); 450 451 kvm_toggle_cache(vcpu, was_enabled); 452 return true; 453 } 454 455 static bool access_actlr(struct kvm_vcpu *vcpu, 456 struct sys_reg_params *p, 457 const struct sys_reg_desc *r) 458 { 459 u64 mask, shift; 460 461 if (p->is_write) 462 return ignore_write(vcpu, p); 463 464 get_access_mask(r, &mask, &shift); 465 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 466 467 return true; 468 } 469 470 /* 471 * Trap handler for the GICv3 SGI generation system register. 472 * Forward the request to the VGIC emulation. 473 * The cp15_64 code makes sure this automatically works 474 * for both AArch64 and AArch32 accesses. 475 */ 476 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 477 struct sys_reg_params *p, 478 const struct sys_reg_desc *r) 479 { 480 bool g1; 481 482 if (!kvm_has_gicv3(vcpu->kvm)) 483 return undef_access(vcpu, p, r); 484 485 if (!p->is_write) 486 return read_from_write_only(vcpu, p, r); 487 488 /* 489 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 490 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 491 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 492 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 493 * group. 494 */ 495 if (p->Op0 == 0) { /* AArch32 */ 496 switch (p->Op1) { 497 default: /* Keep GCC quiet */ 498 case 0: /* ICC_SGI1R */ 499 g1 = true; 500 break; 501 case 1: /* ICC_ASGI1R */ 502 case 2: /* ICC_SGI0R */ 503 g1 = false; 504 break; 505 } 506 } else { /* AArch64 */ 507 switch (p->Op2) { 508 default: /* Keep GCC quiet */ 509 case 5: /* ICC_SGI1R_EL1 */ 510 g1 = true; 511 break; 512 case 6: /* ICC_ASGI1R_EL1 */ 513 case 7: /* ICC_SGI0R_EL1 */ 514 g1 = false; 515 break; 516 } 517 } 518 519 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 520 521 return true; 522 } 523 524 static bool access_gic_sre(struct kvm_vcpu *vcpu, 525 struct sys_reg_params *p, 526 const struct sys_reg_desc *r) 527 { 528 if (!kvm_has_gicv3(vcpu->kvm)) 529 return undef_access(vcpu, p, r); 530 531 if (p->is_write) 532 return ignore_write(vcpu, p); 533 534 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 535 return true; 536 } 537 538 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 539 struct sys_reg_params *p, 540 const struct sys_reg_desc *r) 541 { 542 if (p->is_write) 543 return ignore_write(vcpu, p); 544 else 545 return read_zero(vcpu, p); 546 } 547 548 /* 549 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 550 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 551 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 552 * treat it separately. 553 */ 554 static bool trap_loregion(struct kvm_vcpu *vcpu, 555 struct sys_reg_params *p, 556 const struct sys_reg_desc *r) 557 { 558 u32 sr = reg_to_encoding(r); 559 560 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) 561 return undef_access(vcpu, p, r); 562 563 if (p->is_write && sr == SYS_LORID_EL1) 564 return write_to_read_only(vcpu, p, r); 565 566 return trap_raz_wi(vcpu, p, r); 567 } 568 569 static bool trap_oslar_el1(struct kvm_vcpu *vcpu, 570 struct sys_reg_params *p, 571 const struct sys_reg_desc *r) 572 { 573 if (!p->is_write) 574 return read_from_write_only(vcpu, p, r); 575 576 kvm_debug_handle_oslar(vcpu, p->regval); 577 return true; 578 } 579 580 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 581 struct sys_reg_params *p, 582 const struct sys_reg_desc *r) 583 { 584 if (p->is_write) 585 return write_to_read_only(vcpu, p, r); 586 587 p->regval = __vcpu_sys_reg(vcpu, r->reg); 588 return true; 589 } 590 591 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 592 u64 val) 593 { 594 /* 595 * The only modifiable bit is the OSLK bit. Refuse the write if 596 * userspace attempts to change any other bit in the register. 597 */ 598 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK) 599 return -EINVAL; 600 601 __vcpu_sys_reg(vcpu, rd->reg) = val; 602 return 0; 603 } 604 605 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 606 struct sys_reg_params *p, 607 const struct sys_reg_desc *r) 608 { 609 if (p->is_write) { 610 return ignore_write(vcpu, p); 611 } else { 612 p->regval = read_sysreg(dbgauthstatus_el1); 613 return true; 614 } 615 } 616 617 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 618 struct sys_reg_params *p, 619 const struct sys_reg_desc *r) 620 { 621 access_rw(vcpu, p, r); 622 623 kvm_debug_set_guest_ownership(vcpu); 624 return true; 625 } 626 627 /* 628 * reg_to_dbg/dbg_to_reg 629 * 630 * A 32 bit write to a debug register leave top bits alone 631 * A 32 bit read from a debug register only returns the bottom bits 632 */ 633 static void reg_to_dbg(struct kvm_vcpu *vcpu, 634 struct sys_reg_params *p, 635 const struct sys_reg_desc *rd, 636 u64 *dbg_reg) 637 { 638 u64 mask, shift, val; 639 640 get_access_mask(rd, &mask, &shift); 641 642 val = *dbg_reg; 643 val &= ~mask; 644 val |= (p->regval & (mask >> shift)) << shift; 645 *dbg_reg = val; 646 } 647 648 static void dbg_to_reg(struct kvm_vcpu *vcpu, 649 struct sys_reg_params *p, 650 const struct sys_reg_desc *rd, 651 u64 *dbg_reg) 652 { 653 u64 mask, shift; 654 655 get_access_mask(rd, &mask, &shift); 656 p->regval = (*dbg_reg & mask) >> shift; 657 } 658 659 static u64 *demux_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 660 { 661 struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; 662 663 switch (rd->Op2) { 664 case 0b100: 665 return &dbg->dbg_bvr[rd->CRm]; 666 case 0b101: 667 return &dbg->dbg_bcr[rd->CRm]; 668 case 0b110: 669 return &dbg->dbg_wvr[rd->CRm]; 670 case 0b111: 671 return &dbg->dbg_wcr[rd->CRm]; 672 default: 673 KVM_BUG_ON(1, vcpu->kvm); 674 return NULL; 675 } 676 } 677 678 static bool trap_dbg_wb_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 679 const struct sys_reg_desc *rd) 680 { 681 u64 *reg = demux_wb_reg(vcpu, rd); 682 683 if (!reg) 684 return false; 685 686 if (p->is_write) 687 reg_to_dbg(vcpu, p, rd, reg); 688 else 689 dbg_to_reg(vcpu, p, rd, reg); 690 691 kvm_debug_set_guest_ownership(vcpu); 692 return true; 693 } 694 695 static int set_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 696 u64 val) 697 { 698 u64 *reg = demux_wb_reg(vcpu, rd); 699 700 if (!reg) 701 return -EINVAL; 702 703 *reg = val; 704 return 0; 705 } 706 707 static int get_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 708 u64 *val) 709 { 710 u64 *reg = demux_wb_reg(vcpu, rd); 711 712 if (!reg) 713 return -EINVAL; 714 715 *val = *reg; 716 return 0; 717 } 718 719 static u64 reset_dbg_wb_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) 720 { 721 u64 *reg = demux_wb_reg(vcpu, rd); 722 723 /* 724 * Bail early if we couldn't find storage for the register, the 725 * KVM_BUG_ON() in demux_wb_reg() will prevent this VM from ever 726 * being run. 727 */ 728 if (!reg) 729 return 0; 730 731 *reg = rd->val; 732 return rd->val; 733 } 734 735 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 736 { 737 u64 amair = read_sysreg(amair_el1); 738 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 739 return amair; 740 } 741 742 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 743 { 744 u64 actlr = read_sysreg(actlr_el1); 745 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 746 return actlr; 747 } 748 749 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 750 { 751 u64 mpidr; 752 753 /* 754 * Map the vcpu_id into the first three affinity level fields of 755 * the MPIDR. We limit the number of VCPUs in level 0 due to a 756 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 757 * of the GICv3 to be able to address each CPU directly when 758 * sending IPIs. 759 */ 760 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 761 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 762 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 763 mpidr |= (1ULL << 31); 764 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); 765 766 return mpidr; 767 } 768 769 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, 770 const struct sys_reg_desc *r) 771 { 772 if (kvm_vcpu_has_pmu(vcpu)) 773 return 0; 774 775 return REG_HIDDEN; 776 } 777 778 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 779 { 780 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX); 781 u8 n = vcpu->kvm->arch.pmcr_n; 782 783 if (n) 784 mask |= GENMASK(n - 1, 0); 785 786 reset_unknown(vcpu, r); 787 __vcpu_sys_reg(vcpu, r->reg) &= mask; 788 789 return __vcpu_sys_reg(vcpu, r->reg); 790 } 791 792 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 793 { 794 reset_unknown(vcpu, r); 795 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0); 796 797 return __vcpu_sys_reg(vcpu, r->reg); 798 } 799 800 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 801 { 802 /* This thing will UNDEF, who cares about the reset value? */ 803 if (!kvm_vcpu_has_pmu(vcpu)) 804 return 0; 805 806 reset_unknown(vcpu, r); 807 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm); 808 809 return __vcpu_sys_reg(vcpu, r->reg); 810 } 811 812 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 813 { 814 reset_unknown(vcpu, r); 815 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK; 816 817 return __vcpu_sys_reg(vcpu, r->reg); 818 } 819 820 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 821 { 822 u64 pmcr = 0; 823 824 if (!kvm_supports_32bit_el0()) 825 pmcr |= ARMV8_PMU_PMCR_LC; 826 827 /* 828 * The value of PMCR.N field is included when the 829 * vCPU register is read via kvm_vcpu_read_pmcr(). 830 */ 831 __vcpu_sys_reg(vcpu, r->reg) = pmcr; 832 833 return __vcpu_sys_reg(vcpu, r->reg); 834 } 835 836 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 837 { 838 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 839 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 840 841 if (!enabled) 842 kvm_inject_undefined(vcpu); 843 844 return !enabled; 845 } 846 847 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 848 { 849 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 850 } 851 852 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 853 { 854 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 855 } 856 857 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 858 { 859 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 860 } 861 862 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 863 { 864 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 865 } 866 867 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 868 const struct sys_reg_desc *r) 869 { 870 u64 val; 871 872 if (pmu_access_el0_disabled(vcpu)) 873 return false; 874 875 if (p->is_write) { 876 /* 877 * Only update writeable bits of PMCR (continuing into 878 * kvm_pmu_handle_pmcr() as well) 879 */ 880 val = kvm_vcpu_read_pmcr(vcpu); 881 val &= ~ARMV8_PMU_PMCR_MASK; 882 val |= p->regval & ARMV8_PMU_PMCR_MASK; 883 if (!kvm_supports_32bit_el0()) 884 val |= ARMV8_PMU_PMCR_LC; 885 kvm_pmu_handle_pmcr(vcpu, val); 886 } else { 887 /* PMCR.P & PMCR.C are RAZ */ 888 val = kvm_vcpu_read_pmcr(vcpu) 889 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 890 p->regval = val; 891 } 892 893 return true; 894 } 895 896 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 897 const struct sys_reg_desc *r) 898 { 899 if (pmu_access_event_counter_el0_disabled(vcpu)) 900 return false; 901 902 if (p->is_write) 903 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 904 else 905 /* return PMSELR.SEL field */ 906 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 907 & PMSELR_EL0_SEL_MASK; 908 909 return true; 910 } 911 912 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 913 const struct sys_reg_desc *r) 914 { 915 u64 pmceid, mask, shift; 916 917 BUG_ON(p->is_write); 918 919 if (pmu_access_el0_disabled(vcpu)) 920 return false; 921 922 get_access_mask(r, &mask, &shift); 923 924 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 925 pmceid &= mask; 926 pmceid >>= shift; 927 928 p->regval = pmceid; 929 930 return true; 931 } 932 933 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 934 { 935 u64 pmcr, val; 936 937 pmcr = kvm_vcpu_read_pmcr(vcpu); 938 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); 939 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 940 kvm_inject_undefined(vcpu); 941 return false; 942 } 943 944 return true; 945 } 946 947 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 948 u64 *val) 949 { 950 u64 idx; 951 952 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0) 953 /* PMCCNTR_EL0 */ 954 idx = ARMV8_PMU_CYCLE_IDX; 955 else 956 /* PMEVCNTRn_EL0 */ 957 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 958 959 *val = kvm_pmu_get_counter_value(vcpu, idx); 960 return 0; 961 } 962 963 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 964 struct sys_reg_params *p, 965 const struct sys_reg_desc *r) 966 { 967 u64 idx = ~0UL; 968 969 if (r->CRn == 9 && r->CRm == 13) { 970 if (r->Op2 == 2) { 971 /* PMXEVCNTR_EL0 */ 972 if (pmu_access_event_counter_el0_disabled(vcpu)) 973 return false; 974 975 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, 976 __vcpu_sys_reg(vcpu, PMSELR_EL0)); 977 } else if (r->Op2 == 0) { 978 /* PMCCNTR_EL0 */ 979 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 980 return false; 981 982 idx = ARMV8_PMU_CYCLE_IDX; 983 } 984 } else if (r->CRn == 0 && r->CRm == 9) { 985 /* PMCCNTR */ 986 if (pmu_access_event_counter_el0_disabled(vcpu)) 987 return false; 988 989 idx = ARMV8_PMU_CYCLE_IDX; 990 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 991 /* PMEVCNTRn_EL0 */ 992 if (pmu_access_event_counter_el0_disabled(vcpu)) 993 return false; 994 995 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 996 } 997 998 /* Catch any decoding mistake */ 999 WARN_ON(idx == ~0UL); 1000 1001 if (!pmu_counter_idx_valid(vcpu, idx)) 1002 return false; 1003 1004 if (p->is_write) { 1005 if (pmu_access_el0_disabled(vcpu)) 1006 return false; 1007 1008 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 1009 } else { 1010 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 1011 } 1012 1013 return true; 1014 } 1015 1016 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1017 const struct sys_reg_desc *r) 1018 { 1019 u64 idx, reg; 1020 1021 if (pmu_access_el0_disabled(vcpu)) 1022 return false; 1023 1024 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 1025 /* PMXEVTYPER_EL0 */ 1026 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0)); 1027 reg = PMEVTYPER0_EL0 + idx; 1028 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 1029 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 1030 if (idx == ARMV8_PMU_CYCLE_IDX) 1031 reg = PMCCFILTR_EL0; 1032 else 1033 /* PMEVTYPERn_EL0 */ 1034 reg = PMEVTYPER0_EL0 + idx; 1035 } else { 1036 BUG(); 1037 } 1038 1039 if (!pmu_counter_idx_valid(vcpu, idx)) 1040 return false; 1041 1042 if (p->is_write) { 1043 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 1044 kvm_vcpu_pmu_restore_guest(vcpu); 1045 } else { 1046 p->regval = __vcpu_sys_reg(vcpu, reg); 1047 } 1048 1049 return true; 1050 } 1051 1052 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val) 1053 { 1054 bool set; 1055 1056 val &= kvm_pmu_accessible_counter_mask(vcpu); 1057 1058 switch (r->reg) { 1059 case PMOVSSET_EL0: 1060 /* CRm[1] being set indicates a SET register, and CLR otherwise */ 1061 set = r->CRm & 2; 1062 break; 1063 default: 1064 /* Op2[0] being set indicates a SET register, and CLR otherwise */ 1065 set = r->Op2 & 1; 1066 break; 1067 } 1068 1069 if (set) 1070 __vcpu_sys_reg(vcpu, r->reg) |= val; 1071 else 1072 __vcpu_sys_reg(vcpu, r->reg) &= ~val; 1073 1074 return 0; 1075 } 1076 1077 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val) 1078 { 1079 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1080 1081 *val = __vcpu_sys_reg(vcpu, r->reg) & mask; 1082 return 0; 1083 } 1084 1085 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1086 const struct sys_reg_desc *r) 1087 { 1088 u64 val, mask; 1089 1090 if (pmu_access_el0_disabled(vcpu)) 1091 return false; 1092 1093 mask = kvm_pmu_accessible_counter_mask(vcpu); 1094 if (p->is_write) { 1095 val = p->regval & mask; 1096 if (r->Op2 & 0x1) 1097 /* accessing PMCNTENSET_EL0 */ 1098 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 1099 else 1100 /* accessing PMCNTENCLR_EL0 */ 1101 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 1102 1103 kvm_pmu_reprogram_counter_mask(vcpu, val); 1104 } else { 1105 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); 1106 } 1107 1108 return true; 1109 } 1110 1111 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1112 const struct sys_reg_desc *r) 1113 { 1114 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1115 1116 if (check_pmu_access_disabled(vcpu, 0)) 1117 return false; 1118 1119 if (p->is_write) { 1120 u64 val = p->regval & mask; 1121 1122 if (r->Op2 & 0x1) 1123 /* accessing PMINTENSET_EL1 */ 1124 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 1125 else 1126 /* accessing PMINTENCLR_EL1 */ 1127 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 1128 } else { 1129 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1); 1130 } 1131 1132 return true; 1133 } 1134 1135 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1136 const struct sys_reg_desc *r) 1137 { 1138 u64 mask = kvm_pmu_accessible_counter_mask(vcpu); 1139 1140 if (pmu_access_el0_disabled(vcpu)) 1141 return false; 1142 1143 if (p->is_write) { 1144 if (r->CRm & 0x2) 1145 /* accessing PMOVSSET_EL0 */ 1146 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 1147 else 1148 /* accessing PMOVSCLR_EL0 */ 1149 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 1150 } else { 1151 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); 1152 } 1153 1154 return true; 1155 } 1156 1157 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1158 const struct sys_reg_desc *r) 1159 { 1160 u64 mask; 1161 1162 if (!p->is_write) 1163 return read_from_write_only(vcpu, p, r); 1164 1165 if (pmu_write_swinc_el0_disabled(vcpu)) 1166 return false; 1167 1168 mask = kvm_pmu_accessible_counter_mask(vcpu); 1169 kvm_pmu_software_increment(vcpu, p->regval & mask); 1170 return true; 1171 } 1172 1173 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1174 const struct sys_reg_desc *r) 1175 { 1176 if (p->is_write) { 1177 if (!vcpu_mode_priv(vcpu)) 1178 return undef_access(vcpu, p, r); 1179 1180 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1181 p->regval & ARMV8_PMU_USERENR_MASK; 1182 } else { 1183 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1184 & ARMV8_PMU_USERENR_MASK; 1185 } 1186 1187 return true; 1188 } 1189 1190 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1191 u64 *val) 1192 { 1193 *val = kvm_vcpu_read_pmcr(vcpu); 1194 return 0; 1195 } 1196 1197 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 1198 u64 val) 1199 { 1200 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val); 1201 struct kvm *kvm = vcpu->kvm; 1202 1203 mutex_lock(&kvm->arch.config_lock); 1204 1205 /* 1206 * The vCPU can't have more counters than the PMU hardware 1207 * implements. Ignore this error to maintain compatibility 1208 * with the existing KVM behavior. 1209 */ 1210 if (!kvm_vm_has_ran_once(kvm) && 1211 new_n <= kvm_arm_pmu_get_max_counters(kvm)) 1212 kvm->arch.pmcr_n = new_n; 1213 1214 mutex_unlock(&kvm->arch.config_lock); 1215 1216 /* 1217 * Ignore writes to RES0 bits, read only bits that are cleared on 1218 * vCPU reset, and writable bits that KVM doesn't support yet. 1219 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace) 1220 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU. 1221 * But, we leave the bit as it is here, as the vCPU's PMUver might 1222 * be changed later (NOTE: the bit will be cleared on first vCPU run 1223 * if necessary). 1224 */ 1225 val &= ARMV8_PMU_PMCR_MASK; 1226 1227 /* The LC bit is RES1 when AArch32 is not supported */ 1228 if (!kvm_supports_32bit_el0()) 1229 val |= ARMV8_PMU_PMCR_LC; 1230 1231 __vcpu_sys_reg(vcpu, r->reg) = val; 1232 return 0; 1233 } 1234 1235 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1236 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1237 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1238 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1239 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1240 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1241 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1242 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1243 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1244 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1245 get_dbg_wb_reg, set_dbg_wb_reg }, \ 1246 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1247 trap_dbg_wb_reg, reset_dbg_wb_reg, 0, 0, \ 1248 get_dbg_wb_reg, set_dbg_wb_reg } 1249 1250 #define PMU_SYS_REG(name) \ 1251 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \ 1252 .visibility = pmu_visibility 1253 1254 /* Macro to expand the PMEVCNTRn_EL0 register */ 1255 #define PMU_PMEVCNTR_EL0(n) \ 1256 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ 1257 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \ 1258 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), } 1259 1260 /* Macro to expand the PMEVTYPERn_EL0 register */ 1261 #define PMU_PMEVTYPER_EL0(n) \ 1262 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \ 1263 .reset = reset_pmevtyper, \ 1264 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), } 1265 1266 /* Macro to expand the AMU counter and type registers*/ 1267 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 1268 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 1269 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 1270 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 1271 1272 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1273 const struct sys_reg_desc *rd) 1274 { 1275 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 1276 } 1277 1278 /* 1279 * If we land here on a PtrAuth access, that is because we didn't 1280 * fixup the access on exit by allowing the PtrAuth sysregs. The only 1281 * way this happens is when the guest does not have PtrAuth support 1282 * enabled. 1283 */ 1284 #define __PTRAUTH_KEY(k) \ 1285 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 1286 .visibility = ptrauth_visibility} 1287 1288 #define PTRAUTH_KEY(k) \ 1289 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1290 __PTRAUTH_KEY(k ## KEYHI_EL1) 1291 1292 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1293 struct sys_reg_params *p, 1294 const struct sys_reg_desc *r) 1295 { 1296 enum kvm_arch_timers tmr; 1297 enum kvm_arch_timer_regs treg; 1298 u64 reg = reg_to_encoding(r); 1299 1300 switch (reg) { 1301 case SYS_CNTP_TVAL_EL0: 1302 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1303 tmr = TIMER_HPTIMER; 1304 else 1305 tmr = TIMER_PTIMER; 1306 treg = TIMER_REG_TVAL; 1307 break; 1308 1309 case SYS_CNTV_TVAL_EL0: 1310 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1311 tmr = TIMER_HVTIMER; 1312 else 1313 tmr = TIMER_VTIMER; 1314 treg = TIMER_REG_TVAL; 1315 break; 1316 1317 case SYS_AARCH32_CNTP_TVAL: 1318 case SYS_CNTP_TVAL_EL02: 1319 tmr = TIMER_PTIMER; 1320 treg = TIMER_REG_TVAL; 1321 break; 1322 1323 case SYS_CNTV_TVAL_EL02: 1324 tmr = TIMER_VTIMER; 1325 treg = TIMER_REG_TVAL; 1326 break; 1327 1328 case SYS_CNTHP_TVAL_EL2: 1329 tmr = TIMER_HPTIMER; 1330 treg = TIMER_REG_TVAL; 1331 break; 1332 1333 case SYS_CNTHV_TVAL_EL2: 1334 tmr = TIMER_HVTIMER; 1335 treg = TIMER_REG_TVAL; 1336 break; 1337 1338 case SYS_CNTP_CTL_EL0: 1339 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1340 tmr = TIMER_HPTIMER; 1341 else 1342 tmr = TIMER_PTIMER; 1343 treg = TIMER_REG_CTL; 1344 break; 1345 1346 case SYS_CNTV_CTL_EL0: 1347 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1348 tmr = TIMER_HVTIMER; 1349 else 1350 tmr = TIMER_VTIMER; 1351 treg = TIMER_REG_CTL; 1352 break; 1353 1354 case SYS_AARCH32_CNTP_CTL: 1355 case SYS_CNTP_CTL_EL02: 1356 tmr = TIMER_PTIMER; 1357 treg = TIMER_REG_CTL; 1358 break; 1359 1360 case SYS_CNTV_CTL_EL02: 1361 tmr = TIMER_VTIMER; 1362 treg = TIMER_REG_CTL; 1363 break; 1364 1365 case SYS_CNTHP_CTL_EL2: 1366 tmr = TIMER_HPTIMER; 1367 treg = TIMER_REG_CTL; 1368 break; 1369 1370 case SYS_CNTHV_CTL_EL2: 1371 tmr = TIMER_HVTIMER; 1372 treg = TIMER_REG_CTL; 1373 break; 1374 1375 case SYS_CNTP_CVAL_EL0: 1376 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1377 tmr = TIMER_HPTIMER; 1378 else 1379 tmr = TIMER_PTIMER; 1380 treg = TIMER_REG_CVAL; 1381 break; 1382 1383 case SYS_CNTV_CVAL_EL0: 1384 if (is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) 1385 tmr = TIMER_HVTIMER; 1386 else 1387 tmr = TIMER_VTIMER; 1388 treg = TIMER_REG_CVAL; 1389 break; 1390 1391 case SYS_AARCH32_CNTP_CVAL: 1392 case SYS_CNTP_CVAL_EL02: 1393 tmr = TIMER_PTIMER; 1394 treg = TIMER_REG_CVAL; 1395 break; 1396 1397 case SYS_CNTV_CVAL_EL02: 1398 tmr = TIMER_VTIMER; 1399 treg = TIMER_REG_CVAL; 1400 break; 1401 1402 case SYS_CNTHP_CVAL_EL2: 1403 tmr = TIMER_HPTIMER; 1404 treg = TIMER_REG_CVAL; 1405 break; 1406 1407 case SYS_CNTHV_CVAL_EL2: 1408 tmr = TIMER_HVTIMER; 1409 treg = TIMER_REG_CVAL; 1410 break; 1411 1412 case SYS_CNTPCT_EL0: 1413 case SYS_CNTPCTSS_EL0: 1414 if (is_hyp_ctxt(vcpu)) 1415 tmr = TIMER_HPTIMER; 1416 else 1417 tmr = TIMER_PTIMER; 1418 treg = TIMER_REG_CNT; 1419 break; 1420 1421 case SYS_AARCH32_CNTPCT: 1422 case SYS_AARCH32_CNTPCTSS: 1423 tmr = TIMER_PTIMER; 1424 treg = TIMER_REG_CNT; 1425 break; 1426 1427 case SYS_CNTVCT_EL0: 1428 case SYS_CNTVCTSS_EL0: 1429 if (is_hyp_ctxt(vcpu)) 1430 tmr = TIMER_HVTIMER; 1431 else 1432 tmr = TIMER_VTIMER; 1433 treg = TIMER_REG_CNT; 1434 break; 1435 1436 case SYS_AARCH32_CNTVCT: 1437 case SYS_AARCH32_CNTVCTSS: 1438 tmr = TIMER_VTIMER; 1439 treg = TIMER_REG_CNT; 1440 break; 1441 1442 default: 1443 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register"); 1444 return undef_access(vcpu, p, r); 1445 } 1446 1447 if (p->is_write) 1448 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1449 else 1450 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1451 1452 return true; 1453 } 1454 1455 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, 1456 s64 new, s64 cur) 1457 { 1458 struct arm64_ftr_bits kvm_ftr = *ftrp; 1459 1460 /* Some features have different safe value type in KVM than host features */ 1461 switch (id) { 1462 case SYS_ID_AA64DFR0_EL1: 1463 switch (kvm_ftr.shift) { 1464 case ID_AA64DFR0_EL1_PMUVer_SHIFT: 1465 kvm_ftr.type = FTR_LOWER_SAFE; 1466 break; 1467 case ID_AA64DFR0_EL1_DebugVer_SHIFT: 1468 kvm_ftr.type = FTR_LOWER_SAFE; 1469 break; 1470 } 1471 break; 1472 case SYS_ID_DFR0_EL1: 1473 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) 1474 kvm_ftr.type = FTR_LOWER_SAFE; 1475 break; 1476 } 1477 1478 return arm64_ftr_safe_value(&kvm_ftr, new, cur); 1479 } 1480 1481 /* 1482 * arm64_check_features() - Check if a feature register value constitutes 1483 * a subset of features indicated by the idreg's KVM sanitised limit. 1484 * 1485 * This function will check if each feature field of @val is the "safe" value 1486 * against idreg's KVM sanitised limit return from reset() callback. 1487 * If a field value in @val is the same as the one in limit, it is always 1488 * considered the safe value regardless For register fields that are not in 1489 * writable, only the value in limit is considered the safe value. 1490 * 1491 * Return: 0 if all the fields are safe. Otherwise, return negative errno. 1492 */ 1493 static int arm64_check_features(struct kvm_vcpu *vcpu, 1494 const struct sys_reg_desc *rd, 1495 u64 val) 1496 { 1497 const struct arm64_ftr_reg *ftr_reg; 1498 const struct arm64_ftr_bits *ftrp = NULL; 1499 u32 id = reg_to_encoding(rd); 1500 u64 writable_mask = rd->val; 1501 u64 limit = rd->reset(vcpu, rd); 1502 u64 mask = 0; 1503 1504 /* 1505 * Hidden and unallocated ID registers may not have a corresponding 1506 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the 1507 * only safe value is 0. 1508 */ 1509 if (sysreg_visible_as_raz(vcpu, rd)) 1510 return val ? -E2BIG : 0; 1511 1512 ftr_reg = get_arm64_ftr_reg(id); 1513 if (!ftr_reg) 1514 return -EINVAL; 1515 1516 ftrp = ftr_reg->ftr_bits; 1517 1518 for (; ftrp && ftrp->width; ftrp++) { 1519 s64 f_val, f_lim, safe_val; 1520 u64 ftr_mask; 1521 1522 ftr_mask = arm64_ftr_mask(ftrp); 1523 if ((ftr_mask & writable_mask) != ftr_mask) 1524 continue; 1525 1526 f_val = arm64_ftr_value(ftrp, val); 1527 f_lim = arm64_ftr_value(ftrp, limit); 1528 mask |= ftr_mask; 1529 1530 if (f_val == f_lim) 1531 safe_val = f_val; 1532 else 1533 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim); 1534 1535 if (safe_val != f_val) 1536 return -E2BIG; 1537 } 1538 1539 /* For fields that are not writable, values in limit are the safe values. */ 1540 if ((val & ~mask) != (limit & ~mask)) 1541 return -E2BIG; 1542 1543 return 0; 1544 } 1545 1546 static u8 pmuver_to_perfmon(u8 pmuver) 1547 { 1548 switch (pmuver) { 1549 case ID_AA64DFR0_EL1_PMUVer_IMP: 1550 return ID_DFR0_EL1_PerfMon_PMUv3; 1551 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF: 1552 return ID_DFR0_EL1_PerfMon_IMPDEF; 1553 default: 1554 /* Anything ARMv8.1+ and NI have the same value. For now. */ 1555 return pmuver; 1556 } 1557 } 1558 1559 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1560 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); 1561 1562 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1563 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 1564 const struct sys_reg_desc *r) 1565 { 1566 u32 id = reg_to_encoding(r); 1567 u64 val; 1568 1569 if (sysreg_visible_as_raz(vcpu, r)) 1570 return 0; 1571 1572 val = read_sanitised_ftr_reg(id); 1573 1574 switch (id) { 1575 case SYS_ID_AA64DFR0_EL1: 1576 val = sanitise_id_aa64dfr0_el1(vcpu, val); 1577 break; 1578 case SYS_ID_AA64PFR0_EL1: 1579 val = sanitise_id_aa64pfr0_el1(vcpu, val); 1580 break; 1581 case SYS_ID_AA64PFR1_EL1: 1582 if (!kvm_has_mte(vcpu->kvm)) 1583 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); 1584 1585 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); 1586 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); 1587 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); 1588 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac); 1589 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); 1590 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); 1591 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); 1592 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2); 1593 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); 1594 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac); 1595 break; 1596 case SYS_ID_AA64PFR2_EL1: 1597 /* We only expose FPMR */ 1598 val &= ID_AA64PFR2_EL1_FPMR; 1599 break; 1600 case SYS_ID_AA64ISAR1_EL1: 1601 if (!vcpu_has_ptrauth(vcpu)) 1602 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | 1603 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | 1604 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | 1605 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 1606 break; 1607 case SYS_ID_AA64ISAR2_EL1: 1608 if (!vcpu_has_ptrauth(vcpu)) 1609 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | 1610 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); 1611 if (!cpus_have_final_cap(ARM64_HAS_WFXT) || 1612 has_broken_cntvoff()) 1613 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); 1614 break; 1615 case SYS_ID_AA64ISAR3_EL1: 1616 val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; 1617 break; 1618 case SYS_ID_AA64MMFR2_EL1: 1619 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; 1620 break; 1621 case SYS_ID_AA64MMFR3_EL1: 1622 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | 1623 ID_AA64MMFR3_EL1_S1PIE; 1624 break; 1625 case SYS_ID_MMFR4_EL1: 1626 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); 1627 break; 1628 } 1629 1630 return val; 1631 } 1632 1633 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu, 1634 const struct sys_reg_desc *r) 1635 { 1636 return __kvm_read_sanitised_id_reg(vcpu, r); 1637 } 1638 1639 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 1640 { 1641 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r)); 1642 } 1643 1644 static bool is_feature_id_reg(u32 encoding) 1645 { 1646 return (sys_reg_Op0(encoding) == 3 && 1647 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && 1648 sys_reg_CRn(encoding) == 0 && 1649 sys_reg_CRm(encoding) <= 7); 1650 } 1651 1652 /* 1653 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is 1654 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID 1655 * registers KVM maintains on a per-VM basis. 1656 */ 1657 static inline bool is_vm_ftr_id_reg(u32 id) 1658 { 1659 if (id == SYS_CTR_EL0) 1660 return true; 1661 1662 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1663 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1664 sys_reg_CRm(id) < 8); 1665 } 1666 1667 static inline bool is_vcpu_ftr_id_reg(u32 id) 1668 { 1669 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id); 1670 } 1671 1672 static inline bool is_aa32_id_reg(u32 id) 1673 { 1674 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && 1675 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && 1676 sys_reg_CRm(id) <= 3); 1677 } 1678 1679 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1680 const struct sys_reg_desc *r) 1681 { 1682 u32 id = reg_to_encoding(r); 1683 1684 switch (id) { 1685 case SYS_ID_AA64ZFR0_EL1: 1686 if (!vcpu_has_sve(vcpu)) 1687 return REG_RAZ; 1688 break; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu, 1695 const struct sys_reg_desc *r) 1696 { 1697 /* 1698 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any 1699 * EL. Promote to RAZ/WI in order to guarantee consistency between 1700 * systems. 1701 */ 1702 if (!kvm_supports_32bit_el0()) 1703 return REG_RAZ | REG_USER_WI; 1704 1705 return id_visibility(vcpu, r); 1706 } 1707 1708 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, 1709 const struct sys_reg_desc *r) 1710 { 1711 return REG_RAZ; 1712 } 1713 1714 /* cpufeature ID register access trap handlers */ 1715 1716 static bool access_id_reg(struct kvm_vcpu *vcpu, 1717 struct sys_reg_params *p, 1718 const struct sys_reg_desc *r) 1719 { 1720 if (p->is_write) 1721 return write_to_read_only(vcpu, p, r); 1722 1723 p->regval = read_id_reg(vcpu, r); 1724 1725 return true; 1726 } 1727 1728 /* Visibility overrides for SVE-specific control registers */ 1729 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1730 const struct sys_reg_desc *rd) 1731 { 1732 if (vcpu_has_sve(vcpu)) 1733 return 0; 1734 1735 return REG_HIDDEN; 1736 } 1737 1738 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, 1739 const struct sys_reg_desc *rd) 1740 { 1741 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) 1742 return 0; 1743 1744 return REG_HIDDEN; 1745 } 1746 1747 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, 1748 const struct sys_reg_desc *rd) 1749 { 1750 if (kvm_has_fpmr(vcpu->kvm)) 1751 return 0; 1752 1753 return REG_HIDDEN; 1754 } 1755 1756 static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1757 { 1758 if (!vcpu_has_sve(vcpu)) 1759 val &= ~ID_AA64PFR0_EL1_SVE_MASK; 1760 1761 /* 1762 * The default is to expose CSV2 == 1 if the HW isn't affected. 1763 * Although this is a per-CPU feature, we make it global because 1764 * asymmetric systems are just a nuisance. 1765 * 1766 * Userspace can override this as long as it doesn't promise 1767 * the impossible. 1768 */ 1769 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) { 1770 val &= ~ID_AA64PFR0_EL1_CSV2_MASK; 1771 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP); 1772 } 1773 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) { 1774 val &= ~ID_AA64PFR0_EL1_CSV3_MASK; 1775 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); 1776 } 1777 1778 if (kvm_vgic_global_state.type == VGIC_V3) { 1779 val &= ~ID_AA64PFR0_EL1_GIC_MASK; 1780 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); 1781 } 1782 1783 val &= ~ID_AA64PFR0_EL1_AMU_MASK; 1784 1785 /* 1786 * MPAM is disabled by default as KVM also needs a set of PARTID to 1787 * program the MPAMVPMx_EL2 PARTID remapping registers with. But some 1788 * older kernels let the guest see the ID bit. 1789 */ 1790 val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1791 1792 return val; 1793 } 1794 1795 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ 1796 ({ \ 1797 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ 1798 (val) &= ~reg##_##field##_MASK; \ 1799 (val) |= FIELD_PREP(reg##_##field##_MASK, \ 1800 min(__f_val, \ 1801 (u64)SYS_FIELD_VALUE(reg, field, limit))); \ 1802 (val); \ 1803 }) 1804 1805 static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) 1806 { 1807 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); 1808 1809 /* 1810 * Only initialize the PMU version if the vCPU was configured with one. 1811 */ 1812 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1813 if (kvm_vcpu_has_pmu(vcpu)) 1814 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, 1815 kvm_arm_pmu_get_pmuver_limit()); 1816 1817 /* Hide SPE from guests */ 1818 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; 1819 1820 /* Hide BRBE from guests */ 1821 val &= ~ID_AA64DFR0_EL1_BRBE_MASK; 1822 1823 return val; 1824 } 1825 1826 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, 1827 const struct sys_reg_desc *rd, 1828 u64 val) 1829 { 1830 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); 1831 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); 1832 1833 /* 1834 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the 1835 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously 1836 * exposed an IMP_DEF PMU to userspace and the guest on systems w/ 1837 * non-architectural PMUs. Of course, PMUv3 is the only game in town for 1838 * PMU virtualization, so the IMP_DEF value was rather user-hostile. 1839 * 1840 * At minimum, we're on the hook to allow values that were given to 1841 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value 1842 * with a more sensible NI. The value of an ID register changing under 1843 * the nose of the guest is unfortunate, but is certainly no more 1844 * surprising than an ill-guided PMU driver poking at impdef system 1845 * registers that end in an UNDEF... 1846 */ 1847 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1848 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; 1849 1850 /* 1851 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a 1852 * nonzero minimum safe value. 1853 */ 1854 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) 1855 return -EINVAL; 1856 1857 return set_id_reg(vcpu, rd, val); 1858 } 1859 1860 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, 1861 const struct sys_reg_desc *rd) 1862 { 1863 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 1864 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); 1865 1866 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1867 if (kvm_vcpu_has_pmu(vcpu)) 1868 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); 1869 1870 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); 1871 1872 return val; 1873 } 1874 1875 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, 1876 const struct sys_reg_desc *rd, 1877 u64 val) 1878 { 1879 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); 1880 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); 1881 1882 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { 1883 val &= ~ID_DFR0_EL1_PerfMon_MASK; 1884 perfmon = 0; 1885 } 1886 1887 /* 1888 * Allow DFR0_EL1.PerfMon to be set from userspace as long as 1889 * it doesn't promise more than what the HW gives us on the 1890 * AArch64 side (as everything is emulated with that), and 1891 * that this is a PMUv3. 1892 */ 1893 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) 1894 return -EINVAL; 1895 1896 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) 1897 return -EINVAL; 1898 1899 return set_id_reg(vcpu, rd, val); 1900 } 1901 1902 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1903 const struct sys_reg_desc *rd, u64 user_val) 1904 { 1905 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1906 u64 mpam_mask = ID_AA64PFR0_EL1_MPAM_MASK; 1907 1908 /* 1909 * Commit 011e5f5bf529f ("arm64/cpufeature: Add remaining feature bits 1910 * in ID_AA64PFR0 register") exposed the MPAM field of AA64PFR0_EL1 to 1911 * guests, but didn't add trap handling. KVM doesn't support MPAM and 1912 * always returns an UNDEF for these registers. The guest must see 0 1913 * for this field. 1914 * 1915 * But KVM must also accept values from user-space that were provided 1916 * by KVM. On CPUs that support MPAM, permit user-space to write 1917 * the sanitizied value to ID_AA64PFR0_EL1.MPAM, but ignore this field. 1918 */ 1919 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1920 user_val &= ~ID_AA64PFR0_EL1_MPAM_MASK; 1921 1922 return set_id_reg(vcpu, rd, user_val); 1923 } 1924 1925 static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, 1926 const struct sys_reg_desc *rd, u64 user_val) 1927 { 1928 u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1929 u64 mpam_mask = ID_AA64PFR1_EL1_MPAM_frac_MASK; 1930 1931 /* See set_id_aa64pfr0_el1 for comment about MPAM */ 1932 if ((hw_val & mpam_mask) == (user_val & mpam_mask)) 1933 user_val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK; 1934 1935 return set_id_reg(vcpu, rd, user_val); 1936 } 1937 1938 static int set_ctr_el0(struct kvm_vcpu *vcpu, 1939 const struct sys_reg_desc *rd, u64 user_val) 1940 { 1941 u8 user_L1Ip = SYS_FIELD_GET(CTR_EL0, L1Ip, user_val); 1942 1943 /* 1944 * Both AIVIVT (0b01) and VPIPT (0b00) are documented as reserved. 1945 * Hence only allow to set VIPT(0b10) or PIPT(0b11) for L1Ip based 1946 * on what hardware reports. 1947 * 1948 * Using a VIPT software model on PIPT will lead to over invalidation, 1949 * but still correct. Hence, we can allow downgrading PIPT to VIPT, 1950 * but not the other way around. This is handled via arm64_ftr_safe_value() 1951 * as CTR_EL0 ftr_bits has L1Ip field with type FTR_EXACT and safe value 1952 * set as VIPT. 1953 */ 1954 switch (user_L1Ip) { 1955 case CTR_EL0_L1Ip_RESERVED_VPIPT: 1956 case CTR_EL0_L1Ip_RESERVED_AIVIVT: 1957 return -EINVAL; 1958 case CTR_EL0_L1Ip_VIPT: 1959 case CTR_EL0_L1Ip_PIPT: 1960 return set_id_reg(vcpu, rd, user_val); 1961 default: 1962 return -ENOENT; 1963 } 1964 } 1965 1966 /* 1967 * cpufeature ID register user accessors 1968 * 1969 * For now, these registers are immutable for userspace, so no values 1970 * are stored, and for set_id_reg() we don't allow the effective value 1971 * to be changed. 1972 */ 1973 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1974 u64 *val) 1975 { 1976 /* 1977 * Avoid locking if the VM has already started, as the ID registers are 1978 * guaranteed to be invariant at that point. 1979 */ 1980 if (kvm_vm_has_ran_once(vcpu->kvm)) { 1981 *val = read_id_reg(vcpu, rd); 1982 return 0; 1983 } 1984 1985 mutex_lock(&vcpu->kvm->arch.config_lock); 1986 *val = read_id_reg(vcpu, rd); 1987 mutex_unlock(&vcpu->kvm->arch.config_lock); 1988 1989 return 0; 1990 } 1991 1992 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1993 u64 val) 1994 { 1995 u32 id = reg_to_encoding(rd); 1996 int ret; 1997 1998 mutex_lock(&vcpu->kvm->arch.config_lock); 1999 2000 /* 2001 * Once the VM has started the ID registers are immutable. Reject any 2002 * write that does not match the final register value. 2003 */ 2004 if (kvm_vm_has_ran_once(vcpu->kvm)) { 2005 if (val != read_id_reg(vcpu, rd)) 2006 ret = -EBUSY; 2007 else 2008 ret = 0; 2009 2010 mutex_unlock(&vcpu->kvm->arch.config_lock); 2011 return ret; 2012 } 2013 2014 ret = arm64_check_features(vcpu, rd, val); 2015 if (!ret) 2016 kvm_set_vm_id_reg(vcpu->kvm, id, val); 2017 2018 mutex_unlock(&vcpu->kvm->arch.config_lock); 2019 2020 /* 2021 * arm64_check_features() returns -E2BIG to indicate the register's 2022 * feature set is a superset of the maximally-allowed register value. 2023 * While it would be nice to precisely describe this to userspace, the 2024 * existing UAPI for KVM_SET_ONE_REG has it that invalid register 2025 * writes return -EINVAL. 2026 */ 2027 if (ret == -E2BIG) 2028 ret = -EINVAL; 2029 return ret; 2030 } 2031 2032 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val) 2033 { 2034 u64 *p = __vm_id_reg(&kvm->arch, reg); 2035 2036 lockdep_assert_held(&kvm->arch.config_lock); 2037 2038 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm)) 2039 return; 2040 2041 *p = val; 2042 } 2043 2044 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2045 u64 *val) 2046 { 2047 *val = 0; 2048 return 0; 2049 } 2050 2051 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2052 u64 val) 2053 { 2054 return 0; 2055 } 2056 2057 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2058 const struct sys_reg_desc *r) 2059 { 2060 if (p->is_write) 2061 return write_to_read_only(vcpu, p, r); 2062 2063 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0); 2064 return true; 2065 } 2066 2067 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2068 const struct sys_reg_desc *r) 2069 { 2070 if (p->is_write) 2071 return write_to_read_only(vcpu, p, r); 2072 2073 p->regval = __vcpu_sys_reg(vcpu, r->reg); 2074 return true; 2075 } 2076 2077 /* 2078 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary 2079 * by the physical CPU which the vcpu currently resides in. 2080 */ 2081 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2082 { 2083 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2084 u64 clidr; 2085 u8 loc; 2086 2087 if ((ctr_el0 & CTR_EL0_IDC)) { 2088 /* 2089 * Data cache clean to the PoU is not required so LoUU and LoUIS 2090 * will not be set and a unified cache, which will be marked as 2091 * LoC, will be added. 2092 * 2093 * If not DIC, let the unified cache L2 so that an instruction 2094 * cache can be added as L1 later. 2095 */ 2096 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; 2097 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); 2098 } else { 2099 /* 2100 * Data cache clean to the PoU is required so let L1 have a data 2101 * cache and mark it as LoUU and LoUIS. As L1 has a data cache, 2102 * it can be marked as LoC too. 2103 */ 2104 loc = 1; 2105 clidr = 1 << CLIDR_LOUU_SHIFT; 2106 clidr |= 1 << CLIDR_LOUIS_SHIFT; 2107 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); 2108 } 2109 2110 /* 2111 * Instruction cache invalidation to the PoU is required so let L1 have 2112 * an instruction cache. If L1 already has a data cache, it will be 2113 * CACHE_TYPE_SEPARATE. 2114 */ 2115 if (!(ctr_el0 & CTR_EL0_DIC)) 2116 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); 2117 2118 clidr |= loc << CLIDR_LOC_SHIFT; 2119 2120 /* 2121 * Add tag cache unified to data cache. Allocation tags and data are 2122 * unified in a cache line so that it looks valid even if there is only 2123 * one cache line. 2124 */ 2125 if (kvm_has_mte(vcpu->kvm)) 2126 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); 2127 2128 __vcpu_sys_reg(vcpu, r->reg) = clidr; 2129 2130 return __vcpu_sys_reg(vcpu, r->reg); 2131 } 2132 2133 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 2134 u64 val) 2135 { 2136 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); 2137 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); 2138 2139 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) 2140 return -EINVAL; 2141 2142 __vcpu_sys_reg(vcpu, rd->reg) = val; 2143 2144 return 0; 2145 } 2146 2147 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2148 const struct sys_reg_desc *r) 2149 { 2150 int reg = r->reg; 2151 2152 if (p->is_write) 2153 vcpu_write_sys_reg(vcpu, p->regval, reg); 2154 else 2155 p->regval = vcpu_read_sys_reg(vcpu, reg); 2156 return true; 2157 } 2158 2159 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 2160 const struct sys_reg_desc *r) 2161 { 2162 u32 csselr; 2163 2164 if (p->is_write) 2165 return write_to_read_only(vcpu, p, r); 2166 2167 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 2168 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD; 2169 if (csselr < CSSELR_MAX) 2170 p->regval = get_ccsidr(vcpu, csselr); 2171 2172 return true; 2173 } 2174 2175 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu, 2176 const struct sys_reg_desc *rd) 2177 { 2178 if (kvm_has_mte(vcpu->kvm)) 2179 return 0; 2180 2181 return REG_HIDDEN; 2182 } 2183 2184 #define MTE_REG(name) { \ 2185 SYS_DESC(SYS_##name), \ 2186 .access = undef_access, \ 2187 .reset = reset_unknown, \ 2188 .reg = name, \ 2189 .visibility = mte_visibility, \ 2190 } 2191 2192 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 2193 const struct sys_reg_desc *rd) 2194 { 2195 if (vcpu_has_nv(vcpu)) 2196 return 0; 2197 2198 return REG_HIDDEN; 2199 } 2200 2201 static bool bad_vncr_trap(struct kvm_vcpu *vcpu, 2202 struct sys_reg_params *p, 2203 const struct sys_reg_desc *r) 2204 { 2205 /* 2206 * We really shouldn't be here, and this is likely the result 2207 * of a misconfigured trap, as this register should target the 2208 * VNCR page, and nothing else. 2209 */ 2210 return bad_trap(vcpu, p, r, 2211 "trap of VNCR-backed register"); 2212 } 2213 2214 static bool bad_redir_trap(struct kvm_vcpu *vcpu, 2215 struct sys_reg_params *p, 2216 const struct sys_reg_desc *r) 2217 { 2218 /* 2219 * We really shouldn't be here, and this is likely the result 2220 * of a misconfigured trap, as this register should target the 2221 * corresponding EL1, and nothing else. 2222 */ 2223 return bad_trap(vcpu, p, r, 2224 "trap of EL2 register redirected to EL1"); 2225 } 2226 2227 #define EL2_REG(name, acc, rst, v) { \ 2228 SYS_DESC(SYS_##name), \ 2229 .access = acc, \ 2230 .reset = rst, \ 2231 .reg = name, \ 2232 .visibility = el2_visibility, \ 2233 .val = v, \ 2234 } 2235 2236 #define EL2_REG_FILTERED(name, acc, rst, v, filter) { \ 2237 SYS_DESC(SYS_##name), \ 2238 .access = acc, \ 2239 .reset = rst, \ 2240 .reg = name, \ 2241 .visibility = filter, \ 2242 .val = v, \ 2243 } 2244 2245 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v) 2246 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v) 2247 2248 /* 2249 * Since reset() callback and field val are not used for idregs, they will be 2250 * used for specific purposes for idregs. 2251 * The reset() would return KVM sanitised register value. The value would be the 2252 * same as the host kernel sanitised value if there is no KVM sanitisation. 2253 * The val would be used as a mask indicating writable fields for the idreg. 2254 * Only bits with 1 are writable from userspace. This mask might not be 2255 * necessary in the future whenever all ID registers are enabled as writable 2256 * from userspace. 2257 */ 2258 2259 #define ID_DESC(name) \ 2260 SYS_DESC(SYS_##name), \ 2261 .access = access_id_reg, \ 2262 .get_user = get_id_reg \ 2263 2264 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2265 #define ID_SANITISED(name) { \ 2266 ID_DESC(name), \ 2267 .set_user = set_id_reg, \ 2268 .visibility = id_visibility, \ 2269 .reset = kvm_read_sanitised_id_reg, \ 2270 .val = 0, \ 2271 } 2272 2273 /* sys_reg_desc initialiser for known cpufeature ID registers */ 2274 #define AA32_ID_SANITISED(name) { \ 2275 ID_DESC(name), \ 2276 .set_user = set_id_reg, \ 2277 .visibility = aa32_id_visibility, \ 2278 .reset = kvm_read_sanitised_id_reg, \ 2279 .val = 0, \ 2280 } 2281 2282 /* sys_reg_desc initialiser for writable ID registers */ 2283 #define ID_WRITABLE(name, mask) { \ 2284 ID_DESC(name), \ 2285 .set_user = set_id_reg, \ 2286 .visibility = id_visibility, \ 2287 .reset = kvm_read_sanitised_id_reg, \ 2288 .val = mask, \ 2289 } 2290 2291 /* sys_reg_desc initialiser for cpufeature ID registers that need filtering */ 2292 #define ID_FILTERED(sysreg, name, mask) { \ 2293 ID_DESC(sysreg), \ 2294 .set_user = set_##name, \ 2295 .visibility = id_visibility, \ 2296 .reset = kvm_read_sanitised_id_reg, \ 2297 .val = (mask), \ 2298 } 2299 2300 /* 2301 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 2302 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 2303 * (1 <= crm < 8, 0 <= Op2 < 8). 2304 */ 2305 #define ID_UNALLOCATED(crm, op2) { \ 2306 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 2307 .access = access_id_reg, \ 2308 .get_user = get_id_reg, \ 2309 .set_user = set_id_reg, \ 2310 .visibility = raz_visibility, \ 2311 .reset = kvm_read_sanitised_id_reg, \ 2312 .val = 0, \ 2313 } 2314 2315 /* 2316 * sys_reg_desc initialiser for known ID registers that we hide from guests. 2317 * For now, these are exposed just like unallocated ID regs: they appear 2318 * RAZ for the guest. 2319 */ 2320 #define ID_HIDDEN(name) { \ 2321 ID_DESC(name), \ 2322 .set_user = set_id_reg, \ 2323 .visibility = raz_visibility, \ 2324 .reset = kvm_read_sanitised_id_reg, \ 2325 .val = 0, \ 2326 } 2327 2328 static bool access_sp_el1(struct kvm_vcpu *vcpu, 2329 struct sys_reg_params *p, 2330 const struct sys_reg_desc *r) 2331 { 2332 if (p->is_write) 2333 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval; 2334 else 2335 p->regval = __vcpu_sys_reg(vcpu, SP_EL1); 2336 2337 return true; 2338 } 2339 2340 static bool access_elr(struct kvm_vcpu *vcpu, 2341 struct sys_reg_params *p, 2342 const struct sys_reg_desc *r) 2343 { 2344 if (p->is_write) 2345 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); 2346 else 2347 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1); 2348 2349 return true; 2350 } 2351 2352 static bool access_spsr(struct kvm_vcpu *vcpu, 2353 struct sys_reg_params *p, 2354 const struct sys_reg_desc *r) 2355 { 2356 if (p->is_write) 2357 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval; 2358 else 2359 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1); 2360 2361 return true; 2362 } 2363 2364 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu, 2365 struct sys_reg_params *p, 2366 const struct sys_reg_desc *r) 2367 { 2368 if (p->is_write) 2369 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval; 2370 else 2371 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1); 2372 2373 return true; 2374 } 2375 2376 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 2377 { 2378 u64 val = r->val; 2379 2380 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1)) 2381 val |= HCR_E2H; 2382 2383 return __vcpu_sys_reg(vcpu, r->reg) = val; 2384 } 2385 2386 static unsigned int __el2_visibility(const struct kvm_vcpu *vcpu, 2387 const struct sys_reg_desc *rd, 2388 unsigned int (*fn)(const struct kvm_vcpu *, 2389 const struct sys_reg_desc *)) 2390 { 2391 return el2_visibility(vcpu, rd) ?: fn(vcpu, rd); 2392 } 2393 2394 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu, 2395 const struct sys_reg_desc *rd) 2396 { 2397 return __el2_visibility(vcpu, rd, sve_visibility); 2398 } 2399 2400 static bool access_zcr_el2(struct kvm_vcpu *vcpu, 2401 struct sys_reg_params *p, 2402 const struct sys_reg_desc *r) 2403 { 2404 unsigned int vq; 2405 2406 if (guest_hyp_sve_traps_enabled(vcpu)) { 2407 kvm_inject_nested_sve_trap(vcpu); 2408 return true; 2409 } 2410 2411 if (!p->is_write) { 2412 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2); 2413 return true; 2414 } 2415 2416 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1; 2417 vq = min(vq, vcpu_sve_max_vq(vcpu)); 2418 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2); 2419 return true; 2420 } 2421 2422 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu, 2423 const struct sys_reg_desc *rd) 2424 { 2425 if (kvm_has_s1poe(vcpu->kvm)) 2426 return 0; 2427 2428 return REG_HIDDEN; 2429 } 2430 2431 static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu, 2432 const struct sys_reg_desc *rd) 2433 { 2434 return __el2_visibility(vcpu, rd, s1poe_visibility); 2435 } 2436 2437 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu, 2438 const struct sys_reg_desc *rd) 2439 { 2440 if (kvm_has_tcr2(vcpu->kvm)) 2441 return 0; 2442 2443 return REG_HIDDEN; 2444 } 2445 2446 static unsigned int tcr2_el2_visibility(const struct kvm_vcpu *vcpu, 2447 const struct sys_reg_desc *rd) 2448 { 2449 return __el2_visibility(vcpu, rd, tcr2_visibility); 2450 } 2451 2452 static unsigned int s1pie_visibility(const struct kvm_vcpu *vcpu, 2453 const struct sys_reg_desc *rd) 2454 { 2455 if (kvm_has_s1pie(vcpu->kvm)) 2456 return 0; 2457 2458 return REG_HIDDEN; 2459 } 2460 2461 static unsigned int s1pie_el2_visibility(const struct kvm_vcpu *vcpu, 2462 const struct sys_reg_desc *rd) 2463 { 2464 return __el2_visibility(vcpu, rd, s1pie_visibility); 2465 } 2466 2467 static bool access_mdcr(struct kvm_vcpu *vcpu, 2468 struct sys_reg_params *p, 2469 const struct sys_reg_desc *r) 2470 { 2471 u64 old = __vcpu_sys_reg(vcpu, MDCR_EL2); 2472 2473 if (!access_rw(vcpu, p, r)) 2474 return false; 2475 2476 /* 2477 * Request a reload of the PMU to enable/disable the counters affected 2478 * by HPME. 2479 */ 2480 if ((old ^ __vcpu_sys_reg(vcpu, MDCR_EL2)) & MDCR_EL2_HPME) 2481 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 2482 2483 return true; 2484 } 2485 2486 2487 /* 2488 * Architected system registers. 2489 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 2490 * 2491 * Debug handling: We do trap most, if not all debug related system 2492 * registers. The implementation is good enough to ensure that a guest 2493 * can use these with minimal performance degradation. The drawback is 2494 * that we don't implement any of the external debug architecture. 2495 * This should be revisited if we ever encounter a more demanding 2496 * guest... 2497 */ 2498 static const struct sys_reg_desc sys_reg_descs[] = { 2499 DBG_BCR_BVR_WCR_WVR_EL1(0), 2500 DBG_BCR_BVR_WCR_WVR_EL1(1), 2501 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 2502 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 2503 DBG_BCR_BVR_WCR_WVR_EL1(2), 2504 DBG_BCR_BVR_WCR_WVR_EL1(3), 2505 DBG_BCR_BVR_WCR_WVR_EL1(4), 2506 DBG_BCR_BVR_WCR_WVR_EL1(5), 2507 DBG_BCR_BVR_WCR_WVR_EL1(6), 2508 DBG_BCR_BVR_WCR_WVR_EL1(7), 2509 DBG_BCR_BVR_WCR_WVR_EL1(8), 2510 DBG_BCR_BVR_WCR_WVR_EL1(9), 2511 DBG_BCR_BVR_WCR_WVR_EL1(10), 2512 DBG_BCR_BVR_WCR_WVR_EL1(11), 2513 DBG_BCR_BVR_WCR_WVR_EL1(12), 2514 DBG_BCR_BVR_WCR_WVR_EL1(13), 2515 DBG_BCR_BVR_WCR_WVR_EL1(14), 2516 DBG_BCR_BVR_WCR_WVR_EL1(15), 2517 2518 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 2519 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, 2520 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, 2521 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, 2522 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 2523 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 2524 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 2525 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 2526 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 2527 2528 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 2529 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 2530 // DBGDTR[TR]X_EL0 share the same encoding 2531 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 2532 2533 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 }, 2534 2535 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 2536 2537 /* 2538 * ID regs: all ID_SANITISED() entries here must have corresponding 2539 * entries in arm64_ftr_regs[]. 2540 */ 2541 2542 /* AArch64 mappings of the AArch32 ID registers */ 2543 /* CRm=1 */ 2544 AA32_ID_SANITISED(ID_PFR0_EL1), 2545 AA32_ID_SANITISED(ID_PFR1_EL1), 2546 { SYS_DESC(SYS_ID_DFR0_EL1), 2547 .access = access_id_reg, 2548 .get_user = get_id_reg, 2549 .set_user = set_id_dfr0_el1, 2550 .visibility = aa32_id_visibility, 2551 .reset = read_sanitised_id_dfr0_el1, 2552 .val = ID_DFR0_EL1_PerfMon_MASK | 2553 ID_DFR0_EL1_CopDbg_MASK, }, 2554 ID_HIDDEN(ID_AFR0_EL1), 2555 AA32_ID_SANITISED(ID_MMFR0_EL1), 2556 AA32_ID_SANITISED(ID_MMFR1_EL1), 2557 AA32_ID_SANITISED(ID_MMFR2_EL1), 2558 AA32_ID_SANITISED(ID_MMFR3_EL1), 2559 2560 /* CRm=2 */ 2561 AA32_ID_SANITISED(ID_ISAR0_EL1), 2562 AA32_ID_SANITISED(ID_ISAR1_EL1), 2563 AA32_ID_SANITISED(ID_ISAR2_EL1), 2564 AA32_ID_SANITISED(ID_ISAR3_EL1), 2565 AA32_ID_SANITISED(ID_ISAR4_EL1), 2566 AA32_ID_SANITISED(ID_ISAR5_EL1), 2567 AA32_ID_SANITISED(ID_MMFR4_EL1), 2568 AA32_ID_SANITISED(ID_ISAR6_EL1), 2569 2570 /* CRm=3 */ 2571 AA32_ID_SANITISED(MVFR0_EL1), 2572 AA32_ID_SANITISED(MVFR1_EL1), 2573 AA32_ID_SANITISED(MVFR2_EL1), 2574 ID_UNALLOCATED(3,3), 2575 AA32_ID_SANITISED(ID_PFR2_EL1), 2576 ID_HIDDEN(ID_DFR1_EL1), 2577 AA32_ID_SANITISED(ID_MMFR5_EL1), 2578 ID_UNALLOCATED(3,7), 2579 2580 /* AArch64 ID registers */ 2581 /* CRm=4 */ 2582 ID_FILTERED(ID_AA64PFR0_EL1, id_aa64pfr0_el1, 2583 ~(ID_AA64PFR0_EL1_AMU | 2584 ID_AA64PFR0_EL1_MPAM | 2585 ID_AA64PFR0_EL1_SVE | 2586 ID_AA64PFR0_EL1_RAS | 2587 ID_AA64PFR0_EL1_AdvSIMD | 2588 ID_AA64PFR0_EL1_FP)), 2589 ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1, 2590 ~(ID_AA64PFR1_EL1_PFAR | 2591 ID_AA64PFR1_EL1_DF2 | 2592 ID_AA64PFR1_EL1_MTEX | 2593 ID_AA64PFR1_EL1_THE | 2594 ID_AA64PFR1_EL1_GCS | 2595 ID_AA64PFR1_EL1_MTE_frac | 2596 ID_AA64PFR1_EL1_NMI | 2597 ID_AA64PFR1_EL1_RNDR_trap | 2598 ID_AA64PFR1_EL1_SME | 2599 ID_AA64PFR1_EL1_RES0 | 2600 ID_AA64PFR1_EL1_MPAM_frac | 2601 ID_AA64PFR1_EL1_RAS_frac | 2602 ID_AA64PFR1_EL1_MTE)), 2603 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), 2604 ID_UNALLOCATED(4,3), 2605 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), 2606 ID_HIDDEN(ID_AA64SMFR0_EL1), 2607 ID_UNALLOCATED(4,6), 2608 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), 2609 2610 /* CRm=5 */ 2611 /* 2612 * Prior to FEAT_Debugv8.9, the architecture defines context-aware 2613 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs). 2614 * KVM does not trap + emulate the breakpoint registers, and as such 2615 * cannot support a layout that misaligns with the underlying hardware. 2616 * While it may be possible to describe a subset that aligns with 2617 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for 2618 * simplicity. 2619 * 2620 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking 2621 * of breakpoints for more details. 2622 */ 2623 ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, 2624 ID_AA64DFR0_EL1_DoubleLock_MASK | 2625 ID_AA64DFR0_EL1_WRPs_MASK | 2626 ID_AA64DFR0_EL1_PMUVer_MASK | 2627 ID_AA64DFR0_EL1_DebugVer_MASK), 2628 ID_SANITISED(ID_AA64DFR1_EL1), 2629 ID_UNALLOCATED(5,2), 2630 ID_UNALLOCATED(5,3), 2631 ID_HIDDEN(ID_AA64AFR0_EL1), 2632 ID_HIDDEN(ID_AA64AFR1_EL1), 2633 ID_UNALLOCATED(5,6), 2634 ID_UNALLOCATED(5,7), 2635 2636 /* CRm=6 */ 2637 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0), 2638 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI | 2639 ID_AA64ISAR1_EL1_GPA | 2640 ID_AA64ISAR1_EL1_API | 2641 ID_AA64ISAR1_EL1_APA)), 2642 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | 2643 ID_AA64ISAR2_EL1_APA3 | 2644 ID_AA64ISAR2_EL1_GPA3)), 2645 ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | 2646 ID_AA64ISAR3_EL1_FAMINMAX)), 2647 ID_UNALLOCATED(6,4), 2648 ID_UNALLOCATED(6,5), 2649 ID_UNALLOCATED(6,6), 2650 ID_UNALLOCATED(6,7), 2651 2652 /* CRm=7 */ 2653 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | 2654 ID_AA64MMFR0_EL1_TGRAN4_2 | 2655 ID_AA64MMFR0_EL1_TGRAN64_2 | 2656 ID_AA64MMFR0_EL1_TGRAN16_2 | 2657 ID_AA64MMFR0_EL1_ASIDBITS)), 2658 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | 2659 ID_AA64MMFR1_EL1_HCX | 2660 ID_AA64MMFR1_EL1_TWED | 2661 ID_AA64MMFR1_EL1_XNX | 2662 ID_AA64MMFR1_EL1_VH | 2663 ID_AA64MMFR1_EL1_VMIDBits)), 2664 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 | 2665 ID_AA64MMFR2_EL1_EVT | 2666 ID_AA64MMFR2_EL1_FWB | 2667 ID_AA64MMFR2_EL1_IDS | 2668 ID_AA64MMFR2_EL1_NV | 2669 ID_AA64MMFR2_EL1_CCIDX)), 2670 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | 2671 ID_AA64MMFR3_EL1_S1PIE | 2672 ID_AA64MMFR3_EL1_S1POE)), 2673 ID_SANITISED(ID_AA64MMFR4_EL1), 2674 ID_UNALLOCATED(7,5), 2675 ID_UNALLOCATED(7,6), 2676 ID_UNALLOCATED(7,7), 2677 2678 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 2679 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 2680 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 2681 2682 MTE_REG(RGSR_EL1), 2683 MTE_REG(GCR_EL1), 2684 2685 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 2686 { SYS_DESC(SYS_TRFCR_EL1), undef_access }, 2687 { SYS_DESC(SYS_SMPRI_EL1), undef_access }, 2688 { SYS_DESC(SYS_SMCR_EL1), undef_access }, 2689 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 2690 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 2691 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 2692 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0, 2693 .visibility = tcr2_visibility }, 2694 2695 PTRAUTH_KEY(APIA), 2696 PTRAUTH_KEY(APIB), 2697 PTRAUTH_KEY(APDA), 2698 PTRAUTH_KEY(APDB), 2699 PTRAUTH_KEY(APGA), 2700 2701 { SYS_DESC(SYS_SPSR_EL1), access_spsr}, 2702 { SYS_DESC(SYS_ELR_EL1), access_elr}, 2703 2704 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 2705 2706 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 2707 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 2708 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 2709 2710 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 2711 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 2712 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 2713 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 2714 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 2715 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 2716 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 2717 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 2718 2719 MTE_REG(TFSR_EL1), 2720 MTE_REG(TFSRE0_EL1), 2721 2722 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 2723 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 2724 2725 { SYS_DESC(SYS_PMSCR_EL1), undef_access }, 2726 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access }, 2727 { SYS_DESC(SYS_PMSICR_EL1), undef_access }, 2728 { SYS_DESC(SYS_PMSIRR_EL1), undef_access }, 2729 { SYS_DESC(SYS_PMSFCR_EL1), undef_access }, 2730 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access }, 2731 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access }, 2732 { SYS_DESC(SYS_PMSIDR_EL1), undef_access }, 2733 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, 2734 { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, 2735 { SYS_DESC(SYS_PMBSR_EL1), undef_access }, 2736 /* PMBIDR_EL1 is not trapped */ 2737 2738 { PMU_SYS_REG(PMINTENSET_EL1), 2739 .access = access_pminten, .reg = PMINTENSET_EL1, 2740 .get_user = get_pmreg, .set_user = set_pmreg }, 2741 { PMU_SYS_REG(PMINTENCLR_EL1), 2742 .access = access_pminten, .reg = PMINTENSET_EL1, 2743 .get_user = get_pmreg, .set_user = set_pmreg }, 2744 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi }, 2745 2746 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 2747 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1, 2748 .visibility = s1pie_visibility }, 2749 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1, 2750 .visibility = s1pie_visibility }, 2751 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1, 2752 .visibility = s1poe_visibility }, 2753 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 2754 2755 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 2756 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 2757 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 2758 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 2759 { SYS_DESC(SYS_MPAMIDR_EL1), undef_access }, 2760 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 2761 2762 { SYS_DESC(SYS_MPAM1_EL1), undef_access }, 2763 { SYS_DESC(SYS_MPAM0_EL1), undef_access }, 2764 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 }, 2765 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 2766 2767 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 2768 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 2769 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 2770 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 2771 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 2772 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 2773 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 2774 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 2775 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 2776 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 2777 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 2778 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 2779 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 2780 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 2781 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 2782 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 2783 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 2784 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 2785 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 2786 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 2787 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 2788 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 2789 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 2790 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 2791 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 2792 2793 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 2794 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 2795 2796 { SYS_DESC(SYS_ACCDATA_EL1), undef_access }, 2797 2798 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 2799 2800 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 2801 2802 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 2803 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, 2804 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 }, 2805 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, 2806 { SYS_DESC(SYS_SMIDR_EL1), undef_access }, 2807 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 2808 ID_FILTERED(CTR_EL0, ctr_el0, 2809 CTR_EL0_DIC_MASK | 2810 CTR_EL0_IDC_MASK | 2811 CTR_EL0_DminLine_MASK | 2812 CTR_EL0_L1Ip_MASK | 2813 CTR_EL0_IminLine_MASK), 2814 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, 2815 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, 2816 2817 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, 2818 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, 2819 { PMU_SYS_REG(PMCNTENSET_EL0), 2820 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2821 .get_user = get_pmreg, .set_user = set_pmreg }, 2822 { PMU_SYS_REG(PMCNTENCLR_EL0), 2823 .access = access_pmcnten, .reg = PMCNTENSET_EL0, 2824 .get_user = get_pmreg, .set_user = set_pmreg }, 2825 { PMU_SYS_REG(PMOVSCLR_EL0), 2826 .access = access_pmovs, .reg = PMOVSSET_EL0, 2827 .get_user = get_pmreg, .set_user = set_pmreg }, 2828 /* 2829 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was 2830 * previously (and pointlessly) advertised in the past... 2831 */ 2832 { PMU_SYS_REG(PMSWINC_EL0), 2833 .get_user = get_raz_reg, .set_user = set_wi_reg, 2834 .access = access_pmswinc, .reset = NULL }, 2835 { PMU_SYS_REG(PMSELR_EL0), 2836 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 }, 2837 { PMU_SYS_REG(PMCEID0_EL0), 2838 .access = access_pmceid, .reset = NULL }, 2839 { PMU_SYS_REG(PMCEID1_EL0), 2840 .access = access_pmceid, .reset = NULL }, 2841 { PMU_SYS_REG(PMCCNTR_EL0), 2842 .access = access_pmu_evcntr, .reset = reset_unknown, 2843 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr}, 2844 { PMU_SYS_REG(PMXEVTYPER_EL0), 2845 .access = access_pmu_evtyper, .reset = NULL }, 2846 { PMU_SYS_REG(PMXEVCNTR_EL0), 2847 .access = access_pmu_evcntr, .reset = NULL }, 2848 /* 2849 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 2850 * in 32bit mode. Here we choose to reset it as zero for consistency. 2851 */ 2852 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr, 2853 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 }, 2854 { PMU_SYS_REG(PMOVSSET_EL0), 2855 .access = access_pmovs, .reg = PMOVSSET_EL0, 2856 .get_user = get_pmreg, .set_user = set_pmreg }, 2857 2858 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0, 2859 .visibility = s1poe_visibility }, 2860 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 2861 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 2862 { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, 2863 2864 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 2865 2866 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 2867 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 2868 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 2869 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 2870 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 2871 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 2872 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 2873 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 2874 AMU_AMEVCNTR0_EL0(0), 2875 AMU_AMEVCNTR0_EL0(1), 2876 AMU_AMEVCNTR0_EL0(2), 2877 AMU_AMEVCNTR0_EL0(3), 2878 AMU_AMEVCNTR0_EL0(4), 2879 AMU_AMEVCNTR0_EL0(5), 2880 AMU_AMEVCNTR0_EL0(6), 2881 AMU_AMEVCNTR0_EL0(7), 2882 AMU_AMEVCNTR0_EL0(8), 2883 AMU_AMEVCNTR0_EL0(9), 2884 AMU_AMEVCNTR0_EL0(10), 2885 AMU_AMEVCNTR0_EL0(11), 2886 AMU_AMEVCNTR0_EL0(12), 2887 AMU_AMEVCNTR0_EL0(13), 2888 AMU_AMEVCNTR0_EL0(14), 2889 AMU_AMEVCNTR0_EL0(15), 2890 AMU_AMEVTYPER0_EL0(0), 2891 AMU_AMEVTYPER0_EL0(1), 2892 AMU_AMEVTYPER0_EL0(2), 2893 AMU_AMEVTYPER0_EL0(3), 2894 AMU_AMEVTYPER0_EL0(4), 2895 AMU_AMEVTYPER0_EL0(5), 2896 AMU_AMEVTYPER0_EL0(6), 2897 AMU_AMEVTYPER0_EL0(7), 2898 AMU_AMEVTYPER0_EL0(8), 2899 AMU_AMEVTYPER0_EL0(9), 2900 AMU_AMEVTYPER0_EL0(10), 2901 AMU_AMEVTYPER0_EL0(11), 2902 AMU_AMEVTYPER0_EL0(12), 2903 AMU_AMEVTYPER0_EL0(13), 2904 AMU_AMEVTYPER0_EL0(14), 2905 AMU_AMEVTYPER0_EL0(15), 2906 AMU_AMEVCNTR1_EL0(0), 2907 AMU_AMEVCNTR1_EL0(1), 2908 AMU_AMEVCNTR1_EL0(2), 2909 AMU_AMEVCNTR1_EL0(3), 2910 AMU_AMEVCNTR1_EL0(4), 2911 AMU_AMEVCNTR1_EL0(5), 2912 AMU_AMEVCNTR1_EL0(6), 2913 AMU_AMEVCNTR1_EL0(7), 2914 AMU_AMEVCNTR1_EL0(8), 2915 AMU_AMEVCNTR1_EL0(9), 2916 AMU_AMEVCNTR1_EL0(10), 2917 AMU_AMEVCNTR1_EL0(11), 2918 AMU_AMEVCNTR1_EL0(12), 2919 AMU_AMEVCNTR1_EL0(13), 2920 AMU_AMEVCNTR1_EL0(14), 2921 AMU_AMEVCNTR1_EL0(15), 2922 AMU_AMEVTYPER1_EL0(0), 2923 AMU_AMEVTYPER1_EL0(1), 2924 AMU_AMEVTYPER1_EL0(2), 2925 AMU_AMEVTYPER1_EL0(3), 2926 AMU_AMEVTYPER1_EL0(4), 2927 AMU_AMEVTYPER1_EL0(5), 2928 AMU_AMEVTYPER1_EL0(6), 2929 AMU_AMEVTYPER1_EL0(7), 2930 AMU_AMEVTYPER1_EL0(8), 2931 AMU_AMEVTYPER1_EL0(9), 2932 AMU_AMEVTYPER1_EL0(10), 2933 AMU_AMEVTYPER1_EL0(11), 2934 AMU_AMEVTYPER1_EL0(12), 2935 AMU_AMEVTYPER1_EL0(13), 2936 AMU_AMEVTYPER1_EL0(14), 2937 AMU_AMEVTYPER1_EL0(15), 2938 2939 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer }, 2940 { SYS_DESC(SYS_CNTVCT_EL0), access_arch_timer }, 2941 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer }, 2942 { SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer }, 2943 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 2944 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 2945 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 2946 2947 { SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer }, 2948 { SYS_DESC(SYS_CNTV_CTL_EL0), access_arch_timer }, 2949 { SYS_DESC(SYS_CNTV_CVAL_EL0), access_arch_timer }, 2950 2951 /* PMEVCNTRn_EL0 */ 2952 PMU_PMEVCNTR_EL0(0), 2953 PMU_PMEVCNTR_EL0(1), 2954 PMU_PMEVCNTR_EL0(2), 2955 PMU_PMEVCNTR_EL0(3), 2956 PMU_PMEVCNTR_EL0(4), 2957 PMU_PMEVCNTR_EL0(5), 2958 PMU_PMEVCNTR_EL0(6), 2959 PMU_PMEVCNTR_EL0(7), 2960 PMU_PMEVCNTR_EL0(8), 2961 PMU_PMEVCNTR_EL0(9), 2962 PMU_PMEVCNTR_EL0(10), 2963 PMU_PMEVCNTR_EL0(11), 2964 PMU_PMEVCNTR_EL0(12), 2965 PMU_PMEVCNTR_EL0(13), 2966 PMU_PMEVCNTR_EL0(14), 2967 PMU_PMEVCNTR_EL0(15), 2968 PMU_PMEVCNTR_EL0(16), 2969 PMU_PMEVCNTR_EL0(17), 2970 PMU_PMEVCNTR_EL0(18), 2971 PMU_PMEVCNTR_EL0(19), 2972 PMU_PMEVCNTR_EL0(20), 2973 PMU_PMEVCNTR_EL0(21), 2974 PMU_PMEVCNTR_EL0(22), 2975 PMU_PMEVCNTR_EL0(23), 2976 PMU_PMEVCNTR_EL0(24), 2977 PMU_PMEVCNTR_EL0(25), 2978 PMU_PMEVCNTR_EL0(26), 2979 PMU_PMEVCNTR_EL0(27), 2980 PMU_PMEVCNTR_EL0(28), 2981 PMU_PMEVCNTR_EL0(29), 2982 PMU_PMEVCNTR_EL0(30), 2983 /* PMEVTYPERn_EL0 */ 2984 PMU_PMEVTYPER_EL0(0), 2985 PMU_PMEVTYPER_EL0(1), 2986 PMU_PMEVTYPER_EL0(2), 2987 PMU_PMEVTYPER_EL0(3), 2988 PMU_PMEVTYPER_EL0(4), 2989 PMU_PMEVTYPER_EL0(5), 2990 PMU_PMEVTYPER_EL0(6), 2991 PMU_PMEVTYPER_EL0(7), 2992 PMU_PMEVTYPER_EL0(8), 2993 PMU_PMEVTYPER_EL0(9), 2994 PMU_PMEVTYPER_EL0(10), 2995 PMU_PMEVTYPER_EL0(11), 2996 PMU_PMEVTYPER_EL0(12), 2997 PMU_PMEVTYPER_EL0(13), 2998 PMU_PMEVTYPER_EL0(14), 2999 PMU_PMEVTYPER_EL0(15), 3000 PMU_PMEVTYPER_EL0(16), 3001 PMU_PMEVTYPER_EL0(17), 3002 PMU_PMEVTYPER_EL0(18), 3003 PMU_PMEVTYPER_EL0(19), 3004 PMU_PMEVTYPER_EL0(20), 3005 PMU_PMEVTYPER_EL0(21), 3006 PMU_PMEVTYPER_EL0(22), 3007 PMU_PMEVTYPER_EL0(23), 3008 PMU_PMEVTYPER_EL0(24), 3009 PMU_PMEVTYPER_EL0(25), 3010 PMU_PMEVTYPER_EL0(26), 3011 PMU_PMEVTYPER_EL0(27), 3012 PMU_PMEVTYPER_EL0(28), 3013 PMU_PMEVTYPER_EL0(29), 3014 PMU_PMEVTYPER_EL0(30), 3015 /* 3016 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 3017 * in 32bit mode. Here we choose to reset it as zero for consistency. 3018 */ 3019 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper, 3020 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 }, 3021 3022 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0), 3023 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0), 3024 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1), 3025 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0), 3026 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0), 3027 EL2_REG(MDCR_EL2, access_mdcr, reset_val, 0), 3028 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1), 3029 EL2_REG_VNCR(HSTR_EL2, reset_val, 0), 3030 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0), 3031 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0), 3032 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0), 3033 EL2_REG_VNCR(HACR_EL2, reset_val, 0), 3034 3035 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0, 3036 sve_el2_visibility), 3037 3038 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), 3039 3040 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), 3041 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), 3042 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), 3043 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1, 3044 tcr2_el2_visibility), 3045 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), 3046 EL2_REG_VNCR(VTCR_EL2, reset_val, 0), 3047 3048 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, 3049 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), 3050 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), 3051 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), 3052 EL2_REG_REDIR(SPSR_EL2, reset_val, 0), 3053 EL2_REG_REDIR(ELR_EL2, reset_val, 0), 3054 { SYS_DESC(SYS_SP_EL1), access_sp_el1}, 3055 3056 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */ 3057 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi }, 3058 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi }, 3059 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi }, 3060 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi }, 3061 3062 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 }, 3063 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0), 3064 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0), 3065 EL2_REG_REDIR(ESR_EL2, reset_val, 0), 3066 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 }, 3067 3068 EL2_REG_REDIR(FAR_EL2, reset_val, 0), 3069 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), 3070 3071 EL2_REG(MAIR_EL2, access_rw, reset_val, 0), 3072 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0, 3073 s1pie_el2_visibility), 3074 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0, 3075 s1pie_el2_visibility), 3076 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0, 3077 s1poe_el2_visibility), 3078 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), 3079 { SYS_DESC(SYS_MPAMHCR_EL2), undef_access }, 3080 { SYS_DESC(SYS_MPAMVPMV_EL2), undef_access }, 3081 { SYS_DESC(SYS_MPAM2_EL2), undef_access }, 3082 { SYS_DESC(SYS_MPAMVPM0_EL2), undef_access }, 3083 { SYS_DESC(SYS_MPAMVPM1_EL2), undef_access }, 3084 { SYS_DESC(SYS_MPAMVPM2_EL2), undef_access }, 3085 { SYS_DESC(SYS_MPAMVPM3_EL2), undef_access }, 3086 { SYS_DESC(SYS_MPAMVPM4_EL2), undef_access }, 3087 { SYS_DESC(SYS_MPAMVPM5_EL2), undef_access }, 3088 { SYS_DESC(SYS_MPAMVPM6_EL2), undef_access }, 3089 { SYS_DESC(SYS_MPAMVPM7_EL2), undef_access }, 3090 3091 EL2_REG(VBAR_EL2, access_rw, reset_val, 0), 3092 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0), 3093 { SYS_DESC(SYS_RMR_EL2), undef_access }, 3094 3095 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0), 3096 3097 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0), 3098 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0), 3099 3100 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0), 3101 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), 3102 { SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer }, 3103 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0), 3104 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0), 3105 3106 { SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer }, 3107 EL2_REG(CNTHV_CTL_EL2, access_arch_timer, reset_val, 0), 3108 EL2_REG(CNTHV_CVAL_EL2, access_arch_timer, reset_val, 0), 3109 3110 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 }, 3111 3112 { SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer }, 3113 { SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer }, 3114 { SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer }, 3115 3116 { SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer }, 3117 { SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer }, 3118 { SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer }, 3119 3120 EL2_REG(SP_EL2, NULL, reset_unknown, 0), 3121 }; 3122 3123 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3124 const struct sys_reg_desc *r) 3125 { 3126 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3127 3128 __kvm_at_s1e01(vcpu, op, p->regval); 3129 3130 return true; 3131 } 3132 3133 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3134 const struct sys_reg_desc *r) 3135 { 3136 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3137 3138 /* There is no FGT associated with AT S1E2A :-( */ 3139 if (op == OP_AT_S1E2A && 3140 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) { 3141 kvm_inject_undefined(vcpu); 3142 return false; 3143 } 3144 3145 __kvm_at_s1e2(vcpu, op, p->regval); 3146 3147 return true; 3148 } 3149 3150 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3151 const struct sys_reg_desc *r) 3152 { 3153 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3154 3155 __kvm_at_s12(vcpu, op, p->regval); 3156 3157 return true; 3158 } 3159 3160 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr) 3161 { 3162 struct kvm *kvm = vpcu->kvm; 3163 u8 CRm = sys_reg_CRm(instr); 3164 3165 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3166 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3167 return false; 3168 3169 if (CRm == TLBI_CRm_nROS && 3170 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3171 return false; 3172 3173 return true; 3174 } 3175 3176 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3177 const struct sys_reg_desc *r) 3178 { 3179 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3180 3181 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3182 return undef_access(vcpu, p, r); 3183 3184 write_lock(&vcpu->kvm->mmu_lock); 3185 3186 /* 3187 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the 3188 * corresponding VMIDs. 3189 */ 3190 kvm_nested_s2_unmap(vcpu->kvm, true); 3191 3192 write_unlock(&vcpu->kvm->mmu_lock); 3193 3194 return true; 3195 } 3196 3197 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr) 3198 { 3199 struct kvm *kvm = vpcu->kvm; 3200 u8 CRm = sys_reg_CRm(instr); 3201 u8 Op2 = sys_reg_Op2(instr); 3202 3203 if (sys_reg_CRn(instr) == TLBI_CRn_nXS && 3204 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP)) 3205 return false; 3206 3207 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) && 3208 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3209 return false; 3210 3211 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) && 3212 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 3213 return false; 3214 3215 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) && 3216 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 3217 return false; 3218 3219 return true; 3220 } 3221 3222 /* Only defined here as this is an internal "abstraction" */ 3223 union tlbi_info { 3224 struct { 3225 u64 start; 3226 u64 size; 3227 } range; 3228 3229 struct { 3230 u64 addr; 3231 } ipa; 3232 3233 struct { 3234 u64 addr; 3235 u32 encoding; 3236 } va; 3237 }; 3238 3239 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu, 3240 const union tlbi_info *info) 3241 { 3242 /* 3243 * The unmap operation is allowed to drop the MMU lock and block, which 3244 * means that @mmu could be used for a different context than the one 3245 * currently being invalidated. 3246 * 3247 * This behavior is still safe, as: 3248 * 3249 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating 3250 * the entire MMU before reusing it, which still honors the intent 3251 * of a TLBI. 3252 * 3253 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC 3254 * and ERET to the guest), other vCPUs are allowed to use stale 3255 * translations. 3256 * 3257 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and 3258 * at worst may cause more aborts for shadow stage-2 fills. 3259 * 3260 * Dropping the MMU lock also implies that shadow stage-2 fills could 3261 * happen behind the back of the TLBI. This is still safe, though, as 3262 * the L1 needs to put its stage-2 in a consistent state before doing 3263 * the TLBI. 3264 */ 3265 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true); 3266 } 3267 3268 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3269 const struct sys_reg_desc *r) 3270 { 3271 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3272 u64 limit, vttbr; 3273 3274 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding)) 3275 return undef_access(vcpu, p, r); 3276 3277 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3278 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm)); 3279 3280 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3281 &(union tlbi_info) { 3282 .range = { 3283 .start = 0, 3284 .size = limit, 3285 }, 3286 }, 3287 s2_mmu_unmap_range); 3288 3289 return true; 3290 } 3291 3292 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3293 const struct sys_reg_desc *r) 3294 { 3295 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3296 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3297 u64 base, range, tg, num, scale; 3298 int shift; 3299 3300 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3301 return undef_access(vcpu, p, r); 3302 3303 /* 3304 * Because the shadow S2 structure doesn't necessarily reflect that 3305 * of the guest's S2 (different base granule size, for example), we 3306 * decide to ignore TTL and only use the described range. 3307 */ 3308 tg = FIELD_GET(GENMASK(47, 46), p->regval); 3309 scale = FIELD_GET(GENMASK(45, 44), p->regval); 3310 num = FIELD_GET(GENMASK(43, 39), p->regval); 3311 base = p->regval & GENMASK(36, 0); 3312 3313 switch(tg) { 3314 case 1: 3315 shift = 12; 3316 break; 3317 case 2: 3318 shift = 14; 3319 break; 3320 case 3: 3321 default: /* IMPDEF: handle tg==0 as 64k */ 3322 shift = 16; 3323 break; 3324 } 3325 3326 base <<= shift; 3327 range = __TLBI_RANGE_PAGES(num, scale) << shift; 3328 3329 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3330 &(union tlbi_info) { 3331 .range = { 3332 .start = base, 3333 .size = range, 3334 }, 3335 }, 3336 s2_mmu_unmap_range); 3337 3338 return true; 3339 } 3340 3341 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu, 3342 const union tlbi_info *info) 3343 { 3344 unsigned long max_size; 3345 u64 base_addr; 3346 3347 /* 3348 * We drop a number of things from the supplied value: 3349 * 3350 * - NS bit: we're non-secure only. 3351 * 3352 * - IPA[51:48]: We don't support 52bit IPA just yet... 3353 * 3354 * And of course, adjust the IPA to be on an actual address. 3355 */ 3356 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12; 3357 max_size = compute_tlb_inval_range(mmu, info->ipa.addr); 3358 base_addr &= ~(max_size - 1); 3359 3360 /* 3361 * See comment in s2_mmu_unmap_range() for why this is allowed to 3362 * reschedule. 3363 */ 3364 kvm_stage2_unmap_range(mmu, base_addr, max_size, true); 3365 } 3366 3367 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3368 const struct sys_reg_desc *r) 3369 { 3370 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3371 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3372 3373 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) 3374 return undef_access(vcpu, p, r); 3375 3376 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3377 &(union tlbi_info) { 3378 .ipa = { 3379 .addr = p->regval, 3380 }, 3381 }, 3382 s2_mmu_unmap_ipa); 3383 3384 return true; 3385 } 3386 3387 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu, 3388 const union tlbi_info *info) 3389 { 3390 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding)); 3391 } 3392 3393 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 3394 const struct sys_reg_desc *r) 3395 { 3396 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2); 3397 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2); 3398 3399 /* 3400 * If we're here, this is because we've trapped on a EL1 TLBI 3401 * instruction that affects the EL1 translation regime while 3402 * we're running in a context that doesn't allow us to let the 3403 * HW do its thing (aka vEL2): 3404 * 3405 * - HCR_EL2.E2H == 0 : a non-VHE guest 3406 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode 3407 * 3408 * We don't expect these helpers to ever be called when running 3409 * in a vEL1 context. 3410 */ 3411 3412 WARN_ON(!vcpu_is_el2(vcpu)); 3413 3414 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding)) 3415 return undef_access(vcpu, p, r); 3416 3417 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr), 3418 &(union tlbi_info) { 3419 .va = { 3420 .addr = p->regval, 3421 .encoding = sys_encoding, 3422 }, 3423 }, 3424 s2_mmu_tlbi_s1e1); 3425 3426 return true; 3427 } 3428 3429 #define SYS_INSN(insn, access_fn) \ 3430 { \ 3431 SYS_DESC(OP_##insn), \ 3432 .access = (access_fn), \ 3433 } 3434 3435 static struct sys_reg_desc sys_insn_descs[] = { 3436 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 3437 { SYS_DESC(SYS_DC_IGSW), access_dcgsw }, 3438 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw }, 3439 3440 SYS_INSN(AT_S1E1R, handle_at_s1e01), 3441 SYS_INSN(AT_S1E1W, handle_at_s1e01), 3442 SYS_INSN(AT_S1E0R, handle_at_s1e01), 3443 SYS_INSN(AT_S1E0W, handle_at_s1e01), 3444 SYS_INSN(AT_S1E1RP, handle_at_s1e01), 3445 SYS_INSN(AT_S1E1WP, handle_at_s1e01), 3446 3447 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 3448 { SYS_DESC(SYS_DC_CGSW), access_dcgsw }, 3449 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw }, 3450 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 3451 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw }, 3452 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw }, 3453 3454 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1), 3455 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1), 3456 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1), 3457 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1), 3458 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1), 3459 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1), 3460 3461 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1), 3462 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1), 3463 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1), 3464 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1), 3465 3466 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1), 3467 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1), 3468 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1), 3469 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1), 3470 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1), 3471 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1), 3472 3473 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1), 3474 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1), 3475 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1), 3476 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1), 3477 3478 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1), 3479 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1), 3480 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1), 3481 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1), 3482 3483 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1), 3484 SYS_INSN(TLBI_VAE1, handle_tlbi_el1), 3485 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1), 3486 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1), 3487 SYS_INSN(TLBI_VALE1, handle_tlbi_el1), 3488 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1), 3489 3490 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1), 3491 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1), 3492 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1), 3493 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1), 3494 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1), 3495 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1), 3496 3497 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1), 3498 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1), 3499 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1), 3500 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1), 3501 3502 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1), 3503 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1), 3504 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1), 3505 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1), 3506 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1), 3507 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1), 3508 3509 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1), 3510 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1), 3511 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1), 3512 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1), 3513 3514 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1), 3515 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1), 3516 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1), 3517 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1), 3518 3519 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1), 3520 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1), 3521 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1), 3522 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1), 3523 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1), 3524 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1), 3525 3526 SYS_INSN(AT_S1E2R, handle_at_s1e2), 3527 SYS_INSN(AT_S1E2W, handle_at_s1e2), 3528 SYS_INSN(AT_S12E1R, handle_at_s12), 3529 SYS_INSN(AT_S12E1W, handle_at_s12), 3530 SYS_INSN(AT_S12E0R, handle_at_s12), 3531 SYS_INSN(AT_S12E0W, handle_at_s12), 3532 SYS_INSN(AT_S1E2A, handle_at_s1e2), 3533 3534 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is), 3535 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is), 3536 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is), 3537 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is), 3538 3539 SYS_INSN(TLBI_ALLE2OS, undef_access), 3540 SYS_INSN(TLBI_VAE2OS, undef_access), 3541 SYS_INSN(TLBI_ALLE1OS, handle_alle1is), 3542 SYS_INSN(TLBI_VALE2OS, undef_access), 3543 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is), 3544 3545 SYS_INSN(TLBI_RVAE2IS, undef_access), 3546 SYS_INSN(TLBI_RVALE2IS, undef_access), 3547 3548 SYS_INSN(TLBI_ALLE1IS, handle_alle1is), 3549 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is), 3550 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is), 3551 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is), 3552 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is), 3553 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is), 3554 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is), 3555 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is), 3556 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is), 3557 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is), 3558 SYS_INSN(TLBI_RVAE2OS, undef_access), 3559 SYS_INSN(TLBI_RVALE2OS, undef_access), 3560 SYS_INSN(TLBI_RVAE2, undef_access), 3561 SYS_INSN(TLBI_RVALE2, undef_access), 3562 SYS_INSN(TLBI_ALLE1, handle_alle1is), 3563 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is), 3564 3565 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is), 3566 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is), 3567 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is), 3568 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is), 3569 3570 SYS_INSN(TLBI_ALLE2OSNXS, undef_access), 3571 SYS_INSN(TLBI_VAE2OSNXS, undef_access), 3572 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is), 3573 SYS_INSN(TLBI_VALE2OSNXS, undef_access), 3574 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is), 3575 3576 SYS_INSN(TLBI_RVAE2ISNXS, undef_access), 3577 SYS_INSN(TLBI_RVALE2ISNXS, undef_access), 3578 SYS_INSN(TLBI_ALLE2ISNXS, undef_access), 3579 SYS_INSN(TLBI_VAE2ISNXS, undef_access), 3580 3581 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is), 3582 SYS_INSN(TLBI_VALE2ISNXS, undef_access), 3583 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is), 3584 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is), 3585 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is), 3586 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is), 3587 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is), 3588 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is), 3589 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is), 3590 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is), 3591 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is), 3592 SYS_INSN(TLBI_RVAE2OSNXS, undef_access), 3593 SYS_INSN(TLBI_RVALE2OSNXS, undef_access), 3594 SYS_INSN(TLBI_RVAE2NXS, undef_access), 3595 SYS_INSN(TLBI_RVALE2NXS, undef_access), 3596 SYS_INSN(TLBI_ALLE2NXS, undef_access), 3597 SYS_INSN(TLBI_VAE2NXS, undef_access), 3598 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is), 3599 SYS_INSN(TLBI_VALE2NXS, undef_access), 3600 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is), 3601 }; 3602 3603 static bool trap_dbgdidr(struct kvm_vcpu *vcpu, 3604 struct sys_reg_params *p, 3605 const struct sys_reg_desc *r) 3606 { 3607 if (p->is_write) { 3608 return ignore_write(vcpu, p); 3609 } else { 3610 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1); 3611 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP); 3612 3613 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) | 3614 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) | 3615 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) | 3616 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) | 3617 (1 << 15) | (el3 << 14) | (el3 << 12)); 3618 return true; 3619 } 3620 } 3621 3622 /* 3623 * AArch32 debug register mappings 3624 * 3625 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 3626 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 3627 * 3628 * None of the other registers share their location, so treat them as 3629 * if they were 64bit. 3630 */ 3631 #define DBG_BCR_BVR_WCR_WVR(n) \ 3632 /* DBGBVRn */ \ 3633 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \ 3634 trap_dbg_wb_reg, NULL, n }, \ 3635 /* DBGBCRn */ \ 3636 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_dbg_wb_reg, NULL, n }, \ 3637 /* DBGWVRn */ \ 3638 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_dbg_wb_reg, NULL, n }, \ 3639 /* DBGWCRn */ \ 3640 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_dbg_wb_reg, NULL, n } 3641 3642 #define DBGBXVR(n) \ 3643 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), \ 3644 trap_dbg_wb_reg, NULL, n } 3645 3646 /* 3647 * Trapped cp14 registers. We generally ignore most of the external 3648 * debug, on the principle that they don't really make sense to a 3649 * guest. Revisit this one day, would this principle change. 3650 */ 3651 static const struct sys_reg_desc cp14_regs[] = { 3652 /* DBGDIDR */ 3653 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr }, 3654 /* DBGDTRRXext */ 3655 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 3656 3657 DBG_BCR_BVR_WCR_WVR(0), 3658 /* DBGDSCRint */ 3659 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 3660 DBG_BCR_BVR_WCR_WVR(1), 3661 /* DBGDCCINT */ 3662 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 3663 /* DBGDSCRext */ 3664 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 3665 DBG_BCR_BVR_WCR_WVR(2), 3666 /* DBGDTR[RT]Xint */ 3667 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 3668 /* DBGDTR[RT]Xext */ 3669 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 3670 DBG_BCR_BVR_WCR_WVR(3), 3671 DBG_BCR_BVR_WCR_WVR(4), 3672 DBG_BCR_BVR_WCR_WVR(5), 3673 /* DBGWFAR */ 3674 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 3675 /* DBGOSECCR */ 3676 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 3677 DBG_BCR_BVR_WCR_WVR(6), 3678 /* DBGVCR */ 3679 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 3680 DBG_BCR_BVR_WCR_WVR(7), 3681 DBG_BCR_BVR_WCR_WVR(8), 3682 DBG_BCR_BVR_WCR_WVR(9), 3683 DBG_BCR_BVR_WCR_WVR(10), 3684 DBG_BCR_BVR_WCR_WVR(11), 3685 DBG_BCR_BVR_WCR_WVR(12), 3686 DBG_BCR_BVR_WCR_WVR(13), 3687 DBG_BCR_BVR_WCR_WVR(14), 3688 DBG_BCR_BVR_WCR_WVR(15), 3689 3690 /* DBGDRAR (32bit) */ 3691 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 3692 3693 DBGBXVR(0), 3694 /* DBGOSLAR */ 3695 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 }, 3696 DBGBXVR(1), 3697 /* DBGOSLSR */ 3698 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 }, 3699 DBGBXVR(2), 3700 DBGBXVR(3), 3701 /* DBGOSDLR */ 3702 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 3703 DBGBXVR(4), 3704 /* DBGPRCR */ 3705 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 3706 DBGBXVR(5), 3707 DBGBXVR(6), 3708 DBGBXVR(7), 3709 DBGBXVR(8), 3710 DBGBXVR(9), 3711 DBGBXVR(10), 3712 DBGBXVR(11), 3713 DBGBXVR(12), 3714 DBGBXVR(13), 3715 DBGBXVR(14), 3716 DBGBXVR(15), 3717 3718 /* DBGDSAR (32bit) */ 3719 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 3720 3721 /* DBGDEVID2 */ 3722 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 3723 /* DBGDEVID1 */ 3724 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 3725 /* DBGDEVID */ 3726 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 3727 /* DBGCLAIMSET */ 3728 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 3729 /* DBGCLAIMCLR */ 3730 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 3731 /* DBGAUTHSTATUS */ 3732 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 3733 }; 3734 3735 /* Trapped cp14 64bit registers */ 3736 static const struct sys_reg_desc cp14_64_regs[] = { 3737 /* DBGDRAR (64bit) */ 3738 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 3739 3740 /* DBGDSAR (64bit) */ 3741 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 3742 }; 3743 3744 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ 3745 AA32(_map), \ 3746 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ 3747 .visibility = pmu_visibility 3748 3749 /* Macro to expand the PMEVCNTRn register */ 3750 #define PMU_PMEVCNTR(n) \ 3751 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3752 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3753 .access = access_pmu_evcntr } 3754 3755 /* Macro to expand the PMEVTYPERn register */ 3756 #define PMU_PMEVTYPER(n) \ 3757 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ 3758 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ 3759 .access = access_pmu_evtyper } 3760 /* 3761 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 3762 * depending on the way they are accessed (as a 32bit or a 64bit 3763 * register). 3764 */ 3765 static const struct sys_reg_desc cp15_regs[] = { 3766 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 3767 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 3768 /* ACTLR */ 3769 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 3770 /* ACTLR2 */ 3771 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 3772 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3773 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 3774 /* TTBCR */ 3775 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 3776 /* TTBCR2 */ 3777 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 3778 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 3779 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access }, 3780 /* DFSR */ 3781 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 3782 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 3783 /* ADFSR */ 3784 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 3785 /* AIFSR */ 3786 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 3787 /* DFAR */ 3788 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 3789 /* IFAR */ 3790 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 3791 3792 /* 3793 * DC{C,I,CI}SW operations: 3794 */ 3795 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 3796 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 3797 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 3798 3799 /* PMU */ 3800 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr }, 3801 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten }, 3802 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten }, 3803 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs }, 3804 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc }, 3805 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr }, 3806 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid }, 3807 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid }, 3808 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr }, 3809 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper }, 3810 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr }, 3811 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr }, 3812 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten }, 3813 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten }, 3814 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs }, 3815 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid }, 3816 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid }, 3817 /* PMMIR */ 3818 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi }, 3819 3820 /* PRRR/MAIR0 */ 3821 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 3822 /* NMRR/MAIR1 */ 3823 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 3824 /* AMAIR0 */ 3825 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 3826 /* AMAIR1 */ 3827 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 3828 3829 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access }, 3830 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access }, 3831 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access }, 3832 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access }, 3833 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access }, 3834 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access }, 3835 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access }, 3836 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access }, 3837 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access }, 3838 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access }, 3839 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access }, 3840 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access }, 3841 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access }, 3842 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access }, 3843 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access }, 3844 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access }, 3845 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access }, 3846 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access }, 3847 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access }, 3848 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 3849 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access }, 3850 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access }, 3851 3852 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 3853 3854 /* Arch Tmers */ 3855 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 3856 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 3857 3858 /* PMEVCNTRn */ 3859 PMU_PMEVCNTR(0), 3860 PMU_PMEVCNTR(1), 3861 PMU_PMEVCNTR(2), 3862 PMU_PMEVCNTR(3), 3863 PMU_PMEVCNTR(4), 3864 PMU_PMEVCNTR(5), 3865 PMU_PMEVCNTR(6), 3866 PMU_PMEVCNTR(7), 3867 PMU_PMEVCNTR(8), 3868 PMU_PMEVCNTR(9), 3869 PMU_PMEVCNTR(10), 3870 PMU_PMEVCNTR(11), 3871 PMU_PMEVCNTR(12), 3872 PMU_PMEVCNTR(13), 3873 PMU_PMEVCNTR(14), 3874 PMU_PMEVCNTR(15), 3875 PMU_PMEVCNTR(16), 3876 PMU_PMEVCNTR(17), 3877 PMU_PMEVCNTR(18), 3878 PMU_PMEVCNTR(19), 3879 PMU_PMEVCNTR(20), 3880 PMU_PMEVCNTR(21), 3881 PMU_PMEVCNTR(22), 3882 PMU_PMEVCNTR(23), 3883 PMU_PMEVCNTR(24), 3884 PMU_PMEVCNTR(25), 3885 PMU_PMEVCNTR(26), 3886 PMU_PMEVCNTR(27), 3887 PMU_PMEVCNTR(28), 3888 PMU_PMEVCNTR(29), 3889 PMU_PMEVCNTR(30), 3890 /* PMEVTYPERn */ 3891 PMU_PMEVTYPER(0), 3892 PMU_PMEVTYPER(1), 3893 PMU_PMEVTYPER(2), 3894 PMU_PMEVTYPER(3), 3895 PMU_PMEVTYPER(4), 3896 PMU_PMEVTYPER(5), 3897 PMU_PMEVTYPER(6), 3898 PMU_PMEVTYPER(7), 3899 PMU_PMEVTYPER(8), 3900 PMU_PMEVTYPER(9), 3901 PMU_PMEVTYPER(10), 3902 PMU_PMEVTYPER(11), 3903 PMU_PMEVTYPER(12), 3904 PMU_PMEVTYPER(13), 3905 PMU_PMEVTYPER(14), 3906 PMU_PMEVTYPER(15), 3907 PMU_PMEVTYPER(16), 3908 PMU_PMEVTYPER(17), 3909 PMU_PMEVTYPER(18), 3910 PMU_PMEVTYPER(19), 3911 PMU_PMEVTYPER(20), 3912 PMU_PMEVTYPER(21), 3913 PMU_PMEVTYPER(22), 3914 PMU_PMEVTYPER(23), 3915 PMU_PMEVTYPER(24), 3916 PMU_PMEVTYPER(25), 3917 PMU_PMEVTYPER(26), 3918 PMU_PMEVTYPER(27), 3919 PMU_PMEVTYPER(28), 3920 PMU_PMEVTYPER(29), 3921 PMU_PMEVTYPER(30), 3922 /* PMCCFILTR */ 3923 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper }, 3924 3925 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 3926 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 3927 3928 /* CCSIDR2 */ 3929 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, 3930 3931 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 3932 }; 3933 3934 static const struct sys_reg_desc cp15_64_regs[] = { 3935 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 3936 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr }, 3937 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 3938 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer }, 3939 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 3940 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 3941 { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer }, 3942 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 3943 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 3944 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer }, 3945 { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer }, 3946 }; 3947 3948 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 3949 bool is_32) 3950 { 3951 unsigned int i; 3952 3953 for (i = 0; i < n; i++) { 3954 if (!is_32 && table[i].reg && !table[i].reset) { 3955 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", 3956 &table[i], i, table[i].name); 3957 return false; 3958 } 3959 3960 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 3961 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", 3962 &table[i], i, table[i - 1].name, table[i].name); 3963 return false; 3964 } 3965 } 3966 3967 return true; 3968 } 3969 3970 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 3971 { 3972 kvm_inject_undefined(vcpu); 3973 return 1; 3974 } 3975 3976 static void perform_access(struct kvm_vcpu *vcpu, 3977 struct sys_reg_params *params, 3978 const struct sys_reg_desc *r) 3979 { 3980 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 3981 3982 /* Check for regs disabled by runtime config */ 3983 if (sysreg_hidden(vcpu, r)) { 3984 kvm_inject_undefined(vcpu); 3985 return; 3986 } 3987 3988 /* 3989 * Not having an accessor means that we have configured a trap 3990 * that we don't know how to handle. This certainly qualifies 3991 * as a gross bug that should be fixed right away. 3992 */ 3993 BUG_ON(!r->access); 3994 3995 /* Skip instruction if instructed so */ 3996 if (likely(r->access(vcpu, params, r))) 3997 kvm_incr_pc(vcpu); 3998 } 3999 4000 /* 4001 * emulate_cp -- tries to match a sys_reg access in a handling table, and 4002 * call the corresponding trap handler. 4003 * 4004 * @params: pointer to the descriptor of the access 4005 * @table: array of trap descriptors 4006 * @num: size of the trap descriptor array 4007 * 4008 * Return true if the access has been handled, false if not. 4009 */ 4010 static bool emulate_cp(struct kvm_vcpu *vcpu, 4011 struct sys_reg_params *params, 4012 const struct sys_reg_desc *table, 4013 size_t num) 4014 { 4015 const struct sys_reg_desc *r; 4016 4017 if (!table) 4018 return false; /* Not handled */ 4019 4020 r = find_reg(params, table, num); 4021 4022 if (r) { 4023 perform_access(vcpu, params, r); 4024 return true; 4025 } 4026 4027 /* Not handled */ 4028 return false; 4029 } 4030 4031 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 4032 struct sys_reg_params *params) 4033 { 4034 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 4035 int cp = -1; 4036 4037 switch (esr_ec) { 4038 case ESR_ELx_EC_CP15_32: 4039 case ESR_ELx_EC_CP15_64: 4040 cp = 15; 4041 break; 4042 case ESR_ELx_EC_CP14_MR: 4043 case ESR_ELx_EC_CP14_64: 4044 cp = 14; 4045 break; 4046 default: 4047 WARN_ON(1); 4048 } 4049 4050 print_sys_reg_msg(params, 4051 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 4052 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4053 kvm_inject_undefined(vcpu); 4054 } 4055 4056 /** 4057 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 4058 * @vcpu: The VCPU pointer 4059 * @global: &struct sys_reg_desc 4060 * @nr_global: size of the @global array 4061 */ 4062 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 4063 const struct sys_reg_desc *global, 4064 size_t nr_global) 4065 { 4066 struct sys_reg_params params; 4067 u64 esr = kvm_vcpu_get_esr(vcpu); 4068 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4069 int Rt2 = (esr >> 10) & 0x1f; 4070 4071 params.CRm = (esr >> 1) & 0xf; 4072 params.is_write = ((esr & 1) == 0); 4073 4074 params.Op0 = 0; 4075 params.Op1 = (esr >> 16) & 0xf; 4076 params.Op2 = 0; 4077 params.CRn = 0; 4078 4079 /* 4080 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 4081 * backends between AArch32 and AArch64, we get away with it. 4082 */ 4083 if (params.is_write) { 4084 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 4085 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 4086 } 4087 4088 /* 4089 * If the table contains a handler, handle the 4090 * potential register operation in the case of a read and return 4091 * with success. 4092 */ 4093 if (emulate_cp(vcpu, ¶ms, global, nr_global)) { 4094 /* Split up the value between registers for the read side */ 4095 if (!params.is_write) { 4096 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 4097 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 4098 } 4099 4100 return 1; 4101 } 4102 4103 unhandled_cp_access(vcpu, ¶ms); 4104 return 1; 4105 } 4106 4107 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params); 4108 4109 /* 4110 * The CP10 ID registers are architecturally mapped to AArch64 feature 4111 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses 4112 * from AArch32. 4113 */ 4114 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params) 4115 { 4116 u8 reg_id = (esr >> 10) & 0xf; 4117 bool valid; 4118 4119 params->is_write = ((esr & 1) == 0); 4120 params->Op0 = 3; 4121 params->Op1 = 0; 4122 params->CRn = 0; 4123 params->CRm = 3; 4124 4125 /* CP10 ID registers are read-only */ 4126 valid = !params->is_write; 4127 4128 switch (reg_id) { 4129 /* MVFR0 */ 4130 case 0b0111: 4131 params->Op2 = 0; 4132 break; 4133 /* MVFR1 */ 4134 case 0b0110: 4135 params->Op2 = 1; 4136 break; 4137 /* MVFR2 */ 4138 case 0b0101: 4139 params->Op2 = 2; 4140 break; 4141 default: 4142 valid = false; 4143 } 4144 4145 if (valid) 4146 return true; 4147 4148 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", 4149 params->is_write ? "write" : "read", reg_id); 4150 return false; 4151 } 4152 4153 /** 4154 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and 4155 * VFP Register' from AArch32. 4156 * @vcpu: The vCPU pointer 4157 * 4158 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers. 4159 * Work out the correct AArch64 system register encoding and reroute to the 4160 * AArch64 system register emulation. 4161 */ 4162 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) 4163 { 4164 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4165 u64 esr = kvm_vcpu_get_esr(vcpu); 4166 struct sys_reg_params params; 4167 4168 /* UNDEF on any unhandled register access */ 4169 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { 4170 kvm_inject_undefined(vcpu); 4171 return 1; 4172 } 4173 4174 if (emulate_sys_reg(vcpu, ¶ms)) 4175 vcpu_set_reg(vcpu, Rt, params.regval); 4176 4177 return 1; 4178 } 4179 4180 /** 4181 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where 4182 * CRn=0, which corresponds to the AArch32 feature 4183 * registers. 4184 * @vcpu: the vCPU pointer 4185 * @params: the system register access parameters. 4186 * 4187 * Our cp15 system register tables do not enumerate the AArch32 feature 4188 * registers. Conveniently, our AArch64 table does, and the AArch32 system 4189 * register encoding can be trivially remapped into the AArch64 for the feature 4190 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same. 4191 * 4192 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit 4193 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this 4194 * range are either UNKNOWN or RES0. Rerouting remains architectural as we 4195 * treat undefined registers in this range as RAZ. 4196 */ 4197 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, 4198 struct sys_reg_params *params) 4199 { 4200 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4201 4202 /* Treat impossible writes to RO registers as UNDEFINED */ 4203 if (params->is_write) { 4204 unhandled_cp_access(vcpu, params); 4205 return 1; 4206 } 4207 4208 params->Op0 = 3; 4209 4210 /* 4211 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. 4212 * Avoid conflicting with future expansion of AArch64 feature registers 4213 * and simply treat them as RAZ here. 4214 */ 4215 if (params->CRm > 3) 4216 params->regval = 0; 4217 else if (!emulate_sys_reg(vcpu, params)) 4218 return 1; 4219 4220 vcpu_set_reg(vcpu, Rt, params->regval); 4221 return 1; 4222 } 4223 4224 /** 4225 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 4226 * @vcpu: The VCPU pointer 4227 * @params: &struct sys_reg_params 4228 * @global: &struct sys_reg_desc 4229 * @nr_global: size of the @global array 4230 */ 4231 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 4232 struct sys_reg_params *params, 4233 const struct sys_reg_desc *global, 4234 size_t nr_global) 4235 { 4236 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4237 4238 params->regval = vcpu_get_reg(vcpu, Rt); 4239 4240 if (emulate_cp(vcpu, params, global, nr_global)) { 4241 if (!params->is_write) 4242 vcpu_set_reg(vcpu, Rt, params->regval); 4243 return 1; 4244 } 4245 4246 unhandled_cp_access(vcpu, params); 4247 return 1; 4248 } 4249 4250 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 4251 { 4252 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 4253 } 4254 4255 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 4256 { 4257 struct sys_reg_params params; 4258 4259 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4260 4261 /* 4262 * Certain AArch32 ID registers are handled by rerouting to the AArch64 4263 * system register table. Registers in the ID range where CRm=0 are 4264 * excluded from this scheme as they do not trivially map into AArch64 4265 * system register encodings. 4266 */ 4267 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) 4268 return kvm_emulate_cp15_id_reg(vcpu, ¶ms); 4269 4270 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); 4271 } 4272 4273 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 4274 { 4275 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 4276 } 4277 4278 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 4279 { 4280 struct sys_reg_params params; 4281 4282 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); 4283 4284 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); 4285 } 4286 4287 /** 4288 * emulate_sys_reg - Emulate a guest access to an AArch64 system register 4289 * @vcpu: The VCPU pointer 4290 * @params: Decoded system register parameters 4291 * 4292 * Return: true if the system register access was successful, false otherwise. 4293 */ 4294 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, 4295 struct sys_reg_params *params) 4296 { 4297 const struct sys_reg_desc *r; 4298 4299 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4300 if (likely(r)) { 4301 perform_access(vcpu, params, r); 4302 return true; 4303 } 4304 4305 print_sys_reg_msg(params, 4306 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 4307 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 4308 kvm_inject_undefined(vcpu); 4309 4310 return false; 4311 } 4312 4313 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos) 4314 { 4315 unsigned long i, idreg_idx = 0; 4316 4317 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4318 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4319 4320 if (!is_vm_ftr_id_reg(reg_to_encoding(r))) 4321 continue; 4322 4323 if (idreg_idx == pos) 4324 return r; 4325 4326 idreg_idx++; 4327 } 4328 4329 return NULL; 4330 } 4331 4332 static void *idregs_debug_start(struct seq_file *s, loff_t *pos) 4333 { 4334 struct kvm *kvm = s->private; 4335 u8 *iter; 4336 4337 mutex_lock(&kvm->arch.config_lock); 4338 4339 iter = &kvm->arch.idreg_debugfs_iter; 4340 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) && 4341 *iter == (u8)~0) { 4342 *iter = *pos; 4343 if (!idregs_debug_find(kvm, *iter)) 4344 iter = NULL; 4345 } else { 4346 iter = ERR_PTR(-EBUSY); 4347 } 4348 4349 mutex_unlock(&kvm->arch.config_lock); 4350 4351 return iter; 4352 } 4353 4354 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos) 4355 { 4356 struct kvm *kvm = s->private; 4357 4358 (*pos)++; 4359 4360 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) { 4361 kvm->arch.idreg_debugfs_iter++; 4362 4363 return &kvm->arch.idreg_debugfs_iter; 4364 } 4365 4366 return NULL; 4367 } 4368 4369 static void idregs_debug_stop(struct seq_file *s, void *v) 4370 { 4371 struct kvm *kvm = s->private; 4372 4373 if (IS_ERR(v)) 4374 return; 4375 4376 mutex_lock(&kvm->arch.config_lock); 4377 4378 kvm->arch.idreg_debugfs_iter = ~0; 4379 4380 mutex_unlock(&kvm->arch.config_lock); 4381 } 4382 4383 static int idregs_debug_show(struct seq_file *s, void *v) 4384 { 4385 const struct sys_reg_desc *desc; 4386 struct kvm *kvm = s->private; 4387 4388 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter); 4389 4390 if (!desc->name) 4391 return 0; 4392 4393 seq_printf(s, "%20s:\t%016llx\n", 4394 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc))); 4395 4396 return 0; 4397 } 4398 4399 static const struct seq_operations idregs_debug_sops = { 4400 .start = idregs_debug_start, 4401 .next = idregs_debug_next, 4402 .stop = idregs_debug_stop, 4403 .show = idregs_debug_show, 4404 }; 4405 4406 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 4407 4408 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 4409 { 4410 kvm->arch.idreg_debugfs_iter = ~0; 4411 4412 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 4413 &idregs_debug_fops); 4414 } 4415 4416 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg) 4417 { 4418 u32 id = reg_to_encoding(reg); 4419 struct kvm *kvm = vcpu->kvm; 4420 4421 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)) 4422 return; 4423 4424 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg)); 4425 } 4426 4427 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu, 4428 const struct sys_reg_desc *reg) 4429 { 4430 if (kvm_vcpu_initialized(vcpu)) 4431 return; 4432 4433 reg->reset(vcpu, reg); 4434 } 4435 4436 /** 4437 * kvm_reset_sys_regs - sets system registers to reset value 4438 * @vcpu: The VCPU pointer 4439 * 4440 * This function finds the right table above and sets the registers on the 4441 * virtual CPU struct to their architecturally defined reset values. 4442 */ 4443 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 4444 { 4445 struct kvm *kvm = vcpu->kvm; 4446 unsigned long i; 4447 4448 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4449 const struct sys_reg_desc *r = &sys_reg_descs[i]; 4450 4451 if (!r->reset) 4452 continue; 4453 4454 if (is_vm_ftr_id_reg(reg_to_encoding(r))) 4455 reset_vm_ftr_id_reg(vcpu, r); 4456 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r))) 4457 reset_vcpu_ftr_id_reg(vcpu, r); 4458 else 4459 r->reset(vcpu, r); 4460 4461 if (r->reg >= __SANITISED_REG_START__ && r->reg < NR_SYS_REGS) 4462 (void)__vcpu_sys_reg(vcpu, r->reg); 4463 } 4464 4465 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags); 4466 } 4467 4468 /** 4469 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction 4470 * trap on a guest execution 4471 * @vcpu: The VCPU pointer 4472 */ 4473 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 4474 { 4475 const struct sys_reg_desc *desc = NULL; 4476 struct sys_reg_params params; 4477 unsigned long esr = kvm_vcpu_get_esr(vcpu); 4478 int Rt = kvm_vcpu_sys_get_rt(vcpu); 4479 int sr_idx; 4480 4481 trace_kvm_handle_sys_reg(esr); 4482 4483 if (triage_sysreg_trap(vcpu, &sr_idx)) 4484 return 1; 4485 4486 params = esr_sys64_to_params(esr); 4487 params.regval = vcpu_get_reg(vcpu, Rt); 4488 4489 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */ 4490 if (params.Op0 == 2 || params.Op0 == 3) 4491 desc = &sys_reg_descs[sr_idx]; 4492 else 4493 desc = &sys_insn_descs[sr_idx]; 4494 4495 perform_access(vcpu, ¶ms, desc); 4496 4497 /* Read from system register? */ 4498 if (!params.is_write && 4499 (params.Op0 == 2 || params.Op0 == 3)) 4500 vcpu_set_reg(vcpu, Rt, params.regval); 4501 4502 return 1; 4503 } 4504 4505 /****************************************************************************** 4506 * Userspace API 4507 *****************************************************************************/ 4508 4509 static bool index_to_params(u64 id, struct sys_reg_params *params) 4510 { 4511 switch (id & KVM_REG_SIZE_MASK) { 4512 case KVM_REG_SIZE_U64: 4513 /* Any unused index bits means it's not valid. */ 4514 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 4515 | KVM_REG_ARM_COPROC_MASK 4516 | KVM_REG_ARM64_SYSREG_OP0_MASK 4517 | KVM_REG_ARM64_SYSREG_OP1_MASK 4518 | KVM_REG_ARM64_SYSREG_CRN_MASK 4519 | KVM_REG_ARM64_SYSREG_CRM_MASK 4520 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 4521 return false; 4522 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 4523 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 4524 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 4525 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 4526 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 4527 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 4528 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 4529 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 4530 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 4531 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 4532 return true; 4533 default: 4534 return false; 4535 } 4536 } 4537 4538 const struct sys_reg_desc *get_reg_by_id(u64 id, 4539 const struct sys_reg_desc table[], 4540 unsigned int num) 4541 { 4542 struct sys_reg_params params; 4543 4544 if (!index_to_params(id, ¶ms)) 4545 return NULL; 4546 4547 return find_reg(¶ms, table, num); 4548 } 4549 4550 /* Decode an index value, and find the sys_reg_desc entry. */ 4551 static const struct sys_reg_desc * 4552 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, 4553 const struct sys_reg_desc table[], unsigned int num) 4554 4555 { 4556 const struct sys_reg_desc *r; 4557 4558 /* We only do sys_reg for now. */ 4559 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 4560 return NULL; 4561 4562 r = get_reg_by_id(id, table, num); 4563 4564 /* Not saved in the sys_reg array and not otherwise accessible? */ 4565 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r))) 4566 r = NULL; 4567 4568 return r; 4569 } 4570 4571 /* 4572 * These are the invariant sys_reg registers: we let the guest see the 4573 * host versions of these, so they're part of the guest state. 4574 * 4575 * A future CPU may provide a mechanism to present different values to 4576 * the guest, or a future kvm may trap them. 4577 */ 4578 4579 #define FUNCTION_INVARIANT(reg) \ 4580 static u64 reset_##reg(struct kvm_vcpu *v, \ 4581 const struct sys_reg_desc *r) \ 4582 { \ 4583 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 4584 return ((struct sys_reg_desc *)r)->val; \ 4585 } 4586 4587 FUNCTION_INVARIANT(midr_el1) 4588 FUNCTION_INVARIANT(revidr_el1) 4589 FUNCTION_INVARIANT(aidr_el1) 4590 4591 /* ->val is filled in by kvm_sys_reg_table_init() */ 4592 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = { 4593 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 }, 4594 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 }, 4595 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 }, 4596 }; 4597 4598 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr) 4599 { 4600 const struct sys_reg_desc *r; 4601 4602 r = get_reg_by_id(id, invariant_sys_regs, 4603 ARRAY_SIZE(invariant_sys_regs)); 4604 if (!r) 4605 return -ENOENT; 4606 4607 return put_user(r->val, uaddr); 4608 } 4609 4610 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr) 4611 { 4612 const struct sys_reg_desc *r; 4613 u64 val; 4614 4615 r = get_reg_by_id(id, invariant_sys_regs, 4616 ARRAY_SIZE(invariant_sys_regs)); 4617 if (!r) 4618 return -ENOENT; 4619 4620 if (get_user(val, uaddr)) 4621 return -EFAULT; 4622 4623 /* This is what we mean by invariant: you can't change it. */ 4624 if (r->val != val) 4625 return -EINVAL; 4626 4627 return 0; 4628 } 4629 4630 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4631 { 4632 u32 val; 4633 u32 __user *uval = uaddr; 4634 4635 /* Fail if we have unknown bits set. */ 4636 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4637 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4638 return -ENOENT; 4639 4640 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4641 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4642 if (KVM_REG_SIZE(id) != 4) 4643 return -ENOENT; 4644 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4645 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4646 if (val >= CSSELR_MAX) 4647 return -ENOENT; 4648 4649 return put_user(get_ccsidr(vcpu, val), uval); 4650 default: 4651 return -ENOENT; 4652 } 4653 } 4654 4655 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) 4656 { 4657 u32 val, newval; 4658 u32 __user *uval = uaddr; 4659 4660 /* Fail if we have unknown bits set. */ 4661 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 4662 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 4663 return -ENOENT; 4664 4665 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 4666 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 4667 if (KVM_REG_SIZE(id) != 4) 4668 return -ENOENT; 4669 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 4670 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 4671 if (val >= CSSELR_MAX) 4672 return -ENOENT; 4673 4674 if (get_user(newval, uval)) 4675 return -EFAULT; 4676 4677 return set_ccsidr(vcpu, val, newval); 4678 default: 4679 return -ENOENT; 4680 } 4681 } 4682 4683 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4684 const struct sys_reg_desc table[], unsigned int num) 4685 { 4686 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4687 const struct sys_reg_desc *r; 4688 u64 val; 4689 int ret; 4690 4691 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4692 if (!r || sysreg_hidden(vcpu, r)) 4693 return -ENOENT; 4694 4695 if (r->get_user) { 4696 ret = (r->get_user)(vcpu, r, &val); 4697 } else { 4698 val = __vcpu_sys_reg(vcpu, r->reg); 4699 ret = 0; 4700 } 4701 4702 if (!ret) 4703 ret = put_user(val, uaddr); 4704 4705 return ret; 4706 } 4707 4708 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4709 { 4710 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4711 int err; 4712 4713 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4714 return demux_c15_get(vcpu, reg->id, uaddr); 4715 4716 err = get_invariant_sys_reg(reg->id, uaddr); 4717 if (err != -ENOENT) 4718 return err; 4719 4720 return kvm_sys_reg_get_user(vcpu, reg, 4721 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4722 } 4723 4724 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg, 4725 const struct sys_reg_desc table[], unsigned int num) 4726 { 4727 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr; 4728 const struct sys_reg_desc *r; 4729 u64 val; 4730 int ret; 4731 4732 if (get_user(val, uaddr)) 4733 return -EFAULT; 4734 4735 r = id_to_sys_reg_desc(vcpu, reg->id, table, num); 4736 if (!r || sysreg_hidden(vcpu, r)) 4737 return -ENOENT; 4738 4739 if (sysreg_user_write_ignore(vcpu, r)) 4740 return 0; 4741 4742 if (r->set_user) { 4743 ret = (r->set_user)(vcpu, r, val); 4744 } else { 4745 __vcpu_sys_reg(vcpu, r->reg) = val; 4746 ret = 0; 4747 } 4748 4749 return ret; 4750 } 4751 4752 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 4753 { 4754 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 4755 int err; 4756 4757 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 4758 return demux_c15_set(vcpu, reg->id, uaddr); 4759 4760 err = set_invariant_sys_reg(reg->id, uaddr); 4761 if (err != -ENOENT) 4762 return err; 4763 4764 return kvm_sys_reg_set_user(vcpu, reg, 4765 sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 4766 } 4767 4768 static unsigned int num_demux_regs(void) 4769 { 4770 return CSSELR_MAX; 4771 } 4772 4773 static int write_demux_regids(u64 __user *uindices) 4774 { 4775 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 4776 unsigned int i; 4777 4778 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 4779 for (i = 0; i < CSSELR_MAX; i++) { 4780 if (put_user(val | i, uindices)) 4781 return -EFAULT; 4782 uindices++; 4783 } 4784 return 0; 4785 } 4786 4787 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 4788 { 4789 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 4790 KVM_REG_ARM64_SYSREG | 4791 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 4792 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 4793 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 4794 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 4795 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 4796 } 4797 4798 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 4799 { 4800 if (!*uind) 4801 return true; 4802 4803 if (put_user(sys_reg_to_index(reg), *uind)) 4804 return false; 4805 4806 (*uind)++; 4807 return true; 4808 } 4809 4810 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 4811 const struct sys_reg_desc *rd, 4812 u64 __user **uind, 4813 unsigned int *total) 4814 { 4815 /* 4816 * Ignore registers we trap but don't save, 4817 * and for which no custom user accessor is provided. 4818 */ 4819 if (!(rd->reg || rd->get_user)) 4820 return 0; 4821 4822 if (sysreg_hidden(vcpu, rd)) 4823 return 0; 4824 4825 if (!copy_reg_to_user(rd, uind)) 4826 return -EFAULT; 4827 4828 (*total)++; 4829 return 0; 4830 } 4831 4832 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 4833 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 4834 { 4835 const struct sys_reg_desc *i2, *end2; 4836 unsigned int total = 0; 4837 int err; 4838 4839 i2 = sys_reg_descs; 4840 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 4841 4842 while (i2 != end2) { 4843 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 4844 if (err) 4845 return err; 4846 } 4847 return total; 4848 } 4849 4850 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 4851 { 4852 return ARRAY_SIZE(invariant_sys_regs) 4853 + num_demux_regs() 4854 + walk_sys_regs(vcpu, (u64 __user *)NULL); 4855 } 4856 4857 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 4858 { 4859 unsigned int i; 4860 int err; 4861 4862 /* Then give them all the invariant registers' indices. */ 4863 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 4864 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 4865 return -EFAULT; 4866 uindices++; 4867 } 4868 4869 err = walk_sys_regs(vcpu, uindices); 4870 if (err < 0) 4871 return err; 4872 uindices += err; 4873 4874 return write_demux_regids(uindices); 4875 } 4876 4877 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ 4878 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \ 4879 sys_reg_Op1(r), \ 4880 sys_reg_CRn(r), \ 4881 sys_reg_CRm(r), \ 4882 sys_reg_Op2(r)) 4883 4884 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) 4885 { 4886 const void *zero_page = page_to_virt(ZERO_PAGE(0)); 4887 u64 __user *masks = (u64 __user *)range->addr; 4888 4889 /* Only feature id range is supported, reserved[13] must be zero. */ 4890 if (range->range || 4891 memcmp(range->reserved, zero_page, sizeof(range->reserved))) 4892 return -EINVAL; 4893 4894 /* Wipe the whole thing first */ 4895 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64))) 4896 return -EFAULT; 4897 4898 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 4899 const struct sys_reg_desc *reg = &sys_reg_descs[i]; 4900 u32 encoding = reg_to_encoding(reg); 4901 u64 val; 4902 4903 if (!is_feature_id_reg(encoding) || !reg->set_user) 4904 continue; 4905 4906 if (!reg->val || 4907 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) { 4908 continue; 4909 } 4910 val = reg->val; 4911 4912 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding)))) 4913 return -EFAULT; 4914 } 4915 4916 return 0; 4917 } 4918 4919 static void vcpu_set_hcr(struct kvm_vcpu *vcpu) 4920 { 4921 struct kvm *kvm = vcpu->kvm; 4922 4923 if (has_vhe() || has_hvhe()) 4924 vcpu->arch.hcr_el2 |= HCR_E2H; 4925 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) { 4926 /* route synchronous external abort exceptions to EL2 */ 4927 vcpu->arch.hcr_el2 |= HCR_TEA; 4928 /* trap error record accesses */ 4929 vcpu->arch.hcr_el2 |= HCR_TERR; 4930 } 4931 4932 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) 4933 vcpu->arch.hcr_el2 |= HCR_FWB; 4934 4935 if (cpus_have_final_cap(ARM64_HAS_EVT) && 4936 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) && 4937 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0)) 4938 vcpu->arch.hcr_el2 |= HCR_TID4; 4939 else 4940 vcpu->arch.hcr_el2 |= HCR_TID2; 4941 4942 if (vcpu_el1_is_32bit(vcpu)) 4943 vcpu->arch.hcr_el2 &= ~HCR_RW; 4944 4945 if (kvm_has_mte(vcpu->kvm)) 4946 vcpu->arch.hcr_el2 |= HCR_ATA; 4947 4948 /* 4949 * In the absence of FGT, we cannot independently trap TLBI 4950 * Range instructions. This isn't great, but trapping all 4951 * TLBIs would be far worse. Live with it... 4952 */ 4953 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4954 vcpu->arch.hcr_el2 |= HCR_TTLBOS; 4955 } 4956 4957 void kvm_calculate_traps(struct kvm_vcpu *vcpu) 4958 { 4959 struct kvm *kvm = vcpu->kvm; 4960 4961 mutex_lock(&kvm->arch.config_lock); 4962 vcpu_set_hcr(vcpu); 4963 vcpu_set_ich_hcr(vcpu); 4964 4965 if (cpus_have_final_cap(ARM64_HAS_HCX)) { 4966 /* 4967 * In general, all HCRX_EL2 bits are gated by a feature. 4968 * The only reason we can set SMPME without checking any 4969 * feature is that its effects are not directly observable 4970 * from the guest. 4971 */ 4972 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME; 4973 4974 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) 4975 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); 4976 4977 if (kvm_has_tcr2(kvm)) 4978 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; 4979 4980 if (kvm_has_fpmr(kvm)) 4981 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; 4982 } 4983 4984 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) 4985 goto out; 4986 4987 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 | 4988 HFGxTR_EL2_nMAIR2_EL1 | 4989 HFGxTR_EL2_nS2POR_EL1 | 4990 HFGxTR_EL2_nACCDATA_EL1 | 4991 HFGxTR_EL2_nSMPRI_EL1_MASK | 4992 HFGxTR_EL2_nTPIDR2_EL0_MASK); 4993 4994 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS)) 4995 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS| 4996 HFGITR_EL2_TLBIRVALE1OS | 4997 HFGITR_EL2_TLBIRVAAE1OS | 4998 HFGITR_EL2_TLBIRVAE1OS | 4999 HFGITR_EL2_TLBIVAALE1OS | 5000 HFGITR_EL2_TLBIVALE1OS | 5001 HFGITR_EL2_TLBIVAAE1OS | 5002 HFGITR_EL2_TLBIASIDE1OS | 5003 HFGITR_EL2_TLBIVAE1OS | 5004 HFGITR_EL2_TLBIVMALLE1OS); 5005 5006 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE)) 5007 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 | 5008 HFGITR_EL2_TLBIRVALE1 | 5009 HFGITR_EL2_TLBIRVAAE1 | 5010 HFGITR_EL2_TLBIRVAE1 | 5011 HFGITR_EL2_TLBIRVAALE1IS| 5012 HFGITR_EL2_TLBIRVALE1IS | 5013 HFGITR_EL2_TLBIRVAAE1IS | 5014 HFGITR_EL2_TLBIRVAE1IS | 5015 HFGITR_EL2_TLBIRVAALE1OS| 5016 HFGITR_EL2_TLBIRVALE1OS | 5017 HFGITR_EL2_TLBIRVAAE1OS | 5018 HFGITR_EL2_TLBIRVAE1OS); 5019 5020 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) 5021 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A; 5022 5023 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2)) 5024 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP | 5025 HFGITR_EL2_ATS1E1WP); 5026 5027 if (!kvm_has_s1pie(kvm)) 5028 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 | 5029 HFGxTR_EL2_nPIR_EL1); 5030 5031 if (!kvm_has_s1poe(kvm)) 5032 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | 5033 HFGxTR_EL2_nPOR_EL0); 5034 5035 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) 5036 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | 5037 HAFGRTR_EL2_RES1); 5038 5039 if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, BRBE, IMP)) { 5040 kvm->arch.fgu[HDFGRTR_GROUP] |= (HDFGRTR_EL2_nBRBDATA | 5041 HDFGRTR_EL2_nBRBCTL | 5042 HDFGRTR_EL2_nBRBIDR); 5043 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nBRBINJ | 5044 HFGITR_EL2_nBRBIALL); 5045 } 5046 5047 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags); 5048 out: 5049 mutex_unlock(&kvm->arch.config_lock); 5050 } 5051 5052 /* 5053 * Perform last adjustments to the ID registers that are implied by the 5054 * configuration outside of the ID regs themselves, as well as any 5055 * initialisation that directly depend on these ID registers (such as 5056 * RES0/RES1 behaviours). This is not the place to configure traps though. 5057 * 5058 * Because this can be called once per CPU, changes must be idempotent. 5059 */ 5060 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu) 5061 { 5062 struct kvm *kvm = vcpu->kvm; 5063 5064 guard(mutex)(&kvm->arch.config_lock); 5065 5066 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && 5067 irqchip_in_kernel(kvm) && 5068 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { 5069 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK; 5070 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK; 5071 } 5072 5073 if (vcpu_has_nv(vcpu)) { 5074 int ret = kvm_init_nv_sysregs(vcpu); 5075 if (ret) 5076 return ret; 5077 } 5078 5079 return 0; 5080 } 5081 5082 int __init kvm_sys_reg_table_init(void) 5083 { 5084 bool valid = true; 5085 unsigned int i; 5086 int ret = 0; 5087 5088 /* Make sure tables are unique and in order. */ 5089 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false); 5090 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true); 5091 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true); 5092 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true); 5093 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true); 5094 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false); 5095 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false); 5096 5097 if (!valid) 5098 return -EINVAL; 5099 5100 /* We abuse the reset function to overwrite the table itself. */ 5101 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 5102 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 5103 5104 ret = populate_nv_trap_config(); 5105 5106 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++) 5107 ret = populate_sysreg_config(sys_reg_descs + i, i); 5108 5109 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++) 5110 ret = populate_sysreg_config(sys_insn_descs + i, i); 5111 5112 return ret; 5113 } 5114