1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/arm-smccc.h> 11 #include <linux/kvm_host.h> 12 #include <linux/types.h> 13 #include <linux/jump_label.h> 14 #include <uapi/linux/psci.h> 15 16 #include <kvm/arm_psci.h> 17 18 #include <asm/barrier.h> 19 #include <asm/cpufeature.h> 20 #include <asm/kprobes.h> 21 #include <asm/kvm_asm.h> 22 #include <asm/kvm_emulate.h> 23 #include <asm/kvm_hyp.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 29 #include <nvhe/mem_protect.h> 30 31 /* Non-VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 struct fgt_masks hfgrtr_masks; 37 struct fgt_masks hfgwtr_masks; 38 struct fgt_masks hfgitr_masks; 39 struct fgt_masks hdfgrtr_masks; 40 struct fgt_masks hdfgwtr_masks; 41 struct fgt_masks hafgrtr_masks; 42 struct fgt_masks hfgrtr2_masks; 43 struct fgt_masks hfgwtr2_masks; 44 struct fgt_masks hfgitr2_masks; 45 struct fgt_masks hdfgrtr2_masks; 46 struct fgt_masks hdfgwtr2_masks; 47 48 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); 49 50 static void __activate_traps(struct kvm_vcpu *vcpu) 51 { 52 ___activate_traps(vcpu, vcpu->arch.hcr_el2); 53 __activate_traps_common(vcpu); 54 __activate_cptr_traps(vcpu); 55 56 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 57 58 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 59 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 60 61 isb(); 62 /* 63 * At this stage, and thanks to the above isb(), S2 is 64 * configured and enabled. We can now restore the guest's S1 65 * configuration: SCTLR, and only then TCR. 66 */ 67 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 68 isb(); 69 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 70 } 71 } 72 73 static void __deactivate_traps(struct kvm_vcpu *vcpu) 74 { 75 extern char __kvm_hyp_host_vector[]; 76 77 ___deactivate_traps(vcpu); 78 79 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 80 u64 val; 81 82 /* 83 * Set the TCR and SCTLR registers in the exact opposite 84 * sequence as __activate_traps (first prevent walks, 85 * then force the MMU on). A generous sprinkling of isb() 86 * ensure that things happen in this exact order. 87 */ 88 val = read_sysreg_el1(SYS_TCR); 89 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 90 isb(); 91 val = read_sysreg_el1(SYS_SCTLR); 92 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 93 isb(); 94 } 95 96 __deactivate_traps_common(vcpu); 97 98 write_sysreg_hcr(this_cpu_ptr(&kvm_init_params)->hcr_el2); 99 100 __deactivate_cptr_traps(vcpu); 101 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 102 } 103 104 /* Save VGICv3 state on non-VHE systems */ 105 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 106 { 107 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 108 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 109 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 110 } 111 } 112 113 /* Restore VGICv3 state on non-VHE systems */ 114 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 115 { 116 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 117 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 118 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 119 } 120 } 121 122 /* 123 * Disable host events, enable guest events 124 */ 125 #ifdef CONFIG_HW_PERF_EVENTS 126 static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) 127 { 128 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 129 130 if (pmu->events_host) 131 write_sysreg(pmu->events_host, pmcntenclr_el0); 132 133 if (pmu->events_guest) 134 write_sysreg(pmu->events_guest, pmcntenset_el0); 135 136 return (pmu->events_host || pmu->events_guest); 137 } 138 139 /* 140 * Disable guest events, enable host events 141 */ 142 static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) 143 { 144 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 145 146 if (pmu->events_guest) 147 write_sysreg(pmu->events_guest, pmcntenclr_el0); 148 149 if (pmu->events_host) 150 write_sysreg(pmu->events_host, pmcntenset_el0); 151 } 152 #else 153 #define __pmu_switch_to_guest(v) ({ false; }) 154 #define __pmu_switch_to_host(v) do {} while (0) 155 #endif 156 157 /* 158 * Handler for protected VM MSR, MRS or System instruction execution in AArch64. 159 * 160 * Returns true if the hypervisor has handled the exit, and control should go 161 * back to the guest, or false if it hasn't. 162 */ 163 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code) 164 { 165 /* 166 * Make sure we handle the exit for workarounds before the pKVM 167 * handling, as the latter could decide to UNDEF. 168 */ 169 return (kvm_hyp_handle_sysreg(vcpu, exit_code) || 170 kvm_handle_pvm_sysreg(vcpu, exit_code)); 171 } 172 173 static const exit_handler_fn hyp_exit_handlers[] = { 174 [0 ... ESR_ELx_EC_MAX] = NULL, 175 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 176 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 177 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 178 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 179 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 180 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 181 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 182 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 183 }; 184 185 static const exit_handler_fn pvm_exit_handlers[] = { 186 [0 ... ESR_ELx_EC_MAX] = NULL, 187 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, 188 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted, 189 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 190 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 191 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 192 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 193 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 194 }; 195 196 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 197 { 198 if (unlikely(vcpu_is_protected(vcpu))) 199 return pvm_exit_handlers; 200 201 return hyp_exit_handlers; 202 } 203 204 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 205 { 206 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu); 207 208 synchronize_vcpu_pstate(vcpu, exit_code); 209 210 /* 211 * Some guests (e.g., protected VMs) are not be allowed to run in 212 * AArch32. The ARMv8 architecture does not give the hypervisor a 213 * mechanism to prevent a guest from dropping to AArch32 EL0 if 214 * implemented by the CPU. If the hypervisor spots a guest in such a 215 * state ensure it is handled, and don't trust the host to spot or fix 216 * it. The check below is based on the one in 217 * kvm_arch_vcpu_ioctl_run(). 218 */ 219 if (unlikely(vcpu_is_protected(vcpu) && vcpu_mode_is_32bit(vcpu))) { 220 /* 221 * As we have caught the guest red-handed, decide that it isn't 222 * fit for purpose anymore by making the vcpu invalid. The VMM 223 * can try and fix it by re-initializing the vcpu with 224 * KVM_ARM_VCPU_INIT, however, this is likely not possible for 225 * protected VMs. 226 */ 227 vcpu_clear_flag(vcpu, VCPU_INITIALIZED); 228 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT); 229 *exit_code |= ARM_EXCEPTION_IL; 230 } 231 232 return __fixup_guest_exit(vcpu, exit_code, handlers); 233 } 234 235 /* Switch to the guest for legacy non-VHE systems */ 236 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 237 { 238 struct kvm_cpu_context *host_ctxt; 239 struct kvm_cpu_context *guest_ctxt; 240 struct kvm_s2_mmu *mmu; 241 bool pmu_switch_needed; 242 u64 exit_code; 243 244 /* 245 * Having IRQs masked via PMR when entering the guest means the GIC 246 * will not signal the CPU of interrupts of lower priority, and the 247 * only way to get out will be via guest exceptions. 248 * Naturally, we want to avoid this. 249 */ 250 if (system_uses_irq_prio_masking()) { 251 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 252 pmr_sync(); 253 } 254 255 host_ctxt = host_data_ptr(host_ctxt); 256 host_ctxt->__hyp_running_vcpu = vcpu; 257 guest_ctxt = &vcpu->arch.ctxt; 258 259 pmu_switch_needed = __pmu_switch_to_guest(vcpu); 260 261 __sysreg_save_state_nvhe(host_ctxt); 262 /* 263 * We must flush and disable the SPE buffer for nVHE, as 264 * the translation regime(EL1&0) is going to be loaded with 265 * that of the guest. And we must do this before we change the 266 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and 267 * before we load guest Stage1. 268 */ 269 __debug_save_host_buffers_nvhe(vcpu); 270 271 /* 272 * We're about to restore some new MMU state. Make sure 273 * ongoing page-table walks that have started before we 274 * trapped to EL2 have completed. This also synchronises the 275 * above disabling of SPE and TRBE. 276 * 277 * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", 278 * rule R_LFHQG and subsequent information statements. 279 */ 280 dsb(nsh); 281 282 __kvm_adjust_pc(vcpu); 283 284 /* 285 * We must restore the 32-bit state before the sysregs, thanks 286 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 287 * 288 * Also, and in order to be able to deal with erratum #1319537 (A57) 289 * and #1319367 (A72), we must ensure that all VM-related sysreg are 290 * restored before we enable S2 translation. 291 */ 292 __sysreg32_restore_state(vcpu); 293 __sysreg_restore_state_nvhe(guest_ctxt); 294 295 mmu = kern_hyp_va(vcpu->arch.hw_mmu); 296 __load_stage2(mmu, kern_hyp_va(mmu->arch)); 297 __activate_traps(vcpu); 298 299 __hyp_vgic_restore_state(vcpu); 300 __timer_enable_traps(vcpu); 301 302 __debug_switch_to_guest(vcpu); 303 304 do { 305 /* Jump in the fire! */ 306 exit_code = __guest_enter(vcpu); 307 308 /* And we're baaack! */ 309 } while (fixup_guest_exit(vcpu, &exit_code)); 310 311 __sysreg_save_state_nvhe(guest_ctxt); 312 __sysreg32_save_state(vcpu); 313 __timer_disable_traps(vcpu); 314 __hyp_vgic_save_state(vcpu); 315 316 /* 317 * Same thing as before the guest run: we're about to switch 318 * the MMU context, so let's make sure we don't have any 319 * ongoing EL1&0 translations. 320 */ 321 dsb(nsh); 322 323 __deactivate_traps(vcpu); 324 __load_host_stage2(); 325 326 __sysreg_restore_state_nvhe(host_ctxt); 327 328 if (guest_owns_fp_regs()) 329 __fpsimd_save_fpexc32(vcpu); 330 331 __debug_switch_to_host(vcpu); 332 /* 333 * This must come after restoring the host sysregs, since a non-VHE 334 * system may enable SPE here and make use of the TTBRs. 335 */ 336 __debug_restore_host_buffers_nvhe(vcpu); 337 338 if (pmu_switch_needed) 339 __pmu_switch_to_host(vcpu); 340 341 /* Returning to host will clear PSR.I, remask PMR if needed */ 342 if (system_uses_irq_prio_masking()) 343 gic_write_pmr(GIC_PRIO_IRQOFF); 344 345 host_ctxt->__hyp_running_vcpu = NULL; 346 347 return exit_code; 348 } 349 350 asmlinkage void __noreturn hyp_panic(void) 351 { 352 u64 spsr = read_sysreg_el2(SYS_SPSR); 353 u64 elr = read_sysreg_el2(SYS_ELR); 354 u64 par = read_sysreg_par(); 355 struct kvm_cpu_context *host_ctxt; 356 struct kvm_vcpu *vcpu; 357 358 host_ctxt = host_data_ptr(host_ctxt); 359 vcpu = host_ctxt->__hyp_running_vcpu; 360 361 if (vcpu) { 362 __timer_disable_traps(vcpu); 363 __deactivate_traps(vcpu); 364 __load_host_stage2(); 365 __sysreg_restore_state_nvhe(host_ctxt); 366 } 367 368 /* Prepare to dump kvm nvhe hyp stacktrace */ 369 kvm_nvhe_prepare_backtrace((unsigned long)__builtin_frame_address(0), 370 _THIS_IP_); 371 372 __hyp_do_panic(host_ctxt, spsr, elr, par); 373 unreachable(); 374 } 375 376 asmlinkage void __noreturn hyp_panic_bad_stack(void) 377 { 378 hyp_panic(); 379 } 380 381 asmlinkage void kvm_unexpected_el2_exception(void) 382 { 383 __kvm_unexpected_el2_exception(); 384 } 385