xref: /linux/arch/arm64/kernel/sleep.S (revision 693d5639b44a8f3787444902d3600edc7e0105a2)
1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */
295322526SLorenzo Pieralisi#include <linux/errno.h>
395322526SLorenzo Pieralisi#include <linux/linkage.h>
495322526SLorenzo Pieralisi#include <asm/asm-offsets.h>
595322526SLorenzo Pieralisi#include <asm/assembler.h>
695322526SLorenzo Pieralisi
795322526SLorenzo Pieralisi	.text
895322526SLorenzo Pieralisi/*
995322526SLorenzo Pieralisi * Implementation of MPIDR_EL1 hash algorithm through shifting
1095322526SLorenzo Pieralisi * and OR'ing.
1195322526SLorenzo Pieralisi *
1295322526SLorenzo Pieralisi * @dst: register containing hash result
1395322526SLorenzo Pieralisi * @rs0: register containing affinity level 0 bit shift
1495322526SLorenzo Pieralisi * @rs1: register containing affinity level 1 bit shift
1595322526SLorenzo Pieralisi * @rs2: register containing affinity level 2 bit shift
1695322526SLorenzo Pieralisi * @rs3: register containing affinity level 3 bit shift
1795322526SLorenzo Pieralisi * @mpidr: register containing MPIDR_EL1 value
1895322526SLorenzo Pieralisi * @mask: register containing MPIDR mask
1995322526SLorenzo Pieralisi *
2095322526SLorenzo Pieralisi * Pseudo C-code:
2195322526SLorenzo Pieralisi *
2295322526SLorenzo Pieralisi *u32 dst;
2395322526SLorenzo Pieralisi *
2495322526SLorenzo Pieralisi *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
2595322526SLorenzo Pieralisi *	u32 aff0, aff1, aff2, aff3;
2695322526SLorenzo Pieralisi *	u64 mpidr_masked = mpidr & mask;
2795322526SLorenzo Pieralisi *	aff0 = mpidr_masked & 0xff;
2895322526SLorenzo Pieralisi *	aff1 = mpidr_masked & 0xff00;
2995322526SLorenzo Pieralisi *	aff2 = mpidr_masked & 0xff0000;
3095322526SLorenzo Pieralisi *	aff2 = mpidr_masked & 0xff00000000;
3195322526SLorenzo Pieralisi *	dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
3295322526SLorenzo Pieralisi *}
3395322526SLorenzo Pieralisi * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
3495322526SLorenzo Pieralisi * Output register: dst
3595322526SLorenzo Pieralisi * Note: input and output registers must be disjoint register sets
3695322526SLorenzo Pieralisi         (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
3795322526SLorenzo Pieralisi */
3895322526SLorenzo Pieralisi	.macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
3995322526SLorenzo Pieralisi	and	\mpidr, \mpidr, \mask		// mask out MPIDR bits
4095322526SLorenzo Pieralisi	and	\dst, \mpidr, #0xff		// mask=aff0
4195322526SLorenzo Pieralisi	lsr	\dst ,\dst, \rs0		// dst=aff0>>rs0
4295322526SLorenzo Pieralisi	and	\mask, \mpidr, #0xff00		// mask = aff1
4395322526SLorenzo Pieralisi	lsr	\mask ,\mask, \rs1
4495322526SLorenzo Pieralisi	orr	\dst, \dst, \mask		// dst|=(aff1>>rs1)
4595322526SLorenzo Pieralisi	and	\mask, \mpidr, #0xff0000	// mask = aff2
4695322526SLorenzo Pieralisi	lsr	\mask ,\mask, \rs2
4795322526SLorenzo Pieralisi	orr	\dst, \dst, \mask		// dst|=(aff2>>rs2)
4895322526SLorenzo Pieralisi	and	\mask, \mpidr, #0xff00000000	// mask = aff3
4995322526SLorenzo Pieralisi	lsr	\mask ,\mask, \rs3
5095322526SLorenzo Pieralisi	orr	\dst, \dst, \mask		// dst|=(aff3>>rs3)
5195322526SLorenzo Pieralisi	.endm
5295322526SLorenzo Pieralisi/*
53adc9b2dfSJames Morse * Save CPU state in the provided sleep_stack_data area, and publish its
54adc9b2dfSJames Morse * location for cpu_resume()'s use in sleep_save_stash.
5595322526SLorenzo Pieralisi *
56adc9b2dfSJames Morse * cpu_resume() will restore this saved state, and return. Because the
57adc9b2dfSJames Morse * link-register is saved and restored, it will appear to return from this
58adc9b2dfSJames Morse * function. So that the caller can tell the suspend/resume paths apart,
59adc9b2dfSJames Morse * __cpu_suspend_enter() will always return a non-zero value, whereas the
60adc9b2dfSJames Morse * path through cpu_resume() will return 0.
61adc9b2dfSJames Morse *
62adc9b2dfSJames Morse *  x0 = struct sleep_stack_data area
6395322526SLorenzo Pieralisi */
64714f5992SLorenzo PieralisiENTRY(__cpu_suspend_enter)
65adc9b2dfSJames Morse	stp	x29, lr, [x0, #SLEEP_STACK_DATA_CALLEE_REGS]
66adc9b2dfSJames Morse	stp	x19, x20, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+16]
67adc9b2dfSJames Morse	stp	x21, x22, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+32]
68adc9b2dfSJames Morse	stp	x23, x24, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+48]
69adc9b2dfSJames Morse	stp	x25, x26, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+64]
70adc9b2dfSJames Morse	stp	x27, x28, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+80]
71adc9b2dfSJames Morse
72adc9b2dfSJames Morse	/* save the sp in cpu_suspend_ctx */
7395322526SLorenzo Pieralisi	mov	x2, sp
74adc9b2dfSJames Morse	str	x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP]
75adc9b2dfSJames Morse
76adc9b2dfSJames Morse	/* find the mpidr_hash */
77b5fe2429SArd Biesheuvel	ldr_l	x1, sleep_save_stash
7895322526SLorenzo Pieralisi	mrs	x7, mpidr_el1
79b5fe2429SArd Biesheuvel	adr_l	x9, mpidr_hash
8095322526SLorenzo Pieralisi	ldr	x10, [x9, #MPIDR_HASH_MASK]
8195322526SLorenzo Pieralisi	/*
8295322526SLorenzo Pieralisi	 * Following code relies on the struct mpidr_hash
8395322526SLorenzo Pieralisi	 * members size.
8495322526SLorenzo Pieralisi	 */
8595322526SLorenzo Pieralisi	ldp	w3, w4, [x9, #MPIDR_HASH_SHIFTS]
8695322526SLorenzo Pieralisi	ldp	w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
8795322526SLorenzo Pieralisi	compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
88714f5992SLorenzo Pieralisi	add	x1, x1, x8, lsl #3
89adc9b2dfSJames Morse
90cabe1c81SJames Morse	str	x0, [x1]
91cabe1c81SJames Morse	add	x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
92adc9b2dfSJames Morse	stp	x29, lr, [sp, #-16]!
93cabe1c81SJames Morse	bl	cpu_do_suspend
94adc9b2dfSJames Morse	ldp	x29, lr, [sp], #16
95adc9b2dfSJames Morse	mov	x0, #1
9695322526SLorenzo Pieralisi	ret
97714f5992SLorenzo PieralisiENDPROC(__cpu_suspend_enter)
9895322526SLorenzo Pieralisi
99439e70e2SWill Deacon	.pushsection ".idmap.text", "awx"
10095322526SLorenzo PieralisiENTRY(cpu_resume)
10195322526SLorenzo Pieralisi	bl	el2_setup		// if in EL2 drop to EL1 cleanly
102b5fe2429SArd Biesheuvel	bl	__cpu_setup
103cabe1c81SJames Morse	/* enable the MMU early - so we can access sleep_save_stash by va */
104*693d5639SJun Yao	adrp	x1, swapper_pg_dir
1059dcf7914SArd Biesheuvel	bl	__enable_mmu
106bc9f3d77SArd Biesheuvel	ldr	x8, =_cpu_resume
107bc9f3d77SArd Biesheuvel	br	x8
1089dcf7914SArd BiesheuvelENDPROC(cpu_resume)
109bc9f3d77SArd Biesheuvel	.ltorg
110bc9f3d77SArd Biesheuvel	.popsection
111bc9f3d77SArd Biesheuvel
112dc002475SArd BiesheuvelENTRY(_cpu_resume)
11395322526SLorenzo Pieralisi	mrs	x1, mpidr_el1
114b5fe2429SArd Biesheuvel	adr_l	x8, mpidr_hash		// x8 = struct mpidr_hash virt address
115b5fe2429SArd Biesheuvel
11695322526SLorenzo Pieralisi	/* retrieve mpidr_hash members to compute the hash */
11795322526SLorenzo Pieralisi	ldr	x2, [x8, #MPIDR_HASH_MASK]
11895322526SLorenzo Pieralisi	ldp	w3, w4, [x8, #MPIDR_HASH_SHIFTS]
11995322526SLorenzo Pieralisi	ldp	w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)]
12095322526SLorenzo Pieralisi	compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
121b5fe2429SArd Biesheuvel
12295322526SLorenzo Pieralisi	/* x7 contains hash index, let's use it to grab context pointer */
123cabe1c81SJames Morse	ldr_l	x0, sleep_save_stash
12495322526SLorenzo Pieralisi	ldr	x0, [x0, x7, lsl #3]
125adc9b2dfSJames Morse	add	x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS
126adc9b2dfSJames Morse	add	x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
12795322526SLorenzo Pieralisi	/* load sp from context */
12895322526SLorenzo Pieralisi	ldr	x2, [x0, #CPU_CTX_SP]
12995322526SLorenzo Pieralisi	mov	sp, x2
13095322526SLorenzo Pieralisi	/*
131cabe1c81SJames Morse	 * cpu_do_resume expects x0 to contain context address pointer
13295322526SLorenzo Pieralisi	 */
133cabe1c81SJames Morse	bl	cpu_do_resume
134cabe1c81SJames Morse
135cabe1c81SJames Morse#ifdef CONFIG_KASAN
136cabe1c81SJames Morse	mov	x0, sp
1379f7d416cSDmitry Vyukov	bl	kasan_unpoison_task_stack_below
138cabe1c81SJames Morse#endif
139cabe1c81SJames Morse
140adc9b2dfSJames Morse	ldp	x19, x20, [x29, #16]
141adc9b2dfSJames Morse	ldp	x21, x22, [x29, #32]
142adc9b2dfSJames Morse	ldp	x23, x24, [x29, #48]
143adc9b2dfSJames Morse	ldp	x25, x26, [x29, #64]
144adc9b2dfSJames Morse	ldp	x27, x28, [x29, #80]
145adc9b2dfSJames Morse	ldp	x29, lr, [x29]
146cabe1c81SJames Morse	mov	x0, #0
147cabe1c81SJames Morse	ret
148cabe1c81SJames MorseENDPROC(_cpu_resume)
149