1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 #include <asm/vncr_mapping.h> 31 32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 7 43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 44 45 #define KVM_REQ_SLEEP \ 46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8) 55 56 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 57 KVM_DIRTY_LOG_INITIALLY_SET) 58 59 #define KVM_HAVE_MMU_RWLOCK 60 61 /* 62 * Mode of operation configurable with kvm-arm.mode early param. 63 * See Documentation/admin-guide/kernel-parameters.txt for more information. 64 */ 65 enum kvm_mode { 66 KVM_MODE_DEFAULT, 67 KVM_MODE_PROTECTED, 68 KVM_MODE_NV, 69 KVM_MODE_NONE, 70 }; 71 #ifdef CONFIG_KVM 72 enum kvm_mode kvm_get_mode(void); 73 #else 74 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 75 #endif 76 77 extern unsigned int __ro_after_init kvm_sve_max_vl; 78 extern unsigned int __ro_after_init kvm_host_sve_max_vl; 79 int __init kvm_arm_init_sve(void); 80 81 u32 __attribute_const__ kvm_target_cpu(void); 82 void kvm_reset_vcpu(struct kvm_vcpu *vcpu); 83 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 84 85 struct kvm_hyp_memcache { 86 phys_addr_t head; 87 unsigned long nr_pages; 88 struct pkvm_mapping *mapping; /* only used from EL1 */ 89 }; 90 91 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 92 phys_addr_t *p, 93 phys_addr_t (*to_pa)(void *virt)) 94 { 95 *p = mc->head; 96 mc->head = to_pa(p); 97 mc->nr_pages++; 98 } 99 100 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 101 void *(*to_va)(phys_addr_t phys)) 102 { 103 phys_addr_t *p = to_va(mc->head); 104 105 if (!mc->nr_pages) 106 return NULL; 107 108 mc->head = *p; 109 mc->nr_pages--; 110 111 return p; 112 } 113 114 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 115 unsigned long min_pages, 116 void *(*alloc_fn)(void *arg), 117 phys_addr_t (*to_pa)(void *virt), 118 void *arg) 119 { 120 while (mc->nr_pages < min_pages) { 121 phys_addr_t *p = alloc_fn(arg); 122 123 if (!p) 124 return -ENOMEM; 125 push_hyp_memcache(mc, p, to_pa); 126 } 127 128 return 0; 129 } 130 131 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 132 void (*free_fn)(void *virt, void *arg), 133 void *(*to_va)(phys_addr_t phys), 134 void *arg) 135 { 136 while (mc->nr_pages) 137 free_fn(pop_hyp_memcache(mc, to_va), arg); 138 } 139 140 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 141 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 142 143 struct kvm_vmid { 144 atomic64_t id; 145 }; 146 147 struct kvm_s2_mmu { 148 struct kvm_vmid vmid; 149 150 /* 151 * stage2 entry level table 152 * 153 * Two kvm_s2_mmu structures in the same VM can point to the same 154 * pgd here. This happens when running a guest using a 155 * translation regime that isn't affected by its own stage-2 156 * translation, such as a non-VHE hypervisor running at vEL2, or 157 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 158 * canonical stage-2 page tables. 159 */ 160 phys_addr_t pgd_phys; 161 struct kvm_pgtable *pgt; 162 163 /* 164 * VTCR value used on the host. For a non-NV guest (or a NV 165 * guest that runs in a context where its own S2 doesn't 166 * apply), its T0SZ value reflects that of the IPA size. 167 * 168 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to 169 * the guest. 170 */ 171 u64 vtcr; 172 173 /* The last vcpu id that ran on each physical CPU */ 174 int __percpu *last_vcpu_ran; 175 176 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 177 /* 178 * Memory cache used to split 179 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 180 * is used to allocate stage2 page tables while splitting huge 181 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 182 * influences both the capacity of the split page cache, and 183 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 184 * too high. 185 * 186 * Protected by kvm->slots_lock. 187 */ 188 struct kvm_mmu_memory_cache split_page_cache; 189 uint64_t split_page_chunk_size; 190 191 struct kvm_arch *arch; 192 193 /* 194 * For a shadow stage-2 MMU, the virtual vttbr used by the 195 * host to parse the guest S2. 196 * This either contains: 197 * - the virtual VTTBR programmed by the guest hypervisor with 198 * CnP cleared 199 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid 200 * 201 * We also cache the full VTCR which gets used for TLB invalidation, 202 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted 203 * to be cached in a TLB" to the letter. 204 */ 205 u64 tlb_vttbr; 206 u64 tlb_vtcr; 207 208 /* 209 * true when this represents a nested context where virtual 210 * HCR_EL2.VM == 1 211 */ 212 bool nested_stage2_enabled; 213 214 /* 215 * true when this MMU needs to be unmapped before being used for a new 216 * purpose. 217 */ 218 bool pending_unmap; 219 220 /* 221 * 0: Nobody is currently using this, check vttbr for validity 222 * >0: Somebody is actively using this. 223 */ 224 atomic_t refcnt; 225 }; 226 227 struct kvm_arch_memory_slot { 228 }; 229 230 /** 231 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 232 * 233 * @std_bmap: Bitmap of standard secure service calls 234 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 235 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 236 */ 237 struct kvm_smccc_features { 238 unsigned long std_bmap; 239 unsigned long std_hyp_bmap; 240 unsigned long vendor_hyp_bmap; 241 }; 242 243 typedef unsigned int pkvm_handle_t; 244 245 struct kvm_protected_vm { 246 pkvm_handle_t handle; 247 struct kvm_hyp_memcache teardown_mc; 248 bool enabled; 249 }; 250 251 struct kvm_mpidr_data { 252 u64 mpidr_mask; 253 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx); 254 }; 255 256 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr) 257 { 258 unsigned long index = 0, mask = data->mpidr_mask; 259 unsigned long aff = mpidr & MPIDR_HWID_BITMASK; 260 261 bitmap_gather(&index, &aff, &mask, fls(mask)); 262 263 return index; 264 } 265 266 struct kvm_sysreg_masks; 267 268 enum fgt_group_id { 269 __NO_FGT_GROUP__, 270 HFGxTR_GROUP, 271 HDFGRTR_GROUP, 272 HDFGWTR_GROUP = HDFGRTR_GROUP, 273 HFGITR_GROUP, 274 HAFGRTR_GROUP, 275 276 /* Must be last */ 277 __NR_FGT_GROUP_IDS__ 278 }; 279 280 struct kvm_arch { 281 struct kvm_s2_mmu mmu; 282 283 /* 284 * Fine-Grained UNDEF, mimicking the FGT layout defined by the 285 * architecture. We track them globally, as we present the 286 * same feature-set to all vcpus. 287 * 288 * Index 0 is currently spare. 289 */ 290 u64 fgu[__NR_FGT_GROUP_IDS__]; 291 292 /* 293 * Stage 2 paging state for VMs with nested S2 using a virtual 294 * VMID. 295 */ 296 struct kvm_s2_mmu *nested_mmus; 297 size_t nested_mmus_size; 298 int nested_mmus_next; 299 300 /* Interrupt controller */ 301 struct vgic_dist vgic; 302 303 /* Timers */ 304 struct arch_timer_vm_data timer_data; 305 306 /* Mandated version of PSCI */ 307 u32 psci_version; 308 309 /* Protects VM-scoped configuration data */ 310 struct mutex config_lock; 311 312 /* 313 * If we encounter a data abort without valid instruction syndrome 314 * information, report this to user space. User space can (and 315 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 316 * supported. 317 */ 318 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 319 /* Memory Tagging Extension enabled for the guest */ 320 #define KVM_ARCH_FLAG_MTE_ENABLED 1 321 /* At least one vCPU has ran in the VM */ 322 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 323 /* The vCPU feature set for the VM is configured */ 324 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 325 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 326 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 327 /* VM counter offset */ 328 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 329 /* Timer PPIs made immutable */ 330 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 331 /* Initial ID reg values loaded */ 332 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7 333 /* Fine-Grained UNDEF initialised */ 334 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8 335 /* SVE exposed to guest */ 336 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9 337 unsigned long flags; 338 339 /* VM-wide vCPU feature set */ 340 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 341 342 /* MPIDR to vcpu index mapping, optional */ 343 struct kvm_mpidr_data *mpidr_data; 344 345 /* 346 * VM-wide PMU filter, implemented as a bitmap and big enough for 347 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 348 */ 349 unsigned long *pmu_filter; 350 struct arm_pmu *arm_pmu; 351 352 cpumask_var_t supported_cpus; 353 354 /* PMCR_EL0.N value for the guest */ 355 u8 pmcr_n; 356 357 /* Iterator for idreg debugfs */ 358 u8 idreg_debugfs_iter; 359 360 /* Hypercall features firmware registers' descriptor */ 361 struct kvm_smccc_features smccc_feat; 362 struct maple_tree smccc_filter; 363 364 /* 365 * Emulated CPU ID registers per VM 366 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 367 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 368 * 369 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 370 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 371 */ 372 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 373 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 374 u64 id_regs[KVM_ARM_ID_REG_NUM]; 375 376 u64 ctr_el0; 377 378 /* Masks for VNCR-backed and general EL2 sysregs */ 379 struct kvm_sysreg_masks *sysreg_masks; 380 381 /* 382 * For an untrusted host VM, 'pkvm.handle' is used to lookup 383 * the associated pKVM instance in the hypervisor. 384 */ 385 struct kvm_protected_vm pkvm; 386 }; 387 388 struct kvm_vcpu_fault_info { 389 u64 esr_el2; /* Hyp Syndrom Register */ 390 u64 far_el2; /* Hyp Fault Address Register */ 391 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 392 u64 disr_el1; /* Deferred [SError] Status Register */ 393 }; 394 395 /* 396 * VNCR() just places the VNCR_capable registers in the enum after 397 * __VNCR_START__, and the value (after correction) to be an 8-byte offset 398 * from the VNCR base. As we don't require the enum to be otherwise ordered, 399 * we need the terrible hack below to ensure that we correctly size the 400 * sys_regs array, no matter what. 401 * 402 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful 403 * treasure trove of bit hacks: 404 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax 405 */ 406 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y)))) 407 #define VNCR(r) \ 408 __before_##r, \ 409 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \ 410 __after_##r = __MAX__(__before_##r - 1, r) 411 412 #define MARKER(m) \ 413 m, __after_##m = m - 1 414 415 enum vcpu_sysreg { 416 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 417 MPIDR_EL1, /* MultiProcessor Affinity Register */ 418 CLIDR_EL1, /* Cache Level ID Register */ 419 CSSELR_EL1, /* Cache Size Selection Register */ 420 TPIDR_EL0, /* Thread ID, User R/W */ 421 TPIDRRO_EL0, /* Thread ID, User R/O */ 422 TPIDR_EL1, /* Thread ID, Privileged */ 423 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 424 PAR_EL1, /* Physical Address Register */ 425 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 426 OSLSR_EL1, /* OS Lock Status Register */ 427 DISR_EL1, /* Deferred Interrupt Status Register */ 428 429 /* Performance Monitors Registers */ 430 PMCR_EL0, /* Control Register */ 431 PMSELR_EL0, /* Event Counter Selection Register */ 432 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 433 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 434 PMCCNTR_EL0, /* Cycle Counter Register */ 435 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 436 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 437 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 438 PMCNTENSET_EL0, /* Count Enable Set Register */ 439 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 440 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 441 PMUSERENR_EL0, /* User Enable Register */ 442 443 /* Pointer Authentication Registers in a strict increasing order. */ 444 APIAKEYLO_EL1, 445 APIAKEYHI_EL1, 446 APIBKEYLO_EL1, 447 APIBKEYHI_EL1, 448 APDAKEYLO_EL1, 449 APDAKEYHI_EL1, 450 APDBKEYLO_EL1, 451 APDBKEYHI_EL1, 452 APGAKEYLO_EL1, 453 APGAKEYHI_EL1, 454 455 /* Memory Tagging Extension registers */ 456 RGSR_EL1, /* Random Allocation Tag Seed Register */ 457 GCR_EL1, /* Tag Control Register */ 458 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 459 460 POR_EL0, /* Permission Overlay Register 0 (EL0) */ 461 462 /* FP/SIMD/SVE */ 463 SVCR, 464 FPMR, 465 466 /* 32bit specific registers. */ 467 DACR32_EL2, /* Domain Access Control Register */ 468 IFSR32_EL2, /* Instruction Fault Status Register */ 469 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 470 DBGVCR32_EL2, /* Debug Vector Catch Register */ 471 472 /* EL2 registers */ 473 SCTLR_EL2, /* System Control Register (EL2) */ 474 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 475 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 476 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 477 ZCR_EL2, /* SVE Control Register (EL2) */ 478 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 479 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 480 TCR_EL2, /* Translation Control Register (EL2) */ 481 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ 482 PIR_EL2, /* Permission Indirection Register 1 (EL2) */ 483 POR_EL2, /* Permission Overlay Register 2 (EL2) */ 484 SPSR_EL2, /* EL2 saved program status register */ 485 ELR_EL2, /* EL2 exception link register */ 486 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 487 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 488 ESR_EL2, /* Exception Syndrome Register (EL2) */ 489 FAR_EL2, /* Fault Address Register (EL2) */ 490 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 491 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 492 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 493 VBAR_EL2, /* Vector Base Address Register (EL2) */ 494 RVBAR_EL2, /* Reset Vector Base Address Register */ 495 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 496 SP_EL2, /* EL2 Stack Pointer */ 497 CNTHP_CTL_EL2, 498 CNTHP_CVAL_EL2, 499 CNTHV_CTL_EL2, 500 CNTHV_CVAL_EL2, 501 502 /* Anything from this can be RES0/RES1 sanitised */ 503 MARKER(__SANITISED_REG_START__), 504 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 505 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 506 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 507 508 /* Any VNCR-capable reg goes after this point */ 509 MARKER(__VNCR_START__), 510 511 VNCR(SCTLR_EL1),/* System Control Register */ 512 VNCR(ACTLR_EL1),/* Auxiliary Control Register */ 513 VNCR(CPACR_EL1),/* Coprocessor Access Control */ 514 VNCR(ZCR_EL1), /* SVE Control */ 515 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ 516 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ 517 VNCR(TCR_EL1), /* Translation Control Register */ 518 VNCR(TCR2_EL1), /* Extended Translation Control Register */ 519 VNCR(ESR_EL1), /* Exception Syndrome Register */ 520 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */ 521 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */ 522 VNCR(FAR_EL1), /* Fault Address Register */ 523 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */ 524 VNCR(VBAR_EL1), /* Vector Base Address Register */ 525 VNCR(CONTEXTIDR_EL1), /* Context ID Register */ 526 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */ 527 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */ 528 VNCR(ELR_EL1), 529 VNCR(SP_EL1), 530 VNCR(SPSR_EL1), 531 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */ 532 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */ 533 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */ 534 VNCR(HCR_EL2), /* Hypervisor Configuration Register */ 535 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */ 536 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */ 537 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */ 538 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */ 539 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */ 540 541 /* Permission Indirection Extension registers */ 542 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */ 543 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */ 544 545 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ 546 547 VNCR(HFGRTR_EL2), 548 VNCR(HFGWTR_EL2), 549 VNCR(HFGITR_EL2), 550 VNCR(HDFGRTR_EL2), 551 VNCR(HDFGWTR_EL2), 552 VNCR(HAFGRTR_EL2), 553 554 VNCR(CNTVOFF_EL2), 555 VNCR(CNTV_CVAL_EL0), 556 VNCR(CNTV_CTL_EL0), 557 VNCR(CNTP_CVAL_EL0), 558 VNCR(CNTP_CTL_EL0), 559 560 VNCR(ICH_HCR_EL2), 561 562 NR_SYS_REGS /* Nothing after this line! */ 563 }; 564 565 struct kvm_sysreg_masks { 566 struct { 567 u64 res0; 568 u64 res1; 569 } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 570 }; 571 572 struct kvm_cpu_context { 573 struct user_pt_regs regs; /* sp = sp_el0 */ 574 575 u64 spsr_abt; 576 u64 spsr_und; 577 u64 spsr_irq; 578 u64 spsr_fiq; 579 580 struct user_fpsimd_state fp_regs; 581 582 u64 sys_regs[NR_SYS_REGS]; 583 584 struct kvm_vcpu *__hyp_running_vcpu; 585 586 /* This pointer has to be 4kB aligned. */ 587 u64 *vncr_array; 588 }; 589 590 struct cpu_sve_state { 591 __u64 zcr_el1; 592 593 /* 594 * Ordering is important since __sve_save_state/__sve_restore_state 595 * relies on it. 596 */ 597 __u32 fpsr; 598 __u32 fpcr; 599 600 /* Must be SVE_VQ_BYTES (128 bit) aligned. */ 601 __u8 sve_regs[]; 602 }; 603 604 /* 605 * This structure is instantiated on a per-CPU basis, and contains 606 * data that is: 607 * 608 * - tied to a single physical CPU, and 609 * - either have a lifetime that does not extend past vcpu_put() 610 * - or is an invariant for the lifetime of the system 611 * 612 * Use host_data_ptr(field) as a way to access a pointer to such a 613 * field. 614 */ 615 struct kvm_host_data { 616 #define KVM_HOST_DATA_FLAG_HAS_SPE 0 617 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1 618 #define KVM_HOST_DATA_FLAG_HOST_SVE_ENABLED 2 619 #define KVM_HOST_DATA_FLAG_HOST_SME_ENABLED 3 620 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4 621 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5 622 unsigned long flags; 623 624 struct kvm_cpu_context host_ctxt; 625 626 /* 627 * All pointers in this union are hyp VA. 628 * sve_state is only used in pKVM and if system_supports_sve(). 629 */ 630 union { 631 struct user_fpsimd_state *fpsimd_state; 632 struct cpu_sve_state *sve_state; 633 }; 634 635 union { 636 /* HYP VA pointer to the host storage for FPMR */ 637 u64 *fpmr_ptr; 638 /* 639 * Used by pKVM only, as it needs to provide storage 640 * for the host 641 */ 642 u64 fpmr; 643 }; 644 645 /* Ownership of the FP regs */ 646 enum { 647 FP_STATE_FREE, 648 FP_STATE_HOST_OWNED, 649 FP_STATE_GUEST_OWNED, 650 } fp_owner; 651 652 /* 653 * host_debug_state contains the host registers which are 654 * saved and restored during world switches. 655 */ 656 struct { 657 /* {Break,watch}point registers */ 658 struct kvm_guest_debug_arch regs; 659 /* Statistical profiling extension */ 660 u64 pmscr_el1; 661 /* Self-hosted trace */ 662 u64 trfcr_el1; 663 /* Values of trap registers for the host before guest entry. */ 664 u64 mdcr_el2; 665 } host_debug_state; 666 667 /* Guest trace filter value */ 668 u64 trfcr_while_in_guest; 669 670 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */ 671 unsigned int nr_event_counters; 672 673 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */ 674 unsigned int debug_brps; 675 unsigned int debug_wrps; 676 }; 677 678 struct kvm_host_psci_config { 679 /* PSCI version used by host. */ 680 u32 version; 681 u32 smccc_version; 682 683 /* Function IDs used by host if version is v0.1. */ 684 struct psci_0_1_function_ids function_ids_0_1; 685 686 bool psci_0_1_cpu_suspend_implemented; 687 bool psci_0_1_cpu_on_implemented; 688 bool psci_0_1_cpu_off_implemented; 689 bool psci_0_1_migrate_implemented; 690 }; 691 692 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 693 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 694 695 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 696 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 697 698 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 699 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 700 701 struct vcpu_reset_state { 702 unsigned long pc; 703 unsigned long r0; 704 bool be; 705 bool reset; 706 }; 707 708 struct kvm_vcpu_arch { 709 struct kvm_cpu_context ctxt; 710 711 /* 712 * Guest floating point state 713 * 714 * The architecture has two main floating point extensions, 715 * the original FPSIMD and SVE. These have overlapping 716 * register views, with the FPSIMD V registers occupying the 717 * low 128 bits of the SVE Z registers. When the core 718 * floating point code saves the register state of a task it 719 * records which view it saved in fp_type. 720 */ 721 void *sve_state; 722 enum fp_type fp_type; 723 unsigned int sve_max_vl; 724 725 /* Stage 2 paging state used by the hardware on next switch */ 726 struct kvm_s2_mmu *hw_mmu; 727 728 /* Values of trap registers for the guest. */ 729 u64 hcr_el2; 730 u64 hcrx_el2; 731 u64 mdcr_el2; 732 733 /* Exception Information */ 734 struct kvm_vcpu_fault_info fault; 735 736 /* Configuration flags, set once and for all before the vcpu can run */ 737 u8 cflags; 738 739 /* Input flags to the hypervisor code, potentially cleared after use */ 740 u8 iflags; 741 742 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 743 u8 sflags; 744 745 /* 746 * Don't run the guest (internal implementation need). 747 * 748 * Contrary to the flags above, this is set/cleared outside of 749 * a vcpu context, and thus cannot be mixed with the flags 750 * themselves (or the flag accesses need to be made atomic). 751 */ 752 bool pause; 753 754 /* 755 * We maintain more than a single set of debug registers to support 756 * debugging the guest from the host and to maintain separate host and 757 * guest state during world switches. vcpu_debug_state are the debug 758 * registers of the vcpu as the guest sees them. 759 * 760 * external_debug_state contains the debug values we want to debug the 761 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl. 762 */ 763 struct kvm_guest_debug_arch vcpu_debug_state; 764 struct kvm_guest_debug_arch external_debug_state; 765 u64 external_mdscr_el1; 766 767 enum { 768 VCPU_DEBUG_FREE, 769 VCPU_DEBUG_HOST_OWNED, 770 VCPU_DEBUG_GUEST_OWNED, 771 } debug_owner; 772 773 /* VGIC state */ 774 struct vgic_cpu vgic_cpu; 775 struct arch_timer_cpu timer_cpu; 776 struct kvm_pmu pmu; 777 778 /* vcpu power state */ 779 struct kvm_mp_state mp_state; 780 spinlock_t mp_state_lock; 781 782 /* Cache some mmu pages needed inside spinlock regions */ 783 struct kvm_mmu_memory_cache mmu_page_cache; 784 785 /* Pages to top-up the pKVM/EL2 guest pool */ 786 struct kvm_hyp_memcache pkvm_memcache; 787 788 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 789 u64 vsesr_el2; 790 791 /* Additional reset state */ 792 struct vcpu_reset_state reset_state; 793 794 /* Guest PV state */ 795 struct { 796 u64 last_steal; 797 gpa_t base; 798 } steal; 799 800 /* Per-vcpu CCSIDR override or NULL */ 801 u32 *ccsidr; 802 }; 803 804 /* 805 * Each 'flag' is composed of a comma-separated triplet: 806 * 807 * - the flag-set it belongs to in the vcpu->arch structure 808 * - the value for that flag 809 * - the mask for that flag 810 * 811 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 812 * unpack_vcpu_flag() extract the flag value from the triplet for 813 * direct use outside of the flag accessors. 814 */ 815 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 816 817 #define __unpack_flag(_set, _f, _m) _f 818 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 819 820 #define __build_check_flag(v, flagset, f, m) \ 821 do { \ 822 typeof(v->arch.flagset) *_fset; \ 823 \ 824 /* Check that the flags fit in the mask */ \ 825 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 826 /* Check that the flags fit in the type */ \ 827 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 828 } while (0) 829 830 #define __vcpu_get_flag(v, flagset, f, m) \ 831 ({ \ 832 __build_check_flag(v, flagset, f, m); \ 833 \ 834 READ_ONCE(v->arch.flagset) & (m); \ 835 }) 836 837 /* 838 * Note that the set/clear accessors must be preempt-safe in order to 839 * avoid nesting them with load/put which also manipulate flags... 840 */ 841 #ifdef __KVM_NVHE_HYPERVISOR__ 842 /* the nVHE hypervisor is always non-preemptible */ 843 #define __vcpu_flags_preempt_disable() 844 #define __vcpu_flags_preempt_enable() 845 #else 846 #define __vcpu_flags_preempt_disable() preempt_disable() 847 #define __vcpu_flags_preempt_enable() preempt_enable() 848 #endif 849 850 #define __vcpu_set_flag(v, flagset, f, m) \ 851 do { \ 852 typeof(v->arch.flagset) *fset; \ 853 \ 854 __build_check_flag(v, flagset, f, m); \ 855 \ 856 fset = &v->arch.flagset; \ 857 __vcpu_flags_preempt_disable(); \ 858 if (HWEIGHT(m) > 1) \ 859 *fset &= ~(m); \ 860 *fset |= (f); \ 861 __vcpu_flags_preempt_enable(); \ 862 } while (0) 863 864 #define __vcpu_clear_flag(v, flagset, f, m) \ 865 do { \ 866 typeof(v->arch.flagset) *fset; \ 867 \ 868 __build_check_flag(v, flagset, f, m); \ 869 \ 870 fset = &v->arch.flagset; \ 871 __vcpu_flags_preempt_disable(); \ 872 *fset &= ~(m); \ 873 __vcpu_flags_preempt_enable(); \ 874 } while (0) 875 876 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 877 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 878 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 879 880 /* KVM_ARM_VCPU_INIT completed */ 881 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) 882 /* SVE config completed */ 883 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 884 885 /* Exception pending */ 886 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 887 /* 888 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 889 * be set together with an exception... 890 */ 891 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 892 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 893 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 894 895 /* Helpers to encode exceptions with minimum fuss */ 896 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 897 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 898 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 899 900 /* 901 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 902 * values: 903 * 904 * For AArch32 EL1: 905 */ 906 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 907 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 908 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 909 /* For AArch64: */ 910 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 911 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 912 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 913 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 914 /* For AArch64 with NV: */ 915 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 916 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 917 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 918 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 919 920 /* Physical CPU not in supported_cpus */ 921 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0)) 922 /* WFIT instruction trapped */ 923 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1)) 924 /* vcpu system registers loaded on physical CPU */ 925 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2)) 926 /* Software step state is Active-pending for external debug */ 927 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3)) 928 /* Software step state is Active pending for guest debug */ 929 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4)) 930 /* PMUSERENR for the guest EL0 is on physical CPU */ 931 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5)) 932 /* WFI instruction trapped */ 933 #define IN_WFI __vcpu_single_flag(sflags, BIT(6)) 934 935 936 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 937 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 938 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 939 940 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 941 942 #define vcpu_sve_zcr_elx(vcpu) \ 943 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) 944 945 #define vcpu_sve_state_size(vcpu) ({ \ 946 size_t __size_ret; \ 947 unsigned int __vcpu_vq; \ 948 \ 949 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 950 __size_ret = 0; \ 951 } else { \ 952 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 953 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 954 } \ 955 \ 956 __size_ret; \ 957 }) 958 959 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 960 KVM_GUESTDBG_USE_SW_BP | \ 961 KVM_GUESTDBG_USE_HW | \ 962 KVM_GUESTDBG_SINGLESTEP) 963 964 #define kvm_has_sve(kvm) (system_supports_sve() && \ 965 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags)) 966 967 #ifdef __KVM_NVHE_HYPERVISOR__ 968 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm)) 969 #else 970 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) 971 #endif 972 973 #ifdef CONFIG_ARM64_PTR_AUTH 974 #define vcpu_has_ptrauth(vcpu) \ 975 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 976 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 977 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \ 978 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC))) 979 #else 980 #define vcpu_has_ptrauth(vcpu) false 981 #endif 982 983 #define vcpu_on_unsupported_cpu(vcpu) \ 984 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 985 986 #define vcpu_set_on_unsupported_cpu(vcpu) \ 987 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 988 989 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 990 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 991 992 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 993 994 /* 995 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 996 * memory backed version of a register, and not the one most recently 997 * accessed by a running VCPU. For example, for userspace access or 998 * for system registers that are never context switched, but only 999 * emulated. 1000 * 1001 * Don't bother with VNCR-based accesses in the nVHE code, it has no 1002 * business dealing with NV. 1003 */ 1004 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r) 1005 { 1006 #if !defined (__KVM_NVHE_HYPERVISOR__) 1007 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) && 1008 r >= __VNCR_START__ && ctxt->vncr_array)) 1009 return &ctxt->vncr_array[r - __VNCR_START__]; 1010 #endif 1011 return (u64 *)&ctxt->sys_regs[r]; 1012 } 1013 1014 #define __ctxt_sys_reg(c,r) \ 1015 ({ \ 1016 BUILD_BUG_ON(__builtin_constant_p(r) && \ 1017 (r) >= NR_SYS_REGS); \ 1018 ___ctxt_sys_reg(c, r); \ 1019 }) 1020 1021 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 1022 1023 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64); 1024 #define __vcpu_sys_reg(v,r) \ 1025 (*({ \ 1026 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \ 1027 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \ 1028 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \ 1029 *__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\ 1030 __r; \ 1031 })) 1032 1033 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 1034 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 1035 1036 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 1037 { 1038 /* 1039 * *** VHE ONLY *** 1040 * 1041 * System registers listed in the switch are not saved on every 1042 * exit from the guest but are only saved on vcpu_put. 1043 * 1044 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1045 * should never be listed below, because the guest cannot modify its 1046 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 1047 * thread when emulating cross-VCPU communication. 1048 */ 1049 if (!has_vhe()) 1050 return false; 1051 1052 switch (reg) { 1053 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 1054 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 1055 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 1056 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 1057 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 1058 case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break; 1059 case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break; 1060 case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break; 1061 case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break; 1062 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 1063 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 1064 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 1065 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 1066 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 1067 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 1068 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 1069 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 1070 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 1071 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 1072 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 1073 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 1074 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 1075 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break; 1076 case PAR_EL1: *val = read_sysreg_par(); break; 1077 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 1078 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 1079 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 1080 case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break; 1081 default: return false; 1082 } 1083 1084 return true; 1085 } 1086 1087 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 1088 { 1089 /* 1090 * *** VHE ONLY *** 1091 * 1092 * System registers listed in the switch are not restored on every 1093 * entry to the guest but are only restored on vcpu_load. 1094 * 1095 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 1096 * should never be listed below, because the MPIDR should only be set 1097 * once, before running the VCPU, and never changed later. 1098 */ 1099 if (!has_vhe()) 1100 return false; 1101 1102 switch (reg) { 1103 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 1104 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 1105 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 1106 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 1107 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 1108 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; 1109 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; 1110 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; 1111 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; 1112 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 1113 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 1114 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 1115 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 1116 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 1117 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 1118 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 1119 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 1120 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 1121 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 1122 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 1123 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 1124 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 1125 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; 1126 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 1127 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 1128 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 1129 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 1130 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; 1131 default: return false; 1132 } 1133 1134 return true; 1135 } 1136 1137 struct kvm_vm_stat { 1138 struct kvm_vm_stat_generic generic; 1139 }; 1140 1141 struct kvm_vcpu_stat { 1142 struct kvm_vcpu_stat_generic generic; 1143 u64 hvc_exit_stat; 1144 u64 wfe_exit_stat; 1145 u64 wfi_exit_stat; 1146 u64 mmio_exit_user; 1147 u64 mmio_exit_kernel; 1148 u64 signal_exits; 1149 u64 exits; 1150 }; 1151 1152 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 1153 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 1154 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1155 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 1156 1157 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 1158 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 1159 1160 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 1161 struct kvm_vcpu_events *events); 1162 1163 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 1164 struct kvm_vcpu_events *events); 1165 1166 void kvm_arm_halt_guest(struct kvm *kvm); 1167 void kvm_arm_resume_guest(struct kvm *kvm); 1168 1169 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid)) 1170 1171 #ifndef __KVM_NVHE_HYPERVISOR__ 1172 #define kvm_call_hyp_nvhe(f, ...) \ 1173 ({ \ 1174 struct arm_smccc_res res; \ 1175 \ 1176 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 1177 ##__VA_ARGS__, &res); \ 1178 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 1179 \ 1180 res.a1; \ 1181 }) 1182 1183 /* 1184 * The couple of isb() below are there to guarantee the same behaviour 1185 * on VHE as on !VHE, where the eret to EL1 acts as a context 1186 * synchronization event. 1187 */ 1188 #define kvm_call_hyp(f, ...) \ 1189 do { \ 1190 if (has_vhe()) { \ 1191 f(__VA_ARGS__); \ 1192 isb(); \ 1193 } else { \ 1194 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1195 } \ 1196 } while(0) 1197 1198 #define kvm_call_hyp_ret(f, ...) \ 1199 ({ \ 1200 typeof(f(__VA_ARGS__)) ret; \ 1201 \ 1202 if (has_vhe()) { \ 1203 ret = f(__VA_ARGS__); \ 1204 isb(); \ 1205 } else { \ 1206 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 1207 } \ 1208 \ 1209 ret; \ 1210 }) 1211 #else /* __KVM_NVHE_HYPERVISOR__ */ 1212 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 1213 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 1214 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 1215 #endif /* __KVM_NVHE_HYPERVISOR__ */ 1216 1217 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 1218 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 1219 1220 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 1221 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 1222 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 1223 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 1224 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 1225 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 1226 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 1227 1228 void kvm_sys_regs_create_debugfs(struct kvm *kvm); 1229 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 1230 1231 int __init kvm_sys_reg_table_init(void); 1232 struct sys_reg_desc; 1233 int __init populate_sysreg_config(const struct sys_reg_desc *sr, 1234 unsigned int idx); 1235 int __init populate_nv_trap_config(void); 1236 1237 bool lock_all_vcpus(struct kvm *kvm); 1238 void unlock_all_vcpus(struct kvm *kvm); 1239 1240 void kvm_calculate_traps(struct kvm_vcpu *vcpu); 1241 1242 /* MMIO helpers */ 1243 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 1244 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1245 1246 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1247 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1248 1249 /* 1250 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1251 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1252 * loaded is considered to be "in guest". 1253 */ 1254 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1255 { 1256 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1257 } 1258 1259 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1260 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1261 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1262 1263 bool kvm_arm_pvtime_supported(void); 1264 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1265 struct kvm_device_attr *attr); 1266 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1267 struct kvm_device_attr *attr); 1268 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1269 struct kvm_device_attr *attr); 1270 1271 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1272 int __init kvm_arm_vmid_alloc_init(void); 1273 void __init kvm_arm_vmid_alloc_free(void); 1274 bool kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1275 void kvm_arm_vmid_clear_active(void); 1276 1277 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1278 { 1279 vcpu_arch->steal.base = INVALID_GPA; 1280 } 1281 1282 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1283 { 1284 return (vcpu_arch->steal.base != INVALID_GPA); 1285 } 1286 1287 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1288 1289 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1290 1291 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1292 1293 /* 1294 * How we access per-CPU host data depends on the where we access it from, 1295 * and the mode we're in: 1296 * 1297 * - VHE and nVHE hypervisor bits use their locally defined instance 1298 * 1299 * - the rest of the kernel use either the VHE or nVHE one, depending on 1300 * the mode we're running in. 1301 * 1302 * Unless we're in protected mode, fully deprivileged, and the nVHE 1303 * per-CPU stuff is exclusively accessible to the protected EL2 code. 1304 * In this case, the EL1 code uses the *VHE* data as its private state 1305 * (which makes sense in a way as there shouldn't be any shared state 1306 * between the host and the hypervisor). 1307 * 1308 * Yes, this is all totally trivial. Shoot me now. 1309 */ 1310 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__) 1311 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f) 1312 #else 1313 #define host_data_ptr(f) \ 1314 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \ 1315 &this_cpu_ptr(&kvm_host_data)->f : \ 1316 &this_cpu_ptr_hyp_sym(kvm_host_data)->f) 1317 #endif 1318 1319 #define host_data_test_flag(flag) \ 1320 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))) 1321 #define host_data_set_flag(flag) \ 1322 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1323 #define host_data_clear_flag(flag) \ 1324 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)) 1325 1326 /* Check whether the FP regs are owned by the guest */ 1327 static inline bool guest_owns_fp_regs(void) 1328 { 1329 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED; 1330 } 1331 1332 /* Check whether the FP regs are owned by the host */ 1333 static inline bool host_owns_fp_regs(void) 1334 { 1335 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED; 1336 } 1337 1338 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1339 { 1340 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1341 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1342 } 1343 1344 static inline bool kvm_system_needs_idmapped_vectors(void) 1345 { 1346 return cpus_have_final_cap(ARM64_SPECTRE_V3A); 1347 } 1348 1349 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1350 1351 void kvm_init_host_debug_data(void); 1352 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu); 1353 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu); 1354 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu); 1355 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val); 1356 1357 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1358 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1359 1360 #define kvm_debug_regs_in_use(vcpu) \ 1361 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE) 1362 #define kvm_host_owns_debug_regs(vcpu) \ 1363 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED) 1364 #define kvm_guest_owns_debug_regs(vcpu) \ 1365 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED) 1366 1367 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1368 struct kvm_device_attr *attr); 1369 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1370 struct kvm_device_attr *attr); 1371 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1372 struct kvm_device_attr *attr); 1373 1374 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1375 struct kvm_arm_copy_mte_tags *copy_tags); 1376 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1377 struct kvm_arm_counter_offset *offset); 1378 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, 1379 struct reg_mask_range *range); 1380 1381 /* Guest/host FPSIMD coordination helpers */ 1382 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1383 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1384 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1385 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1386 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1387 1388 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1389 { 1390 return (!has_vhe() && attr->exclude_host); 1391 } 1392 1393 #ifdef CONFIG_KVM 1394 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); 1395 void kvm_clr_pmu_events(u64 clr); 1396 bool kvm_set_pmuserenr(u64 val); 1397 void kvm_enable_trbe(void); 1398 void kvm_disable_trbe(void); 1399 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); 1400 #else 1401 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} 1402 static inline void kvm_clr_pmu_events(u64 clr) {} 1403 static inline bool kvm_set_pmuserenr(u64 val) 1404 { 1405 return false; 1406 } 1407 static inline void kvm_enable_trbe(void) {} 1408 static inline void kvm_disable_trbe(void) {} 1409 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} 1410 #endif 1411 1412 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); 1413 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu); 1414 1415 int __init kvm_set_ipa_limit(void); 1416 u32 kvm_get_pa_bits(struct kvm *kvm); 1417 1418 #define __KVM_HAVE_ARCH_VM_ALLOC 1419 struct kvm *kvm_arch_alloc_vm(void); 1420 1421 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS 1422 1423 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE 1424 1425 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled) 1426 1427 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) 1428 1429 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1430 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1431 1432 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1433 1434 #define kvm_has_mte(kvm) \ 1435 (system_supports_mte() && \ 1436 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1437 1438 #define kvm_supports_32bit_el0() \ 1439 (system_supports_32bit_el0() && \ 1440 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1441 1442 #define kvm_vm_has_ran_once(kvm) \ 1443 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1444 1445 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature) 1446 { 1447 return test_bit(feature, ka->vcpu_features); 1448 } 1449 1450 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f)) 1451 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f)) 1452 1453 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED) 1454 1455 int kvm_trng_call(struct kvm_vcpu *vcpu); 1456 #ifdef CONFIG_KVM 1457 extern phys_addr_t hyp_mem_base; 1458 extern phys_addr_t hyp_mem_size; 1459 void __init kvm_hyp_reserve(void); 1460 #else 1461 static inline void kvm_hyp_reserve(void) { } 1462 #endif 1463 1464 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1465 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1466 1467 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg) 1468 { 1469 switch (reg) { 1470 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7): 1471 return &ka->id_regs[IDREG_IDX(reg)]; 1472 case SYS_CTR_EL0: 1473 return &ka->ctr_el0; 1474 default: 1475 WARN_ON_ONCE(1); 1476 return NULL; 1477 } 1478 } 1479 1480 #define kvm_read_vm_id_reg(kvm, reg) \ 1481 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; }) 1482 1483 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 1484 1485 #define __expand_field_sign_unsigned(id, fld, val) \ 1486 ((u64)SYS_FIELD_VALUE(id, fld, val)) 1487 1488 #define __expand_field_sign_signed(id, fld, val) \ 1489 ({ \ 1490 u64 __val = SYS_FIELD_VALUE(id, fld, val); \ 1491 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1492 }) 1493 1494 #define get_idreg_field_unsigned(kvm, id, fld) \ 1495 ({ \ 1496 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \ 1497 FIELD_GET(id##_##fld##_MASK, __val); \ 1498 }) 1499 1500 #define get_idreg_field_signed(kvm, id, fld) \ 1501 ({ \ 1502 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \ 1503 sign_extend64(__val, id##_##fld##_WIDTH - 1); \ 1504 }) 1505 1506 #define get_idreg_field_enum(kvm, id, fld) \ 1507 get_idreg_field_unsigned(kvm, id, fld) 1508 1509 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \ 1510 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit)) 1511 1512 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \ 1513 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit)) 1514 1515 #define kvm_cmp_feat(kvm, id, fld, op, limit) \ 1516 (id##_##fld##_SIGNED ? \ 1517 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \ 1518 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)) 1519 1520 #define kvm_has_feat(kvm, id, fld, limit) \ 1521 kvm_cmp_feat(kvm, id, fld, >=, limit) 1522 1523 #define kvm_has_feat_enum(kvm, id, fld, val) \ 1524 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val) 1525 1526 #define kvm_has_feat_range(kvm, id, fld, min, max) \ 1527 (kvm_cmp_feat(kvm, id, fld, >=, min) && \ 1528 kvm_cmp_feat(kvm, id, fld, <=, max)) 1529 1530 /* Check for a given level of PAuth support */ 1531 #define kvm_has_pauth(k, l) \ 1532 ({ \ 1533 bool pa, pi, pa3; \ 1534 \ 1535 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \ 1536 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \ 1537 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \ 1538 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \ 1539 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \ 1540 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \ 1541 \ 1542 (pa + pi + pa3) == 1; \ 1543 }) 1544 1545 #define kvm_has_fpmr(k) \ 1546 (system_supports_fpmr() && \ 1547 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) 1548 1549 #define kvm_has_tcr2(k) \ 1550 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP)) 1551 1552 #define kvm_has_s1pie(k) \ 1553 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP)) 1554 1555 #define kvm_has_s1poe(k) \ 1556 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP)) 1557 1558 #endif /* __ARM64_KVM_HOST_H__ */ 1559