134d7b841SSiddharth Vadapalli// SPDX-License-Identifier: GPL-2.0-only OR MIT 234d7b841SSiddharth Vadapalli/** 334d7b841SSiddharth Vadapalli * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the 434d7b841SSiddharth Vadapalli * AM642 EVM. 534d7b841SSiddharth Vadapalli * 634d7b841SSiddharth Vadapalli * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM 734d7b841SSiddharth Vadapalli * 834d7b841SSiddharth Vadapalli * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 934d7b841SSiddharth Vadapalli */ 1034d7b841SSiddharth Vadapalli 1134d7b841SSiddharth Vadapalli/dts-v1/; 1234d7b841SSiddharth Vadapalli/plugin/; 1334d7b841SSiddharth Vadapalli 1434d7b841SSiddharth Vadapalli#include <dt-bindings/interrupt-controller/arm-gic.h> 1534d7b841SSiddharth Vadapalli#include <dt-bindings/soc/ti,sci_pm_domain.h> 1634d7b841SSiddharth Vadapalli 1734d7b841SSiddharth Vadapalli#include "k3-pinctrl.h" 1834d7b841SSiddharth Vadapalli 1934d7b841SSiddharth Vadapalli/* 2034d7b841SSiddharth Vadapalli * Since Root Complex and Endpoint modes are mutually exclusive 2134d7b841SSiddharth Vadapalli * disable Root Complex mode. 2234d7b841SSiddharth Vadapalli */ 2334d7b841SSiddharth Vadapalli&pcie0_rc { 2434d7b841SSiddharth Vadapalli status = "disabled"; 2534d7b841SSiddharth Vadapalli}; 2634d7b841SSiddharth Vadapalli 2734d7b841SSiddharth Vadapalli&cbass_main { 2834d7b841SSiddharth Vadapalli #address-cells = <2>; 2934d7b841SSiddharth Vadapalli #size-cells = <2>; 3034d7b841SSiddharth Vadapalli interrupt-parent = <&gic500>; 3134d7b841SSiddharth Vadapalli 3234d7b841SSiddharth Vadapalli pcie0_ep: pcie-ep@f102000 { 3334d7b841SSiddharth Vadapalli compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 3434d7b841SSiddharth Vadapalli reg = <0x00 0x0f102000 0x00 0x1000>, 3534d7b841SSiddharth Vadapalli <0x00 0x0f100000 0x00 0x400>, 3634d7b841SSiddharth Vadapalli <0x00 0x0d000000 0x00 0x00800000>, 3734d7b841SSiddharth Vadapalli <0x00 0x68000000 0x00 0x08000000>; 3834d7b841SSiddharth Vadapalli reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 3934d7b841SSiddharth Vadapalli interrupt-names = "link_state"; 4034d7b841SSiddharth Vadapalli interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 4134d7b841SSiddharth Vadapalli max-link-speed = <2>; 4234d7b841SSiddharth Vadapalli num-lanes = <1>; 4334d7b841SSiddharth Vadapalli power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 4434d7b841SSiddharth Vadapalli clocks = <&k3_clks 114 0>; 4534d7b841SSiddharth Vadapalli clock-names = "fck"; 4634d7b841SSiddharth Vadapalli max-functions = /bits/ 8 <1>; 4734d7b841SSiddharth Vadapalli phys = <&serdes0_pcie_link>; 4834d7b841SSiddharth Vadapalli phy-names = "pcie-phy"; 49*4e7ad3b4SAndrew Davis bootph-all; 5034d7b841SSiddharth Vadapalli ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 5134d7b841SSiddharth Vadapalli }; 52}; 53