1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device tree definitions for the Turing RK1 SoM. 4 * 5 * Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com> 6 * 7 * Based on RK3588-EVB1 devicetree 8 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 9 */ 10 11/dts-v1/; 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/pinctrl/rockchip.h> 14#include "rk3588.dtsi" 15 16/ { 17 compatible = "turing,rk1", "rockchip,rk3588"; 18 19 aliases { 20 ethernet0 = &gmac1; 21 mmc0 = &sdhci; 22 }; 23 24 fan: pwm-fan { 25 compatible = "pwm-fan"; 26 cooling-levels = <0 25 95 145 195 255>; 27 fan-supply = <&vcc5v0_sys>; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pwm0m2_pins &fan_int>; 30 interrupt-parent = <&gpio0>; 31 interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>; 32 pwms = <&pwm0 0 50000 0>; 33 #cooling-cells = <2>; 34 }; 35 36 vcc3v3_pcie30: regulator-vcc3v3-pcie30 { 37 compatible = "regulator-fixed"; 38 regulator-name = "vcc3v3_pcie30"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 enable-active-high; 42 gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&vcc3v3_pcie30_en>; 45 startup-delay-us = <5000>; 46 }; 47 48 vcc5v0_sys: regulator-vcc5v0-sys { 49 compatible = "regulator-fixed"; 50 regulator-name = "vcc5v0_sys"; 51 regulator-always-on; 52 regulator-boot-on; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 }; 56 57 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 58 compatible = "regulator-fixed"; 59 regulator-name = "vcc_1v1_nldo_s3"; 60 regulator-always-on; 61 regulator-boot-on; 62 regulator-min-microvolt = <1100000>; 63 regulator-max-microvolt = <1100000>; 64 vin-supply = <&vcc5v0_sys>; 65 }; 66}; 67 68&combphy2_psu { 69 status = "okay"; 70}; 71 72&cpu_b0 { 73 cpu-supply = <&vdd_cpu_big0_s0>; 74}; 75 76&cpu_b1 { 77 cpu-supply = <&vdd_cpu_big0_s0>; 78}; 79 80&cpu_b2 { 81 cpu-supply = <&vdd_cpu_big1_s0>; 82}; 83 84&cpu_b3 { 85 cpu-supply = <&vdd_cpu_big1_s0>; 86}; 87 88&cpu_l0 { 89 cpu-supply = <&vdd_cpu_lit_s0>; 90}; 91 92&cpu_l1 { 93 cpu-supply = <&vdd_cpu_lit_s0>; 94}; 95 96&cpu_l2 { 97 cpu-supply = <&vdd_cpu_lit_s0>; 98}; 99 100&cpu_l3 { 101 cpu-supply = <&vdd_cpu_lit_s0>; 102}; 103 104&gmac1 { 105 clock_in_out = "output"; 106 phy-handle = <&rgmii_phy>; 107 phy-mode = "rgmii-rxid"; 108 pinctrl-0 = <&gmac1_miim 109 &gmac1_tx_bus2 110 &gmac1_rx_bus2 111 &gmac1_rgmii_clk 112 &gmac1_rgmii_bus>; 113 pinctrl-names = "default"; 114 rx_delay = <0x00>; 115 tx_delay = <0x43>; 116 status = "okay"; 117}; 118 119&gpu { 120 mali-supply = <&vdd_gpu_s0>; 121 status = "okay"; 122}; 123 124&i2c0 { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&i2c0m2_xfer>; 127 status = "okay"; 128 129 vdd_cpu_big0_s0: regulator@42 { 130 compatible = "rockchip,rk8602"; 131 reg = <0x42>; 132 fcs,suspend-voltage-selector = <1>; 133 regulator-name = "vdd_cpu_big0_s0"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <550000>; 137 regulator-max-microvolt = <1050000>; 138 regulator-ramp-delay = <2300>; 139 vin-supply = <&vcc5v0_sys>; 140 141 regulator-state-mem { 142 regulator-off-in-suspend; 143 }; 144 }; 145 146 vdd_cpu_big1_s0: regulator@43 { 147 compatible = "rockchip,rk8603", "rockchip,rk8602"; 148 reg = <0x43>; 149 fcs,suspend-voltage-selector = <1>; 150 regulator-name = "vdd_cpu_big1_s0"; 151 regulator-always-on; 152 regulator-boot-on; 153 regulator-min-microvolt = <550000>; 154 regulator-max-microvolt = <1050000>; 155 regulator-ramp-delay = <2300>; 156 vin-supply = <&vcc5v0_sys>; 157 158 regulator-state-mem { 159 regulator-off-in-suspend; 160 }; 161 }; 162}; 163 164&i2c1 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&i2c1m2_xfer>; 167 status = "okay"; 168 169 vdd_npu_s0: regulator@42 { 170 compatible = "rockchip,rk8602"; 171 reg = <0x42>; 172 fcs,suspend-voltage-selector = <1>; 173 regulator-name = "vdd_npu_s0"; 174 regulator-always-on; 175 regulator-boot-on; 176 regulator-min-microvolt = <550000>; 177 regulator-max-microvolt = <950000>; 178 regulator-ramp-delay = <2300>; 179 vin-supply = <&vcc5v0_sys>; 180 181 regulator-state-mem { 182 regulator-off-in-suspend; 183 }; 184 }; 185}; 186 187&i2c6 { 188 status = "okay"; 189 190 hym8563: rtc@51 { 191 compatible = "haoyu,hym8563"; 192 reg = <0x51>; 193 #clock-cells = <0>; 194 clock-output-names = "hym8563"; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&hym8563_int>; 197 interrupt-parent = <&gpio0>; 198 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 199 wakeup-source; 200 }; 201}; 202 203&mdio1 { 204 rgmii_phy: ethernet-phy@1 { 205 /* RTL8211F */ 206 compatible = "ethernet-phy-id001c.c916"; 207 reg = <0x1>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&rtl8211f_rst>; 210 reset-assert-us = <15000>; 211 reset-deassert-us = <50000>; 212 reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 213 }; 214}; 215 216&package_thermal { 217 trips { 218 package_active1: trip-active1 { 219 temperature = <45000>; 220 hysteresis = <5000>; 221 type = "active"; 222 }; 223 package_active2: trip-active2 { 224 temperature = <50000>; 225 hysteresis = <5000>; 226 type = "active"; 227 }; 228 package_active3: trip-active3 { 229 temperature = <60000>; 230 hysteresis = <5000>; 231 type = "active"; 232 }; 233 package_active4: trip-active4 { 234 temperature = <70000>; 235 hysteresis = <5000>; 236 type = "active"; 237 }; 238 package_active5: trip-active5 { 239 temperature = <80000>; 240 hysteresis = <5000>; 241 type = "active"; 242 }; 243 }; 244 245 cooling-maps { 246 map1 { 247 trip = <&package_active1>; 248 cooling-device = <&fan 1 1>; 249 }; 250 map2 { 251 trip = <&package_active2>; 252 cooling-device = <&fan 2 2>; 253 }; 254 map3 { 255 trip = <&package_active3>; 256 cooling-device = <&fan 3 3>; 257 }; 258 map4 { 259 trip = <&package_active4>; 260 cooling-device = <&fan 4 4>; 261 }; 262 map5 { 263 trip = <&package_active5>; 264 cooling-device = <&fan 5 5>; 265 }; 266 }; 267}; 268 269&pcie2x1l1 { 270 linux,pci-domain = <1>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pcie2_reset>, <&pcie30x1m1_0_clkreqn>, <&pcie30x1m1_0_waken>; 273 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 274 status = "okay"; 275}; 276 277&pcie30phy { 278 status = "okay"; 279}; 280 281&pcie3x4 { 282 linux,pci-domain = <0>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>, <&pcie30x4m1_waken>; 285 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 286 vpcie3v3-supply = <&vcc3v3_pcie30>; 287 status = "okay"; 288}; 289 290&pd_gpu { 291 domain-supply = <&vdd_gpu_s0>; 292}; 293 294&pinctrl { 295 fan { 296 fan_int: fan-int { 297 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 298 }; 299 }; 300 301 hym8563 { 302 hym8563_int: hym8563-int { 303 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 304 }; 305 }; 306 307 pcie2 { 308 pcie2_reset: pcie2-reset { 309 rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 310 }; 311 }; 312 313 pcie3 { 314 pcie3_reset: pcie3-reset { 315 rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 316 }; 317 318 vcc3v3_pcie30_en: pcie3-reg { 319 rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 320 }; 321 }; 322 323 rtl8211f { 324 rtl8211f_rst: rtl8211f-rst { 325 rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 326 }; 327 }; 328}; 329 330&pwm0 { 331 status = "okay"; 332}; 333 334&sdhci { 335 bus-width = <8>; 336 no-sdio; 337 no-sd; 338 non-removable; 339 mmc-hs400-1_8v; 340 mmc-hs400-enhanced-strobe; 341 status = "okay"; 342}; 343 344&spi2 { 345 status = "okay"; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 348 num-cs = <1>; 349 350 pmic@0 { 351 compatible = "rockchip,rk806"; 352 spi-max-frequency = <1000000>; 353 reg = <0x0>; 354 355 interrupt-parent = <&gpio0>; 356 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 357 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 360 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 361 system-power-controller; 362 363 vcc1-supply = <&vcc5v0_sys>; 364 vcc2-supply = <&vcc5v0_sys>; 365 vcc3-supply = <&vcc5v0_sys>; 366 vcc4-supply = <&vcc5v0_sys>; 367 vcc5-supply = <&vcc5v0_sys>; 368 vcc6-supply = <&vcc5v0_sys>; 369 vcc7-supply = <&vcc5v0_sys>; 370 vcc8-supply = <&vcc5v0_sys>; 371 vcc9-supply = <&vcc5v0_sys>; 372 vcc10-supply = <&vcc5v0_sys>; 373 vcc11-supply = <&vcc_2v0_pldo_s3>; 374 vcc12-supply = <&vcc5v0_sys>; 375 vcc13-supply = <&vcc_1v1_nldo_s3>; 376 vcc14-supply = <&vcc_1v1_nldo_s3>; 377 vcca-supply = <&vcc5v0_sys>; 378 379 gpio-controller; 380 #gpio-cells = <2>; 381 382 rk806_dvs1_null: dvs1-null-pins { 383 pins = "gpio_pwrctrl1"; 384 function = "pin_fun0"; 385 }; 386 387 rk806_dvs2_null: dvs2-null-pins { 388 pins = "gpio_pwrctrl2"; 389 function = "pin_fun0"; 390 }; 391 392 rk806_dvs3_null: dvs3-null-pins { 393 pins = "gpio_pwrctrl3"; 394 function = "pin_fun0"; 395 }; 396 397 regulators { 398 vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { 399 /* 400 * RK3588's GPU power domain cannot be enabled 401 * without this regulator active, but it 402 * doesn't have to be on when the GPU PD is 403 * disabled. Because the PD binding does not 404 * currently allow us to express this 405 * relationship, we have no choice but to do 406 * this instead: 407 */ 408 regulator-always-on; 409 410 regulator-boot-on; 411 regulator-min-microvolt = <550000>; 412 regulator-max-microvolt = <950000>; 413 regulator-ramp-delay = <12500>; 414 regulator-name = "vdd_gpu_s0"; 415 regulator-enable-ramp-delay = <400>; 416 417 regulator-state-mem { 418 regulator-off-in-suspend; 419 }; 420 }; 421 422 vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { 423 regulator-always-on; 424 regulator-boot-on; 425 regulator-min-microvolt = <550000>; 426 regulator-max-microvolt = <950000>; 427 regulator-ramp-delay = <12500>; 428 regulator-name = "vdd_cpu_lit_s0"; 429 430 regulator-state-mem { 431 regulator-off-in-suspend; 432 }; 433 }; 434 435 vdd_log_s0: dcdc-reg3 { 436 regulator-always-on; 437 regulator-boot-on; 438 regulator-min-microvolt = <675000>; 439 regulator-max-microvolt = <750000>; 440 regulator-ramp-delay = <12500>; 441 regulator-name = "vdd_log_s0"; 442 443 regulator-state-mem { 444 regulator-off-in-suspend; 445 regulator-suspend-microvolt = <750000>; 446 }; 447 }; 448 449 vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { 450 regulator-always-on; 451 regulator-boot-on; 452 regulator-min-microvolt = <550000>; 453 regulator-max-microvolt = <950000>; 454 regulator-ramp-delay = <12500>; 455 regulator-name = "vdd_vdenc_s0"; 456 457 regulator-state-mem { 458 regulator-off-in-suspend; 459 }; 460 }; 461 462 vdd_ddr_s0: dcdc-reg5 { 463 regulator-always-on; 464 regulator-boot-on; 465 regulator-min-microvolt = <675000>; 466 regulator-max-microvolt = <900000>; 467 regulator-ramp-delay = <12500>; 468 regulator-name = "vdd_ddr_s0"; 469 470 regulator-state-mem { 471 regulator-off-in-suspend; 472 regulator-suspend-microvolt = <850000>; 473 }; 474 }; 475 476 vdd2_ddr_s3: dcdc-reg6 { 477 regulator-always-on; 478 regulator-boot-on; 479 regulator-name = "vdd2_ddr_s3"; 480 481 regulator-state-mem { 482 regulator-on-in-suspend; 483 }; 484 }; 485 486 vcc_2v0_pldo_s3: dcdc-reg7 { 487 regulator-always-on; 488 regulator-boot-on; 489 regulator-min-microvolt = <2000000>; 490 regulator-max-microvolt = <2000000>; 491 regulator-ramp-delay = <12500>; 492 regulator-name = "vdd_2v0_pldo_s3"; 493 494 regulator-state-mem { 495 regulator-on-in-suspend; 496 regulator-suspend-microvolt = <2000000>; 497 }; 498 }; 499 500 vcc_3v3_s3: dcdc-reg8 { 501 regulator-always-on; 502 regulator-boot-on; 503 regulator-min-microvolt = <3300000>; 504 regulator-max-microvolt = <3300000>; 505 regulator-name = "vcc_3v3_s3"; 506 507 regulator-state-mem { 508 regulator-on-in-suspend; 509 regulator-suspend-microvolt = <3300000>; 510 }; 511 }; 512 513 vddq_ddr_s0: dcdc-reg9 { 514 regulator-always-on; 515 regulator-boot-on; 516 regulator-name = "vddq_ddr_s0"; 517 518 regulator-state-mem { 519 regulator-off-in-suspend; 520 }; 521 }; 522 523 vcc_1v8_s3: dcdc-reg10 { 524 regulator-always-on; 525 regulator-boot-on; 526 regulator-min-microvolt = <1800000>; 527 regulator-max-microvolt = <1800000>; 528 regulator-name = "vcc_1v8_s3"; 529 530 regulator-state-mem { 531 regulator-on-in-suspend; 532 regulator-suspend-microvolt = <1800000>; 533 }; 534 }; 535 536 avcc_1v8_s0: pldo-reg1 { 537 regulator-always-on; 538 regulator-boot-on; 539 regulator-min-microvolt = <1800000>; 540 regulator-max-microvolt = <1800000>; 541 regulator-name = "avcc_1v8_s0"; 542 543 regulator-state-mem { 544 regulator-off-in-suspend; 545 }; 546 }; 547 548 vcc_1v8_s0: pldo-reg2 { 549 regulator-always-on; 550 regulator-boot-on; 551 regulator-min-microvolt = <1800000>; 552 regulator-max-microvolt = <1800000>; 553 regulator-name = "vcc_1v8_s0"; 554 555 regulator-state-mem { 556 regulator-off-in-suspend; 557 regulator-suspend-microvolt = <1800000>; 558 }; 559 }; 560 561 avdd_1v2_s0: pldo-reg3 { 562 regulator-always-on; 563 regulator-boot-on; 564 regulator-min-microvolt = <1200000>; 565 regulator-max-microvolt = <1200000>; 566 regulator-name = "avdd_1v2_s0"; 567 568 regulator-state-mem { 569 regulator-off-in-suspend; 570 }; 571 }; 572 573 vcc_3v3_s0: pldo-reg4 { 574 regulator-always-on; 575 regulator-boot-on; 576 regulator-min-microvolt = <3300000>; 577 regulator-max-microvolt = <3300000>; 578 regulator-ramp-delay = <12500>; 579 regulator-name = "vcc_3v3_s0"; 580 581 regulator-state-mem { 582 regulator-off-in-suspend; 583 }; 584 }; 585 586 vccio_sd_s0: pldo-reg5 { 587 regulator-always-on; 588 regulator-boot-on; 589 regulator-min-microvolt = <1800000>; 590 regulator-max-microvolt = <3300000>; 591 regulator-ramp-delay = <12500>; 592 regulator-name = "vccio_sd_s0"; 593 594 regulator-state-mem { 595 regulator-off-in-suspend; 596 }; 597 }; 598 599 pldo6_s3: pldo-reg6 { 600 regulator-always-on; 601 regulator-boot-on; 602 regulator-min-microvolt = <1800000>; 603 regulator-max-microvolt = <1800000>; 604 regulator-name = "pldo6_s3"; 605 606 regulator-state-mem { 607 regulator-on-in-suspend; 608 regulator-suspend-microvolt = <1800000>; 609 }; 610 }; 611 612 vdd_0v75_s3: nldo-reg1 { 613 regulator-always-on; 614 regulator-boot-on; 615 regulator-min-microvolt = <750000>; 616 regulator-max-microvolt = <750000>; 617 regulator-name = "vdd_0v75_s3"; 618 619 regulator-state-mem { 620 regulator-on-in-suspend; 621 regulator-suspend-microvolt = <750000>; 622 }; 623 }; 624 625 vdd_ddr_pll_s0: nldo-reg2 { 626 regulator-always-on; 627 regulator-boot-on; 628 regulator-min-microvolt = <850000>; 629 regulator-max-microvolt = <850000>; 630 regulator-name = "vdd_ddr_pll_s0"; 631 632 regulator-state-mem { 633 regulator-off-in-suspend; 634 regulator-suspend-microvolt = <850000>; 635 }; 636 }; 637 638 avdd_0v75_s0: nldo-reg3 { 639 regulator-always-on; 640 regulator-boot-on; 641 regulator-min-microvolt = <750000>; 642 regulator-max-microvolt = <750000>; 643 regulator-name = "avdd_0v75_s0"; 644 645 regulator-state-mem { 646 regulator-off-in-suspend; 647 }; 648 }; 649 650 vdd_0v85_s0: nldo-reg4 { 651 regulator-always-on; 652 regulator-boot-on; 653 regulator-min-microvolt = <850000>; 654 regulator-max-microvolt = <850000>; 655 regulator-name = "vdd_0v85_s0"; 656 657 regulator-state-mem { 658 regulator-off-in-suspend; 659 }; 660 }; 661 662 vdd_0v75_s0: nldo-reg5 { 663 regulator-always-on; 664 regulator-boot-on; 665 regulator-min-microvolt = <750000>; 666 regulator-max-microvolt = <750000>; 667 regulator-name = "vdd_0v75_s0"; 668 669 regulator-state-mem { 670 regulator-off-in-suspend; 671 }; 672 }; 673 }; 674 }; 675}; 676 677&tsadc { 678 status = "okay"; 679}; 680 681&uart2 { 682 pinctrl-0 = <&uart2m0_xfer>; 683 status = "okay"; 684}; 685 686&uart9 { 687 pinctrl-0 = <&uart9m0_xfer>; 688 status = "okay"; 689}; 690 691/* USB 0: USB 2.0 only, OTG-capable */ 692&u2phy0 { 693 status = "okay"; 694}; 695 696&u2phy0_otg { 697 status = "okay"; 698}; 699 700&usbdp_phy0 { 701 /* 702 * TODO: On the RK1, USBDP0 drives the DisplayPort pins and is not 703 * involved in this USB2-only bus. The bus controller (below) needs to 704 * know that it doesn't have a USB3 port so it can ignore any 705 * USB3-related signals. This is handled in hardware by updating the 706 * GRFs corresponding to that bus controller. Alas, Linux currently 707 * puts the code to do that in the USBDP driver, so USBDP0 must be 708 * enabled for now. 709 */ 710 rockchip,dp-lane-mux = <0 1 2 3>; /* "No USB lanes" */ 711 status = "okay"; 712}; 713 714&usb_host0_xhci { 715 extcon = <&u2phy0>; 716 maximum-speed = "high-speed"; 717 status = "okay"; 718}; 719 720/* USB 1: USB 3.0, host only */ 721&u2phy1 { 722 status = "okay"; 723}; 724 725&u2phy1_otg { 726 status = "okay"; 727}; 728 729&usbdp_phy1 { 730 status = "okay"; 731}; 732 733&usb_host1_xhci { 734 dr_mode = "host"; 735 extcon = <&u2phy1>; 736 status = "okay"; 737}; 738 739/* USB 2: USB 2.0, host only */ 740&u2phy2 { 741 status = "okay"; 742}; 743 744&u2phy2_host { 745 status = "okay"; 746}; 747 748&usb_host0_ehci { 749 status = "okay"; 750}; 751 752&usb_host0_ohci { 753 status = "okay"; 754}; 755