1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Cherry Embedded Solutions GmbH 4 * 5 * Device Tree Overlay for the Ethernet Switch adapter for the Mezzanine 6 * connector on RK3588 Jaguar 7 * (manual: https://embedded.cherry.de/jaguar-ethernet-switch-user-manual/) 8 * 9 * This adapter has a KSZ9896 Ethernet Switch with 4 1GbE Ethernet connectors, 10 * two user controllable LEDs, and an M12 12-pin connector which exposes the 11 * following signals: 12 * - RS232/RS485 (max 250Kbps/500Kbps, RX pin1, TX pin2) 13 * - two digital inputs (pin4 routed to GPIO3_C5 on SoC, pin5 to GPIO4_B4) 14 * - two digital outputs (pin7 routed to GPIO3_D3 on SoC, pin8 to GPIO3_D1) 15 * - two analog inputs (pin10 to channel1 of ADS1015, pin11 to channel2) 16 * 17 * RK3588 Jaguar can be powered entirely through the adapter via the M8 3-pin 18 * connector (12-24V). 19 */ 20 21/dts-v1/; 22/plugin/; 23 24#include <dt-bindings/clock/rockchip,rk3588-cru.h> 25#include <dt-bindings/gpio/gpio.h> 26#include <dt-bindings/interrupt-controller/irq.h> 27#include <dt-bindings/leds/common.h> 28#include <dt-bindings/pinctrl/rockchip.h> 29 30&{/} { 31 aliases { 32 ethernet1 = "/ethernet@fe1c0000"; 33 }; 34 35 mezzanine-leds { 36 compatible = "gpio-leds"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&led_usr1_pin &led_usr2_pin>; 39 40 led-1 { 41 gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; 42 label = "USR1"; 43 }; 44 45 led-2 { 46 gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; 47 label = "USR2"; 48 }; 49 }; 50}; 51 52&gmac1 { 53 clock_in_out = "output"; 54 phy-mode = "rgmii-id"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&gmac1_rx_bus2 57 &gmac1_tx_bus2 58 &gmac1_rgmii_clk 59 &gmac1_rgmii_bus 60 ð1_pins>; 61 rx_delay = <0x0>; 62 tx_delay = <0x0>; 63 status = "okay"; 64 65 fixed-link { 66 speed = <1000>; 67 full-duplex; 68 }; 69}; 70 71&i2c1 { 72 #address-cells = <1>; 73 /* 74 * ADS1015 can handle high-speed (HS) mode (up to 3.4MHz) on I2C bus, 75 * but SoC can handle only up to 400kHz. 76 */ 77 clock-frequency = <400000>; 78 #size-cells = <0>; 79 status = "okay"; 80 81 adc@48 { 82 compatible = "ti,ads1015"; 83 reg = <0x48>; 84 #address-cells = <1>; 85 interrupt-parent = <&gpio3>; 86 interrupts = <RK_PC7 IRQ_TYPE_EDGE_FALLING>; 87 pinctrl-0 = <&adc_alert>; 88 pinctrl-names = "default"; 89 #io-channel-cells = <1>; 90 #size-cells = <0>; 91 92 channel@1 { 93 reg = <5>; /* Single-ended between AIN1 and GND */ 94 ti,datarate = <0>; 95 ti,gain = <5>; 96 }; 97 98 channel@2 { 99 reg = <6>; /* Single-ended between AIN2 and GND */ 100 ti,datarate = <0>; 101 ti,gain = <5>; 102 }; 103 }; 104 105 switch@5f { 106 compatible = "microchip,ksz9896"; 107 reg = <0x5f>; 108 interrupt-parent = <&gpio3>; 109 interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>; /* ETH_INTRP_N */ 110 pinctrl-0 = <ð_reset_n ð_intrp_n>; 111 pinctrl-names = "default"; 112 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; /* ETH_RESET */ 113 microchip,synclko-disable; /* CLKO_25_125 only routed to TP1 */ 114 115 ethernet-ports { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 lan1: port@0 { 120 reg = <0>; 121 label = "ETH1"; 122 }; 123 124 lan2: port@1 { 125 reg = <1>; 126 label = "ETH2"; 127 }; 128 129 lan3: port@2 { 130 reg = <2>; 131 label = "ETH3"; 132 }; 133 134 lan4: port@3 { 135 reg = <3>; 136 label = "ETH4"; 137 }; 138 139 port@5 { 140 reg = <5>; 141 ethernet = <&gmac1>; 142 label = "CPU"; 143 phy-mode = "rgmii-id"; 144 rx-internal-delay-ps = <2000>; 145 tx-internal-delay-ps = <2000>; 146 147 fixed-link { 148 speed = <1000>; 149 full-duplex; 150 }; 151 }; 152 }; 153 }; 154}; 155 156&pinctrl { 157 adc { 158 adc_alert: adc-alert-irq { 159 rockchip,pins = 160 <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 161 }; 162 }; 163 164 ethernet { 165 eth_intrp_n: eth-intrp-n { 166 rockchip,pins = 167 <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 168 }; 169 170 eth_reset_n: eth-reset-n { 171 rockchip,pins = 172 <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 173 }; 174 }; 175 176 leds { 177 led_usr1_pin: led-usr1-pin { 178 rockchip,pins = 179 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; 180 }; 181 182 led_usr2_pin: led-usr2-pin { 183 rockchip,pins = 184 <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; 185 }; 186 }; 187}; 188 189&uart9 { 190 /* GPIO3_D0/EN_RS485_MODE for switching between RS232 and RS485 */ 191 pinctrl-0 = <&uart9m2_xfer &uart9m2_rtsn>; 192 pinctrl-names = "default"; 193 linux,rs485-enabled-at-boot-time; 194 status = "okay"; 195}; 196