xref: /linux/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi (revision af9feb0b85f92d2972061224839c5fea5ee39f6d) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	clk32k {
15		/omit-if-no-ref/
16		clk32k_out1: clk32k-out1 {
17			rockchip,pins =
18				/* clk32k_out1 */
19				<2 RK_PC5 1 &pcfg_pull_none>;
20		};
21
22	};
23
24	eth0 {
25		/omit-if-no-ref/
26		eth0_pins: eth0-pins {
27			rockchip,pins =
28				/* eth0_refclko_25m */
29				<2 RK_PC3 1 &pcfg_pull_none>;
30		};
31
32	};
33
34	fspi {
35		/omit-if-no-ref/
36		fspim1_pins: fspim1-pins {
37			rockchip,pins =
38				/* fspi_clk_m1 */
39				<2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
40				/* fspi_cs0n_m1 */
41				<2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
42				/* fspi_d0_m1 */
43				<2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
44				/* fspi_d1_m1 */
45				<2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
46				/* fspi_d2_m1 */
47				<2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
48				/* fspi_d3_m1 */
49				<2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
50		};
51
52		/omit-if-no-ref/
53		fspim1_cs1: fspim1-cs1 {
54			rockchip,pins =
55				/* fspi_cs1n_m1 */
56				<2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
57		};
58	};
59
60	gmac0 {
61		/omit-if-no-ref/
62		gmac0_miim: gmac0-miim {
63			rockchip,pins =
64				/* gmac0_mdc */
65				<4 RK_PC4 1 &pcfg_pull_none>,
66				/* gmac0_mdio */
67				<4 RK_PC5 1 &pcfg_pull_none>;
68		};
69
70		/omit-if-no-ref/
71		gmac0_clkinout: gmac0-clkinout {
72			rockchip,pins =
73				/* gmac0_mclkinout */
74				<4 RK_PC3 1 &pcfg_pull_none>;
75		};
76
77		/omit-if-no-ref/
78		gmac0_rx_bus2: gmac0-rx-bus2 {
79			rockchip,pins =
80				/* gmac0_rxd0 */
81				<2 RK_PC1 1 &pcfg_pull_none>,
82				/* gmac0_rxd1 */
83				<2 RK_PC2 1 &pcfg_pull_none>,
84				/* gmac0_rxdv_crs */
85				<4 RK_PC2 1 &pcfg_pull_none>;
86		};
87
88		/omit-if-no-ref/
89		gmac0_tx_bus2: gmac0-tx-bus2 {
90			rockchip,pins =
91				/* gmac0_txd0 */
92				<2 RK_PB6 1 &pcfg_pull_none>,
93				/* gmac0_txd1 */
94				<2 RK_PB7 1 &pcfg_pull_none>,
95				/* gmac0_txen */
96				<2 RK_PC0 1 &pcfg_pull_none>;
97		};
98
99		/omit-if-no-ref/
100		gmac0_rgmii_clk: gmac0-rgmii-clk {
101			rockchip,pins =
102				/* gmac0_rxclk */
103				<2 RK_PB0 1 &pcfg_pull_none>,
104				/* gmac0_txclk */
105				<2 RK_PB3 1 &pcfg_pull_none>;
106		};
107
108		/omit-if-no-ref/
109		gmac0_rgmii_bus: gmac0-rgmii-bus {
110			rockchip,pins =
111				/* gmac0_rxd2 */
112				<2 RK_PA6 1 &pcfg_pull_none>,
113				/* gmac0_rxd3 */
114				<2 RK_PA7 1 &pcfg_pull_none>,
115				/* gmac0_txd2 */
116				<2 RK_PB1 1 &pcfg_pull_none>,
117				/* gmac0_txd3 */
118				<2 RK_PB2 1 &pcfg_pull_none>;
119		};
120
121		/omit-if-no-ref/
122		gmac0_ppsclk: gmac0-ppsclk {
123			rockchip,pins =
124				/* gmac0_ppsclk */
125				<2 RK_PC4 1 &pcfg_pull_none>;
126		};
127
128		/omit-if-no-ref/
129		gmac0_ppstring: gmac0-ppstring {
130			rockchip,pins =
131				/* gmac0_ppstring */
132				<2 RK_PB5 1 &pcfg_pull_none>;
133		};
134
135		/omit-if-no-ref/
136		gmac0_ptp_refclk: gmac0-ptp-refclk {
137			rockchip,pins =
138				/* gmac0_ptp_refclk */
139				<2 RK_PB4 1 &pcfg_pull_none>;
140		};
141
142		/omit-if-no-ref/
143		gmac0_txer: gmac0-txer {
144			rockchip,pins =
145				/* gmac0_txer */
146				<4 RK_PC6 1 &pcfg_pull_none>;
147		};
148
149	};
150
151	hdmi {
152		/omit-if-no-ref/
153		hdmim0_tx1_cec: hdmim0-tx1-cec {
154			rockchip,pins =
155				/* hdmim0_tx1_cec */
156				<2 RK_PC4 4 &pcfg_pull_none>;
157		};
158
159		/omit-if-no-ref/
160		hdmim0_tx1_scl: hdmim0-tx1-scl {
161			rockchip,pins =
162				/* hdmim0_tx1_scl */
163				<2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
164		};
165
166		/omit-if-no-ref/
167		hdmim0_tx1_sda: hdmim0-tx1-sda {
168			rockchip,pins =
169				/* hdmim0_tx1_sda */
170				<2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
171
172		};
173	};
174
175	i2c0 {
176		/omit-if-no-ref/
177		i2c0m1_xfer: i2c0m1-xfer {
178			rockchip,pins =
179				/* i2c0_scl_m1 */
180				<4 RK_PC5 9 &pcfg_pull_none_smt>,
181				/* i2c0_sda_m1 */
182				<4 RK_PC6 9 &pcfg_pull_none_smt>;
183		};
184	};
185
186	i2c2 {
187		/omit-if-no-ref/
188		i2c2m1_xfer: i2c2m1-xfer {
189			rockchip,pins =
190				/* i2c2_scl_m1 */
191				<2 RK_PC1 9 &pcfg_pull_none_smt>,
192				/* i2c2_sda_m1 */
193				<2 RK_PC0 9 &pcfg_pull_none_smt>;
194		};
195	};
196
197	i2c3 {
198		/omit-if-no-ref/
199		i2c3m3_xfer: i2c3m3-xfer {
200			rockchip,pins =
201				/* i2c3_scl_m3 */
202				<2 RK_PB2 9 &pcfg_pull_none_smt>,
203				/* i2c3_sda_m3 */
204				<2 RK_PB3 9 &pcfg_pull_none_smt>;
205		};
206	};
207
208	i2c4 {
209		/omit-if-no-ref/
210		i2c4m1_xfer: i2c4m1-xfer {
211			rockchip,pins =
212				/* i2c4_scl_m1 */
213				<2 RK_PB5 9 &pcfg_pull_none_smt>,
214				/* i2c4_sda_m1 */
215				<2 RK_PB4 9 &pcfg_pull_none_smt>;
216		};
217	};
218
219	i2c5 {
220		/omit-if-no-ref/
221		i2c5m4_xfer: i2c5m4-xfer {
222			rockchip,pins =
223				/* i2c5_scl_m4 */
224				<2 RK_PB6 9 &pcfg_pull_none_smt>,
225				/* i2c5_sda_m4 */
226				<2 RK_PB7 9 &pcfg_pull_none_smt>;
227		};
228	};
229
230	i2c6 {
231		/omit-if-no-ref/
232		i2c6m2_xfer: i2c6m2-xfer {
233			rockchip,pins =
234				/* i2c6_scl_m2 */
235				<2 RK_PC3 9 &pcfg_pull_none_smt>,
236				/* i2c6_sda_m2 */
237				<2 RK_PC2 9 &pcfg_pull_none_smt>;
238		};
239	};
240
241	i2c7 {
242		/omit-if-no-ref/
243		i2c7m1_xfer: i2c7m1-xfer {
244			rockchip,pins =
245				/* i2c7_scl_m1 */
246				<4 RK_PC3 9 &pcfg_pull_none_smt>,
247				/* i2c7_sda_m1 */
248				<4 RK_PC4 9 &pcfg_pull_none_smt>;
249		};
250	};
251
252	i2c8 {
253		/omit-if-no-ref/
254		i2c8m1_xfer: i2c8m1-xfer {
255			rockchip,pins =
256				/* i2c8_scl_m1 */
257				<2 RK_PB0 9 &pcfg_pull_none_smt>,
258				/* i2c8_sda_m1 */
259				<2 RK_PB1 9 &pcfg_pull_none_smt>;
260		};
261	};
262
263	i2s2 {
264		/omit-if-no-ref/
265		i2s2m0_lrck: i2s2m0-lrck {
266			rockchip,pins =
267				/* i2s2m0_lrck */
268				<2 RK_PC0 2 &pcfg_pull_none>;
269		};
270
271		/omit-if-no-ref/
272		i2s2m0_mclk: i2s2m0-mclk {
273			rockchip,pins =
274				/* i2s2m0_mclk */
275				<2 RK_PB6 2 &pcfg_pull_none>;
276		};
277
278		/omit-if-no-ref/
279		i2s2m0_sclk: i2s2m0-sclk {
280			rockchip,pins =
281				/* i2s2m0_sclk */
282				<2 RK_PB7 2 &pcfg_pull_none>;
283		};
284
285		/omit-if-no-ref/
286		i2s2m0_sdi: i2s2m0-sdi {
287			rockchip,pins =
288				/* i2s2m0_sdi */
289				<2 RK_PC3 2 &pcfg_pull_none>;
290		};
291
292		/omit-if-no-ref/
293		i2s2m0_sdo: i2s2m0-sdo {
294			rockchip,pins =
295				/* i2s2m0_sdo */
296				<4 RK_PC3 2 &pcfg_pull_none>;
297		};
298	};
299
300	pwm2 {
301		/omit-if-no-ref/
302		pwm2m2_pins: pwm2m2-pins {
303			rockchip,pins =
304				/* pwm2_m2 */
305				<4 RK_PC2 11 &pcfg_pull_none>;
306		};
307	};
308
309	pwm4 {
310		/omit-if-no-ref/
311		pwm4m1_pins: pwm4m1-pins {
312			rockchip,pins =
313				/* pwm4_m1 */
314				<4 RK_PC3 11 &pcfg_pull_none>;
315		};
316	};
317
318	pwm5 {
319		/omit-if-no-ref/
320		pwm5m2_pins: pwm5m2-pins {
321			rockchip,pins =
322				/* pwm5_m2 */
323				<4 RK_PC4 11 &pcfg_pull_none>;
324		};
325	};
326
327	pwm6 {
328		/omit-if-no-ref/
329		pwm6m2_pins: pwm6m2-pins {
330			rockchip,pins =
331				/* pwm6_m2 */
332				<4 RK_PC5 11 &pcfg_pull_none>;
333		};
334	};
335
336	pwm7 {
337		/omit-if-no-ref/
338		pwm7m3_pins: pwm7m3-pins {
339			rockchip,pins =
340				/* pwm7_ir_m3 */
341				<4 RK_PC6 11 &pcfg_pull_none>;
342		};
343	};
344
345	sdio {
346		/omit-if-no-ref/
347		sdiom0_pins: sdiom0-pins {
348			rockchip,pins =
349				/* sdio_clk_m0 */
350				<2 RK_PB3 2 &pcfg_pull_none>,
351				/* sdio_cmd_m0 */
352				<2 RK_PB2 2 &pcfg_pull_none>,
353				/* sdio_d0_m0 */
354				<2 RK_PA6 2 &pcfg_pull_none>,
355				/* sdio_d1_m0 */
356				<2 RK_PA7 2 &pcfg_pull_none>,
357				/* sdio_d2_m0 */
358				<2 RK_PB0 2 &pcfg_pull_none>,
359				/* sdio_d3_m0 */
360				<2 RK_PB1 2 &pcfg_pull_none>;
361		};
362	};
363
364	spi1 {
365		/omit-if-no-ref/
366		spi1m0_pins: spi1m0-pins {
367			rockchip,pins =
368				/* spi1_clk_m0 */
369				<2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
370				/* spi1_miso_m0 */
371				<2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
372				/* spi1_mosi_m0 */
373				<2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
374		};
375
376		/omit-if-no-ref/
377		spi1m0_cs0: spi1m0-cs0 {
378			rockchip,pins =
379				/* spi1_cs0_m0 */
380				<2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
381		};
382
383		/omit-if-no-ref/
384		spi1m0_cs1: spi1m0-cs1 {
385			rockchip,pins =
386				/* spi1_cs1_m0 */
387				<2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
388		};
389	};
390
391	spi3 {
392		/omit-if-no-ref/
393		spi3m0_pins: spi3m0-pins {
394			rockchip,pins =
395				/* spi3_clk_m0 */
396				<4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
397				/* spi3_miso_m0 */
398				<4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
399				/* spi3_mosi_m0 */
400				<4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
401		};
402
403		/omit-if-no-ref/
404		spi3m0_cs0: spi3m0-cs0 {
405			rockchip,pins =
406				/* spi3_cs0_m0 */
407				<4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
408		};
409
410		/omit-if-no-ref/
411		spi3m0_cs1: spi3m0-cs1 {
412			rockchip,pins =
413				/* spi3_cs1_m0 */
414				<4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
415		};
416	};
417
418	uart1 {
419		/omit-if-no-ref/
420		uart1m0_xfer: uart1m0-xfer {
421			rockchip,pins =
422				/* uart1_rx_m0 */
423				<2 RK_PB6 10 &pcfg_pull_up>,
424				/* uart1_tx_m0 */
425				<2 RK_PB7 10 &pcfg_pull_up>;
426		};
427
428		/omit-if-no-ref/
429		uart1m0_ctsn: uart1m0-ctsn {
430			rockchip,pins =
431				/* uart1m0_ctsn */
432				<2 RK_PC1 10 &pcfg_pull_none>;
433		};
434
435		/omit-if-no-ref/
436		uart1m0_rtsn: uart1m0-rtsn {
437			rockchip,pins =
438				/* uart1m0_rtsn */
439				<2 RK_PC0 10 &pcfg_pull_none>;
440		};
441	};
442
443	uart6 {
444		/omit-if-no-ref/
445		uart6m0_xfer: uart6m0-xfer {
446			rockchip,pins =
447				/* uart6_rx_m0 */
448				<2 RK_PA6 10 &pcfg_pull_up>,
449				/* uart6_tx_m0 */
450				<2 RK_PA7 10 &pcfg_pull_up>;
451		};
452
453		/omit-if-no-ref/
454		uart6m0_ctsn: uart6m0-ctsn {
455			rockchip,pins =
456				/* uart6m0_ctsn */
457				<2 RK_PB1 10 &pcfg_pull_none>;
458		};
459
460		/omit-if-no-ref/
461		uart6m0_rtsn: uart6m0-rtsn {
462			rockchip,pins =
463				/* uart6m0_rtsn */
464				<2 RK_PB0 10 &pcfg_pull_none>;
465		};
466	};
467
468	uart7 {
469		/omit-if-no-ref/
470		uart7m0_xfer: uart7m0-xfer {
471			rockchip,pins =
472				/* uart7_rx_m0 */
473				<2 RK_PB4 10 &pcfg_pull_up>,
474				/* uart7_tx_m0 */
475				<2 RK_PB5 10 &pcfg_pull_up>;
476		};
477
478		/omit-if-no-ref/
479		uart7m0_ctsn: uart7m0-ctsn {
480			rockchip,pins =
481				/* uart7m0_ctsn */
482				<4 RK_PC6 10 &pcfg_pull_none>;
483		};
484
485		/omit-if-no-ref/
486		uart7m0_rtsn: uart7m0-rtsn {
487			rockchip,pins =
488				/* uart7m0_rtsn */
489				<4 RK_PC2 10 &pcfg_pull_none>;
490		};
491	};
492
493	uart9 {
494		/omit-if-no-ref/
495		uart9m0_xfer: uart9m0-xfer {
496			rockchip,pins =
497				/* uart9_rx_m0 */
498				<2 RK_PC4 10 &pcfg_pull_up>,
499				/* uart9_tx_m0 */
500				<2 RK_PC2 10 &pcfg_pull_up>;
501		};
502
503		/omit-if-no-ref/
504		uart9m0_ctsn: uart9m0-ctsn {
505			rockchip,pins =
506				/* uart9m0_ctsn */
507				<4 RK_PC5 10 &pcfg_pull_none>;
508		};
509
510		/omit-if-no-ref/
511		uart9m0_rtsn: uart9m0-rtsn {
512			rockchip,pins =
513				/* uart9m0_rtsn */
514				<4 RK_PC4 10 &pcfg_pull_none>;
515		};
516	};
517};
518