1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/soc/rockchip,vop2.h> 8 9/ { 10 chosen { 11 stdout-path = "serial2:1500000n8"; 12 }; 13 14 hdmi1-con { 15 compatible = "hdmi-connector"; 16 type = "a"; 17 18 port { 19 hdmi1_con_in: endpoint { 20 remote-endpoint = <&hdmi1_out_con>; 21 }; 22 }; 23 }; 24 25 /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ 26 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { 27 compatible = "gated-fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <100000000>; 30 clock-output-names = "pcie30_refclk"; 31 vdd-supply = <&vcc3v3_pi6c_05>; 32 }; 33 34 vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { 35 compatible = "regulator-fixed"; 36 regulator-name = "vcc3v3_pcie2x1l0"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 startup-delay-us = <5000>; 40 vin-supply = <&vcc_3v3_s3>; 41 }; 42 43 vcc3v3_bkey: regulator-vcc3v3-bkey { 44 compatible = "regulator-fixed"; 45 enable-active-high; 46 gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pcie_4g_pwen>; 49 regulator-name = "vcc3v3_bkey"; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 startup-delay-us = <5000>; 53 vin-supply = <&vcc5v0_sys>; 54 }; 55 56 vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { 57 compatible = "regulator-fixed"; 58 enable-active-high; 59 gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pcie30x4_pwren_h>; 62 regulator-name = "vcc3v3_pcie30"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 startup-delay-us = <5000>; 66 vin-supply = <&vcc5v0_sys>; 67 }; 68 69 vcc5v0_host: regulator-vcc5v0-host { 70 compatible = "regulator-fixed"; 71 enable-active-high; 72 gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&vcc5v0_host_en>; 75 regulator-name = "vcc5v0_host"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 regulator-boot-on; 79 regulator-always-on; 80 vin-supply = <&vcc5v0_sys>; 81 }; 82}; 83 84&combphy0_ps { 85 status = "okay"; 86}; 87 88&combphy1_ps { 89 status = "okay"; 90}; 91 92&combphy2_psu { 93 status = "okay"; 94}; 95 96&hdmi1 { 97 status = "okay"; 98}; 99 100&hdmi1_in { 101 hdmi1_in_vp0: endpoint { 102 remote-endpoint = <&vp0_out_hdmi1>; 103 }; 104}; 105 106&hdmi1_out { 107 hdmi1_out_con: endpoint { 108 remote-endpoint = <&hdmi1_con_in>; 109 }; 110}; 111 112&hdptxphy1 { 113 status = "okay"; 114}; 115 116&i2c6 { 117 status = "okay"; 118 119 hym8563: rtc@51 { 120 compatible = "haoyu,hym8563"; 121 reg = <0x51>; 122 interrupt-parent = <&gpio0>; 123 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 124 #clock-cells = <0>; 125 clock-output-names = "hym8563"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&hym8563_int>; 128 wakeup-source; 129 }; 130}; 131 132/* ETH */ 133&pcie2x1l0 { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pcie2_0_rst>; 136 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */ 137 vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; 138 status = "okay"; 139}; 140 141&pcie30phy { 142 data-lanes = <1 1 2 2>; 143 /* separate clock lines from the clock generator to phy and devices */ 144 rockchip,rx-common-refclk-mode = <0 0 0 0>; 145 status = "okay"; 146}; 147 148/* M-Key */ 149&pcie3x2 { 150 /* 151 * The board has a "pcie_refclk" oscillator that needs enabling, 152 * so add it to the list of clocks. 153 */ 154 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 155 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 156 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, 157 <&pcie30_port1_refclk>; 158 clock-names = "aclk_mst", "aclk_slv", 159 "aclk_dbi", "pclk", 160 "aux", "pipe", 161 "ref"; 162 num-lanes = <2>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pcie30x2_perstn_m1_l>; 165 reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ 166 vpcie3v3-supply = <&vcc3v3_pcie30>; 167 status = "okay"; 168}; 169 170/* B-Key and E-Key */ 171&pcie3x4 { 172 /* 173 * The board has a "pcie_refclk" oscillator that needs enabling, 174 * so add it to the list of clocks. 175 */ 176 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 177 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 178 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, 179 <&pcie30_port0_refclk>; 180 clock-names = "aclk_mst", "aclk_slv", 181 "aclk_dbi", "pclk", 182 "aux", "pipe", 183 "ref"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pcie30x4_perstn_m1_l>; 186 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ 187 vpcie3v3-supply = <&vcc3v3_bkey>; 188 status = "okay"; 189}; 190 191&pinctrl { 192 pcie2 { 193 pcie2_0_rst: pcie2-0-rst { 194 rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 195 }; 196 }; 197 198 pcie3 { 199 pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l { 200 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 201 }; 202 203 pcie_4g_pwen: pcie-4g-pwen { 204 rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; 205 }; 206 207 pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l { 208 rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 209 }; 210 211 pcie30x4_pwren_h: pcie30x4-pwren-h { 212 rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; 213 }; 214 }; 215 216 hym8563 { 217 hym8563_int: hym8563-int { 218 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 219 }; 220 }; 221 222 usb { 223 vcc5v0_host_en: vcc5v0-host-en { 224 rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 225 }; 226 }; 227}; 228 229/* FAN */ 230&pwm2 { 231 pinctrl-0 = <&pwm2m1_pins>; 232 pinctrl-names = "default"; 233 status = "okay"; 234}; 235 236&sata0 { 237 status = "okay"; 238}; 239 240&sdmmc { 241 bus-width = <4>; 242 cap-mmc-highspeed; 243 cap-sd-highspeed; 244 disable-wp; 245 no-sdio; 246 no-mmc; 247 sd-uhs-sdr104; 248 vmmc-supply = <&vcc_3v3_s3>; 249 vqmmc-supply = <&vccio_sd_s0>; 250 status = "okay"; 251}; 252 253&uart2 { 254 pinctrl-0 = <&uart2m0_xfer>; 255 status = "okay"; 256}; 257 258/* RS232 */ 259&uart6 { 260 pinctrl-0 = <&uart6m0_xfer>; 261 pinctrl-names = "default"; 262 status = "okay"; 263}; 264 265/* RS485 */ 266&uart7 { 267 pinctrl-0 = <&uart7m2_xfer>; 268 pinctrl-names = "default"; 269 status = "okay"; 270}; 271 272&u2phy2 { 273 status = "okay"; 274}; 275 276&u2phy2_host { 277 /* connected to USB hub, which is powered by vcc5v0_sys */ 278 phy-supply = <&vcc5v0_sys>; 279 status = "okay"; 280}; 281 282&u2phy3 { 283 status = "okay"; 284}; 285 286&u2phy3_host { 287 phy-supply = <&vcc5v0_host>; 288 status = "okay"; 289}; 290 291&usb_host0_ehci { 292 status = "okay"; 293}; 294 295&usb_host0_ohci { 296 status = "okay"; 297}; 298 299&usb_host1_ehci { 300 status = "okay"; 301}; 302 303&usb_host1_ohci { 304 status = "okay"; 305}; 306 307&usb_host2_xhci { 308 status = "okay"; 309}; 310 311&vop_mmu { 312 status = "okay"; 313}; 314 315&vop { 316 status = "okay"; 317}; 318 319&vp0 { 320 vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { 321 reg = <ROCKCHIP_VOP2_EP_HDMI1>; 322 remote-endpoint = <&hdmi1_in_vp0>; 323 }; 324}; 325