1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3562-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/reset/rockchip,rk3562-cru.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3562"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 }; 29 30 xin32k: clock-xin32k { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <32768>; 34 clock-output-names = "xin32k"; 35 }; 36 37 xin24m: clock-xin24m { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <24000000>; 41 clock-output-names = "xin24m"; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 clocks = <&scmi_clk ARMCLK>; 54 cpu-idle-states = <&CPU_SLEEP>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 #cooling-cells = <2>; 57 dynamic-power-coefficient = <138>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x1>; 64 enable-method = "psci"; 65 clocks = <&scmi_clk ARMCLK>; 66 cpu-idle-states = <&CPU_SLEEP>; 67 operating-points-v2 = <&cpu0_opp_table>; 68 #cooling-cells = <2>; 69 dynamic-power-coefficient = <138>; 70 }; 71 72 cpu2: cpu@2 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x2>; 76 enable-method = "psci"; 77 clocks = <&scmi_clk ARMCLK>; 78 cpu-idle-states = <&CPU_SLEEP>; 79 operating-points-v2 = <&cpu0_opp_table>; 80 #cooling-cells = <2>; 81 dynamic-power-coefficient = <138>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 clocks = <&scmi_clk ARMCLK>; 90 cpu-idle-states = <&CPU_SLEEP>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 #cooling-cells = <2>; 93 dynamic-power-coefficient = <138>; 94 }; 95 96 idle-states { 97 entry-method = "psci"; 98 99 CPU_SLEEP: cpu-sleep { 100 compatible = "arm,idle-state"; 101 local-timer-stop; 102 arm,psci-suspend-param = <0x0010000>; 103 entry-latency-us = <120>; 104 exit-latency-us = <250>; 105 min-residency-us = <900>; 106 }; 107 }; 108 }; 109 110 cpu0_opp_table: opp-table-cpu0 { 111 compatible = "operating-points-v2"; 112 opp-shared; 113 114 opp-408000000 { 115 opp-hz = /bits/ 64 <408000000>; 116 opp-microvolt = <825000 825000 1150000>; 117 clock-latency-ns = <40000>; 118 opp-suspend; 119 }; 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <825000 825000 1150000>; 123 clock-latency-ns = <40000>; 124 }; 125 opp-816000000 { 126 opp-hz = /bits/ 64 <816000000>; 127 opp-microvolt = <825000 825000 1150000>; 128 clock-latency-ns = <40000>; 129 }; 130 opp-1008000000 { 131 opp-hz = /bits/ 64 <1008000000>; 132 opp-microvolt = <850000 850000 1150000>; 133 clock-latency-ns = <40000>; 134 }; 135 opp-1200000000 { 136 opp-hz = /bits/ 64 <1200000000>; 137 opp-microvolt = <925000 925000 1150000>; 138 clock-latency-ns = <40000>; 139 }; 140 opp-1416000000 { 141 opp-hz = /bits/ 64 <1416000000>; 142 opp-microvolt = <1000000 1000000 1150000>; 143 clock-latency-ns = <40000>; 144 }; 145 opp-1608000000 { 146 opp-supported-hw = <0xf9 0xffff>; 147 opp-hz = /bits/ 64 <1608000000>; 148 opp-microvolt = <1037500 1037500 1150000>; 149 clock-latency-ns = <40000>; 150 }; 151 opp-1800000000 { 152 opp-hz = /bits/ 64 <1800000000>; 153 opp-microvolt = <1125000 1125000 1150000>; 154 clock-latency-ns = <40000>; 155 }; 156 opp-2016000000 { 157 opp-hz = /bits/ 64 <2016000000>; 158 opp-microvolt = <1150000 1150000 1150000>; 159 clock-latency-ns = <40000>; 160 }; 161 162 }; 163 164 gpu_opp_table: opp-table-gpu { 165 compatible = "operating-points-v2"; 166 167 opp-300000000 { 168 opp-hz = /bits/ 64 <300000000>; 169 opp-microvolt = <825000 825000 1000000>; 170 }; 171 opp-400000000 { 172 opp-hz = /bits/ 64 <400000000>; 173 opp-microvolt = <825000 825000 1000000>; 174 }; 175 opp-500000000 { 176 opp-hz = /bits/ 64 <500000000>; 177 opp-microvolt = <825000 825000 1000000>; 178 }; 179 opp-600000000 { 180 opp-hz = /bits/ 64 <600000000>; 181 opp-microvolt = <825000 825000 1000000>; 182 }; 183 opp-700000000 { 184 opp-hz = /bits/ 64 <700000000>; 185 opp-microvolt = <900000 900000 1000000>; 186 }; 187 opp-800000000 { 188 opp-hz = /bits/ 64 <800000000>; 189 opp-microvolt = <950000 950000 1000000>; 190 }; 191 opp-900000000 { 192 opp-hz = /bits/ 64 <900000000>; 193 opp-microvolt = <1000000 1000000 1000000>; 194 }; 195 }; 196 197 arm_pmu: arm-pmu { 198 compatible = "arm,cortex-a53-pmu"; 199 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 204 }; 205 206 firmware { 207 scmi: scmi { 208 compatible = "arm,scmi-smc"; 209 shmem = <&scmi_shmem>; 210 arm,smc-id = <0x82000010>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 scmi_clk: protocol@14 { 215 reg = <0x14>; 216 #clock-cells = <1>; 217 }; 218 }; 219 }; 220 221 pinctrl: pinctrl { 222 compatible = "rockchip,rk3562-pinctrl"; 223 rockchip,grf = <&ioc_grf>; 224 #address-cells = <2>; 225 #size-cells = <2>; 226 ranges; 227 228 gpio0: gpio@ff260000 { 229 compatible = "rockchip,gpio-bank"; 230 reg = <0x0 0xff260000 0x0 0x100>; 231 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; 232 gpio-controller; 233 gpio-ranges = <&pinctrl 0 0 32>; 234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-controller; 236 #gpio-cells = <2>; 237 #interrupt-cells = <2>; 238 }; 239 240 gpio1: gpio@ff620000 { 241 compatible = "rockchip,gpio-bank"; 242 reg = <0x0 0xff620000 0x0 0x100>; 243 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; 244 gpio-controller; 245 gpio-ranges = <&pinctrl 0 32 32>; 246 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-controller; 248 #gpio-cells = <2>; 249 #interrupt-cells = <2>; 250 }; 251 252 gpio2: gpio@ff630000 { 253 compatible = "rockchip,gpio-bank"; 254 reg = <0x0 0xff630000 0x0 0x100>; 255 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; 256 gpio-controller; 257 gpio-ranges = <&pinctrl 0 64 32>; 258 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-controller; 260 #gpio-cells = <2>; 261 #interrupt-cells = <2>; 262 }; 263 264 gpio3: gpio@ffac0000 { 265 compatible = "rockchip,gpio-bank"; 266 reg = <0x0 0xffac0000 0x0 0x100>; 267 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; 268 gpio-controller; 269 gpio-ranges = <&pinctrl 0 96 32>; 270 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-controller; 272 #gpio-cells = <2>; 273 #interrupt-cells = <2>; 274 }; 275 276 gpio4: gpio@ffad0000 { 277 compatible = "rockchip,gpio-bank"; 278 reg = <0x0 0xffad0000 0x0 0x100>; 279 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; 280 gpio-controller; 281 gpio-ranges = <&pinctrl 0 128 32>; 282 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-controller; 284 #gpio-cells = <2>; 285 #interrupt-cells = <2>; 286 }; 287 }; 288 289 psci { 290 compatible = "arm,psci-1.0"; 291 method = "smc"; 292 }; 293 294 reserved-memory { 295 #address-cells = <2>; 296 #size-cells = <2>; 297 ranges; 298 299 scmi_shmem: shmem@10f000 { 300 compatible = "arm,scmi-shmem"; 301 reg = <0x0 0x0010f000 0x0 0x100>; 302 no-map; 303 }; 304 }; 305 306 timer { 307 compatible = "arm,armv8-timer"; 308 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 309 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 310 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 311 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 ranges; 319 320 pcie2x1: pcie@fe000000 { 321 compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; 322 reg = <0x0 0xfe000000 0x0 0x400000>, 323 <0x0 0xff500000 0x0 0x10000>, 324 <0x0 0xfc000000 0x0 0x100000>; 325 reg-names = "dbi", "apb", "config"; 326 bus-range = <0x0 0xff>; 327 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 328 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 329 <&cru CLK_PCIE20_AUX>; 330 clock-names = "aclk_mst", "aclk_slv", 331 "aclk_dbi", "pclk", "aux"; 332 device_type = "pci"; 333 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 339 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 340 #interrupt-cells = <1>; 341 interrupt-map-mask = <0 0 0 7>; 342 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 343 <0 0 0 2 &pcie2x1_intc 1>, 344 <0 0 0 3 &pcie2x1_intc 2>, 345 <0 0 0 4 &pcie2x1_intc 3>; 346 linux,pci-domain = <0>; 347 max-link-speed = <2>; 348 num-ib-windows = <8>; 349 num-viewport = <8>; 350 num-ob-windows = <2>; 351 num-lanes = <1>; 352 phys = <&combphy PHY_TYPE_PCIE>; 353 phy-names = "pcie-phy"; 354 power-domains = <&power 15>; 355 ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 356 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 357 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 358 resets = <&cru SRST_PCIE20_POWERUP>; 359 reset-names = "pipe"; 360 #address-cells = <3>; 361 #size-cells = <2>; 362 status = "disabled"; 363 364 pcie2x1_intc: legacy-interrupt-controller { 365 interrupt-controller; 366 #address-cells = <0>; 367 #interrupt-cells = <1>; 368 interrupt-parent = <&gic>; 369 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 370 }; 371 }; 372 373 gic: interrupt-controller@fe901000 { 374 compatible = "arm,gic-400"; 375 #interrupt-cells = <3>; 376 #address-cells = <0>; 377 interrupt-controller; 378 reg = <0x0 0xfe901000 0 0x1000>, 379 <0x0 0xfe902000 0 0x2000>, 380 <0x0 0xfe904000 0 0x2000>, 381 <0x0 0xfe906000 0 0x2000>; 382 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 383 }; 384 385 qos_dma2ddr: qos@fee03800 { 386 compatible = "rockchip,rk3562-qos", "syscon"; 387 reg = <0x0 0xfee03800 0x0 0x20>; 388 }; 389 390 qos_mcu: qos@fee10000 { 391 compatible = "rockchip,rk3562-qos", "syscon"; 392 reg = <0x0 0xfee10000 0x0 0x20>; 393 }; 394 395 qos_dft_apb: qos@fee10100 { 396 compatible = "rockchip,rk3562-qos", "syscon"; 397 reg = <0x0 0xfee10100 0x0 0x20>; 398 }; 399 400 qos_gmac: qos@fee10200 { 401 compatible = "rockchip,rk3562-qos", "syscon"; 402 reg = <0x0 0xfee10200 0x0 0x20>; 403 }; 404 405 qos_mac100: qos@fee10300 { 406 compatible = "rockchip,rk3562-qos", "syscon"; 407 reg = <0x0 0xfee10300 0x0 0x20>; 408 }; 409 410 qos_dcf: qos@fee10400 { 411 compatible = "rockchip,rk3562-qos", "syscon"; 412 reg = <0x0 0xfee10400 0x0 0x20>; 413 }; 414 415 qos_cpu: qos@fee20000 { 416 compatible = "rockchip,rk3562-qos", "syscon"; 417 reg = <0x0 0xfee20000 0x0 0x20>; 418 }; 419 420 qos_gpu: qos@fee30000 { 421 compatible = "rockchip,rk3562-qos", "syscon"; 422 reg = <0x0 0xfee30000 0x0 0x20>; 423 }; 424 425 qos_npu: qos@fee40000 { 426 compatible = "rockchip,rk3562-qos", "syscon"; 427 reg = <0x0 0xfee40000 0x0 0x20>; 428 }; 429 430 qos_rkvdec: qos@fee50000 { 431 compatible = "rockchip,rk3562-qos", "syscon"; 432 reg = <0x0 0xfee50000 0x0 0x20>; 433 }; 434 435 qos_vepu: qos@fee60000 { 436 compatible = "rockchip,rk3562-qos", "syscon"; 437 reg = <0x0 0xfee60000 0x0 0x20>; 438 }; 439 440 qos_isp: qos@fee70000 { 441 compatible = "rockchip,rk3562-qos", "syscon"; 442 reg = <0x0 0xfee70000 0x0 0x20>; 443 }; 444 445 qos_vicap: qos@fee70100 { 446 compatible = "rockchip,rk3562-qos", "syscon"; 447 reg = <0x0 0xfee70100 0x0 0x20>; 448 }; 449 450 qos_vop: qos@fee80000 { 451 compatible = "rockchip,rk3562-qos", "syscon"; 452 reg = <0x0 0xfee80000 0x0 0x20>; 453 }; 454 455 qos_jpeg: qos@fee90000 { 456 compatible = "rockchip,rk3562-qos", "syscon"; 457 reg = <0x0 0xfee90000 0x0 0x20>; 458 }; 459 460 qos_rga_rd: qos@fee90100 { 461 compatible = "rockchip,rk3562-qos", "syscon"; 462 reg = <0x0 0xfee90100 0x0 0x20>; 463 }; 464 465 qos_rga_wr: qos@fee90200 { 466 compatible = "rockchip,rk3562-qos", "syscon"; 467 reg = <0x0 0xfee90200 0x0 0x20>; 468 }; 469 470 qos_pcie: qos@feea0000 { 471 compatible = "rockchip,rk3562-qos", "syscon"; 472 reg = <0x0 0xfeea0000 0x0 0x20>; 473 }; 474 475 qos_usb3: qos@feea0100 { 476 compatible = "rockchip,rk3562-qos", "syscon"; 477 reg = <0x0 0xfeea0100 0x0 0x20>; 478 }; 479 480 qos_crypto_apb: qos@feeb0000 { 481 compatible = "rockchip,rk3562-qos", "syscon"; 482 reg = <0x0 0xfeeb0000 0x0 0x20>; 483 }; 484 485 qos_crypto: qos@feeb0100 { 486 compatible = "rockchip,rk3562-qos", "syscon"; 487 reg = <0x0 0xfeeb0100 0x0 0x20>; 488 }; 489 490 qos_dmac: qos@feeb0200 { 491 compatible = "rockchip,rk3562-qos", "syscon"; 492 reg = <0x0 0xfeeb0200 0x0 0x20>; 493 }; 494 495 qos_emmc: qos@feeb0300 { 496 compatible = "rockchip,rk3562-qos", "syscon"; 497 reg = <0x0 0xfeeb0300 0x0 0x20>; 498 }; 499 500 qos_fspi: qos@feeb0400 { 501 compatible = "rockchip,rk3562-qos", "syscon"; 502 reg = <0x0 0xfeeb0400 0x0 0x20>; 503 }; 504 505 qos_rkdma: qos@feeb0500 { 506 compatible = "rockchip,rk3562-qos", "syscon"; 507 reg = <0x0 0xfeeb0500 0x0 0x20>; 508 }; 509 510 qos_sdmmc0: qos@feeb0600 { 511 compatible = "rockchip,rk3562-qos", "syscon"; 512 reg = <0x0 0xfeeb0600 0x0 0x20>; 513 }; 514 515 qos_sdmmc1: qos@feeb0700 { 516 compatible = "rockchip,rk3562-qos", "syscon"; 517 reg = <0x0 0xfeeb0700 0x0 0x20>; 518 }; 519 520 qos_usb2: qos@feeb0800 { 521 compatible = "rockchip,rk3562-qos", "syscon"; 522 reg = <0x0 0xfeeb0800 0x0 0x20>; 523 }; 524 525 pmu_grf: syscon@ff010000 { 526 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; 527 reg = <0x0 0xff010000 0x0 0x10000>; 528 529 reboot_mode: reboot-mode { 530 compatible = "syscon-reboot-mode"; 531 offset = <0x220>; 532 mode-normal = <BOOT_NORMAL>; 533 mode-loader = <BOOT_BL_DOWNLOAD>; 534 mode-recovery = <BOOT_RECOVERY>; 535 mode-bootloader = <BOOT_FASTBOOT>; 536 }; 537 }; 538 539 sys_grf: syscon@ff030000 { 540 compatible = "rockchip,rk3562-sys-grf", "syscon"; 541 reg = <0x0 0xff030000 0x0 0x10000>; 542 }; 543 544 peri_grf: syscon@ff040000 { 545 compatible = "rockchip,rk3562-peri-grf", "syscon"; 546 reg = <0x0 0xff040000 0x0 0x10000>; 547 }; 548 549 ioc_grf: syscon@ff060000 { 550 compatible = "rockchip,rk3562-ioc-grf", "syscon"; 551 reg = <0x0 0xff060000 0x0 0x30000>; 552 }; 553 554 usbphy_grf: syscon@ff090000 { 555 compatible = "rockchip,rk3562-usbphy-grf", "syscon"; 556 reg = <0x0 0xff090000 0x0 0x8000>; 557 }; 558 559 pipephy_grf: syscon@ff098000 { 560 compatible = "rockchip,rk3562-pipephy-grf", "syscon"; 561 reg = <0x0 0xff098000 0x0 0x8000>; 562 }; 563 564 cru: clock-controller@ff100000 { 565 compatible = "rockchip,rk3562-cru"; 566 reg = <0x0 0xff100000 0x0 0x40000>; 567 #clock-cells = <1>; 568 #reset-cells = <1>; 569 570 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 571 <&cru PLL_HPLL>; 572 assigned-clock-rates = <1188000000>, <1000000000>, 573 <983040000>; 574 }; 575 576 i2c0: i2c@ff200000 { 577 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff200000 0x0 0x1000>; 579 clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; 580 clock-names = "i2c", "pclk"; 581 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&i2c0_xfer>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 uart0: serial@ff210000 { 590 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 591 reg = <0x0 0xff210000 0x0 0x100>; 592 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; 594 clock-names = "baudclk", "apb_pclk"; 595 reg-shift = <2>; 596 reg-io-width = <4>; 597 status = "disabled"; 598 }; 599 600 spi0: spi@ff220000 { 601 compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi"; 602 reg = <0x0 0xff220000 0x0 0x1000>; 603 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; 605 clock-names = "spiclk", "apb_pclk"; 606 dmas = <&dmac 13>, <&dmac 12>; 607 dma-names = "tx", "rx"; 608 num-cs = <2>; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 pwm0: pwm@ff230000 { 617 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 618 reg = <0x0 0xff230000 0x0 0x10>; 619 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 620 clock-names = "pwm", "pclk"; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pwm0m0_pins>; 623 #pwm-cells = <3>; 624 status = "disabled"; 625 }; 626 627 pwm1: pwm@ff230010 { 628 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 629 reg = <0x0 0xff230010 0x0 0x10>; 630 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 631 clock-names = "pwm", "pclk"; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pwm1m0_pins>; 634 #pwm-cells = <3>; 635 status = "disabled"; 636 }; 637 638 pwm2: pwm@ff230020 { 639 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 640 reg = <0x0 0xff230020 0x0 0x10>; 641 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 642 clock-names = "pwm", "pclk"; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&pwm2m0_pins>; 645 #pwm-cells = <3>; 646 status = "disabled"; 647 }; 648 649 pwm3: pwm@ff230030 { 650 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 651 reg = <0x0 0xff230030 0x0 0x10>; 652 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 653 clock-names = "pwm", "pclk"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pwm3m0_pins>; 656 #pwm-cells = <3>; 657 status = "disabled"; 658 }; 659 660 pmu: power-management@ff258000 { 661 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; 662 reg = <0x0 0xff258000 0x0 0x1000>; 663 664 power: power-controller { 665 compatible = "rockchip,rk3562-power-controller"; 666 #power-domain-cells = <1>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 670 power-domain@8 { 671 reg = <8>; 672 pm_qos = <&qos_gpu>; 673 #power-domain-cells = <0>; 674 }; 675 676 power-domain@7 { 677 reg = <7>; 678 pm_qos = <&qos_npu>; 679 #power-domain-cells = <0>; 680 }; 681 682 power-domain@11 { 683 reg = <11>; 684 pm_qos = <&qos_rkvdec>; 685 #power-domain-cells = <0>; 686 }; 687 688 power-domain@12 { 689 reg = <12>; 690 pm_qos = <&qos_isp>, 691 <&qos_vicap>; 692 #power-domain-cells = <1>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 power-domain@10 { 697 reg = <10>; 698 pm_qos = <&qos_vepu>; 699 #power-domain-cells = <0>; 700 }; 701 }; 702 703 power-domain@13 { 704 reg = <13>; 705 pm_qos = <&qos_vop>; 706 #power-domain-cells = <1>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 power-domain@14 { 711 reg = <14>; 712 pm_qos = <&qos_rga_rd>, 713 <&qos_rga_wr>, 714 <&qos_jpeg>; 715 #power-domain-cells = <0>; 716 }; 717 }; 718 719 power-domain@15 { 720 reg = <15>; 721 pm_qos = <&qos_pcie>, 722 <&qos_usb3>; 723 #power-domain-cells = <0>; 724 }; 725 }; 726 }; 727 728 gpu: gpu@ff320000 { 729 compatible = "rockchip,rk3562-mali", "arm,mali-bifrost"; 730 reg = <0x0 0xff320000 0x0 0x4000>; 731 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>, 732 <&cru ACLK_GPU_PRE>; 733 clock-names = "clk_gpu", "clk_gpu_brg", "aclk_gpu"; 734 dynamic-power-coefficient = <820>; 735 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "job", "mmu", "gpu"; 739 operating-points-v2 = <&gpu_opp_table>; 740 power-domains = <&power 8>; 741 #cooling-cells = <2>; 742 status = "disabled"; 743 }; 744 745 spi1: spi@ff640000 { 746 compatible = "rockchip,rk3066-spi"; 747 reg = <0x0 0xff640000 0x0 0x1000>; 748 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 750 clock-names = "spiclk", "apb_pclk"; 751 dmas = <&dmac 15>, <&dmac 14>; 752 dma-names = "tx", "rx"; 753 num-cs = <2>; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 spi2: spi@ff650000 { 762 compatible = "rockchip,rk3066-spi"; 763 reg = <0x0 0xff650000 0x0 0x1000>; 764 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 766 clock-names = "spiclk", "apb_pclk"; 767 dmas = <&dmac 17>, <&dmac 16>; 768 dma-names = "tx", "rx"; 769 num-cs = <2>; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 uart1: serial@ff670000 { 778 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 779 reg = <0x0 0xff670000 0x0 0x100>; 780 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 782 clock-names = "baudclk", "apb_pclk"; 783 reg-shift = <2>; 784 reg-io-width = <4>; 785 status = "disabled"; 786 }; 787 788 uart2: serial@ff680000 { 789 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 790 reg = <0x0 0xff680000 0x0 0x100>; 791 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 793 clock-names = "baudclk", "apb_pclk"; 794 reg-shift = <2>; 795 reg-io-width = <4>; 796 status = "disabled"; 797 }; 798 799 uart3: serial@ff690000 { 800 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 801 reg = <0x0 0xff690000 0x0 0x100>; 802 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 804 clock-names = "baudclk", "apb_pclk"; 805 reg-shift = <2>; 806 reg-io-width = <4>; 807 status = "disabled"; 808 }; 809 810 uart4: serial@ff6a0000 { 811 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 812 reg = <0x0 0xff6a0000 0x0 0x100>; 813 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 815 clock-names = "baudclk", "apb_pclk"; 816 reg-shift = <2>; 817 reg-io-width = <4>; 818 status = "disabled"; 819 }; 820 821 uart5: serial@ff6b0000 { 822 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 823 reg = <0x0 0xff6b0000 0x0 0x100>; 824 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 826 clock-names = "baudclk", "apb_pclk"; 827 reg-shift = <2>; 828 reg-io-width = <4>; 829 status = "disabled"; 830 }; 831 832 uart6: serial@ff6c0000 { 833 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 834 reg = <0x0 0xff6c0000 0x0 0x100>; 835 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 837 clock-names = "baudclk", "apb_pclk"; 838 reg-shift = <2>; 839 reg-io-width = <4>; 840 status = "disabled"; 841 }; 842 843 uart7: serial@ff6d0000 { 844 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 845 reg = <0x0 0xff6d0000 0x0 0x100>; 846 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 848 clock-names = "baudclk", "apb_pclk"; 849 reg-shift = <2>; 850 reg-io-width = <4>; 851 status = "disabled"; 852 }; 853 854 uart8: serial@ff6e0000 { 855 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 856 reg = <0x0 0xff6e0000 0x0 0x100>; 857 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 859 clock-names = "baudclk", "apb_pclk"; 860 reg-shift = <2>; 861 reg-io-width = <4>; 862 status = "disabled"; 863 }; 864 865 uart9: serial@ff6f0000 { 866 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 867 reg = <0x0 0xff6f0000 0x0 0x100>; 868 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 870 clock-names = "baudclk", "apb_pclk"; 871 reg-shift = <2>; 872 reg-io-width = <4>; 873 status = "disabled"; 874 }; 875 876 pwm4: pwm@ff700000 { 877 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 878 reg = <0x0 0xff700000 0x0 0x10>; 879 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 880 clock-names = "pwm", "pclk"; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&pwm4m0_pins>; 883 #pwm-cells = <3>; 884 status = "disabled"; 885 }; 886 887 pwm5: pwm@ff700010 { 888 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 889 reg = <0x0 0xff700010 0x0 0x10>; 890 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 891 clock-names = "pwm", "pclk"; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&pwm5m0_pins>; 894 #pwm-cells = <3>; 895 status = "disabled"; 896 }; 897 898 pwm6: pwm@ff700020 { 899 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 900 reg = <0x0 0xff700020 0x0 0x10>; 901 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 902 clock-names = "pwm", "pclk"; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&pwm6m0_pins>; 905 #pwm-cells = <3>; 906 status = "disabled"; 907 }; 908 909 pwm7: pwm@ff700030 { 910 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 911 reg = <0x0 0xff700030 0x0 0x10>; 912 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 913 clock-names = "pwm", "pclk"; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&pwm7m0_pins>; 916 #pwm-cells = <3>; 917 status = "disabled"; 918 }; 919 920 pwm8: pwm@ff710000 { 921 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 922 reg = <0x0 0xff710000 0x0 0x10>; 923 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 924 clock-names = "pwm", "pclk"; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&pwm8m0_pins>; 927 #pwm-cells = <3>; 928 status = "disabled"; 929 }; 930 931 pwm9: pwm@ff710010 { 932 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 933 reg = <0x0 0xff710010 0x0 0x10>; 934 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 935 clock-names = "pwm", "pclk"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&pwm9m0_pins>; 938 #pwm-cells = <3>; 939 status = "disabled"; 940 }; 941 942 pwm10: pwm@ff710020 { 943 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 944 reg = <0x0 0xff710020 0x0 0x10>; 945 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 946 clock-names = "pwm", "pclk"; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&pwm10m0_pins>; 949 #pwm-cells = <3>; 950 status = "disabled"; 951 }; 952 953 pwm11: pwm@ff710030 { 954 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 955 reg = <0x0 0xff710030 0x0 0x10>; 956 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 957 clock-names = "pwm", "pclk"; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&pwm11m0_pins>; 960 #pwm-cells = <3>; 961 status = "disabled"; 962 }; 963 964 pwm12: pwm@ff720000 { 965 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 966 reg = <0x0 0xff720000 0x0 0x10>; 967 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 968 clock-names = "pwm", "pclk"; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&pwm12m0_pins>; 971 #pwm-cells = <3>; 972 status = "disabled"; 973 }; 974 975 pwm13: pwm@ff720010 { 976 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 977 reg = <0x0 0xff720010 0x0 0x10>; 978 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 979 clock-names = "pwm", "pclk"; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&pwm13m0_pins>; 982 #pwm-cells = <3>; 983 status = "disabled"; 984 }; 985 986 pwm14: pwm@ff720020 { 987 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 988 reg = <0x0 0xff720020 0x0 0x10>; 989 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 990 clock-names = "pwm", "pclk"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&pwm14m0_pins>; 993 #pwm-cells = <3>; 994 status = "disabled"; 995 }; 996 997 pwm15: pwm@ff720030 { 998 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 999 reg = <0x0 0xff720030 0x0 0x10>; 1000 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1001 clock-names = "pwm", "pclk"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&pwm15m0_pins>; 1004 #pwm-cells = <3>; 1005 status = "disabled"; 1006 }; 1007 1008 saradc0: adc@ff730000 { 1009 compatible = "rockchip,rk3562-saradc"; 1010 reg = <0x0 0xff730000 0x0 0x100>; 1011 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1013 clock-names = "saradc", "apb_pclk"; 1014 resets = <&cru SRST_P_SARADC>; 1015 reset-names = "saradc-apb"; 1016 #io-channel-cells = <1>; 1017 status = "disabled"; 1018 }; 1019 1020 combphy: phy@ff750000 { 1021 compatible = "rockchip,rk3562-naneng-combphy"; 1022 reg = <0x0 0xff750000 0x0 0x100>; 1023 #phy-cells = <1>; 1024 clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, 1025 <&cru PCLK_PHP>; 1026 clock-names = "ref", "apb", "pipe"; 1027 assigned-clocks = <&cru CLK_PIPEPHY_REF>; 1028 assigned-clock-rates = <100000000>; 1029 resets = <&cru SRST_PIPEPHY>; 1030 reset-names = "phy"; 1031 rockchip,pipe-grf = <&peri_grf>; 1032 rockchip,pipe-phy-grf = <&pipephy_grf>; 1033 status = "disabled"; 1034 }; 1035 1036 sfc: spi@ff860000 { 1037 compatible = "rockchip,sfc"; 1038 reg = <0x0 0xff860000 0x0 0x10000>; 1039 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1041 clock-names = "clk_sfc", "hclk_sfc"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 sdhci: mmc@ff870000 { 1048 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc"; 1049 reg = <0x0 0xff870000 0x0 0x10000>; 1050 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1051 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; 1052 assigned-clock-rates = <200000000>, <200000000>; 1053 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1054 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1055 <&cru TMCLK_EMMC>; 1056 clock-names = "core", "bus", "axi", "block", "timer"; 1057 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1058 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1059 <&cru SRST_T_EMMC>; 1060 reset-names = "core", "bus", "axi", "block", "timer"; 1061 max-frequency = <200000000>; 1062 status = "disabled"; 1063 }; 1064 1065 sdmmc0: mmc@ff880000 { 1066 compatible = "rockchip,rk3562-dw-mshc", 1067 "rockchip,rk3288-dw-mshc"; 1068 reg = <0x0 0xff880000 0x0 0x10000>; 1069 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, 1071 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1072 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1073 fifo-depth = <0x100>; 1074 max-frequency = <200000000>; 1075 resets = <&cru SRST_H_SDMMC0>; 1076 reset-names = "reset"; 1077 status = "disabled"; 1078 }; 1079 1080 sdmmc1: mmc@ff890000 { 1081 compatible = "rockchip,rk3562-dw-mshc", 1082 "rockchip,rk3288-dw-mshc"; 1083 reg = <0x0 0xff890000 0x0 0x10000>; 1084 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, 1086 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1087 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1088 fifo-depth = <0x100>; 1089 max-frequency = <200000000>; 1090 resets = <&cru SRST_H_SDMMC1>; 1091 reset-names = "reset"; 1092 status = "disabled"; 1093 }; 1094 1095 dmac: dma-controller@ff990000 { 1096 compatible = "arm,pl330", "arm,primecell"; 1097 reg = <0x0 0xff990000 0x0 0x4000>; 1098 arm,pl330-periph-burst; 1099 clocks = <&cru ACLK_DMAC>; 1100 clock-names = "apb_pclk"; 1101 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1103 #dma-cells = <1>; 1104 }; 1105 1106 i2c1: i2c@ffa00000 { 1107 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1108 reg = <0x0 0xffa00000 0x0 0x1000>; 1109 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1110 clock-names = "i2c", "pclk"; 1111 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&i2c1m0_xfer>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 }; 1118 1119 i2c2: i2c@ffa10000 { 1120 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1121 reg = <0x0 0xffa10000 0x0 0x1000>; 1122 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1123 clock-names = "i2c", "pclk"; 1124 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&i2c2m0_xfer>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c3: i2c@ffa20000 { 1133 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1134 reg = <0x0 0xffa20000 0x0 0x1000>; 1135 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1136 clock-names = "i2c", "pclk"; 1137 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&i2c3m0_xfer>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 i2c4: i2c@ffa30000 { 1146 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1147 reg = <0x0 0xffa30000 0x0 0x1000>; 1148 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1149 clock-names = "i2c", "pclk"; 1150 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&i2c4m0_xfer>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2c5: i2c@ffa40000 { 1159 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1160 reg = <0x0 0xffa40000 0x0 0x1000>; 1161 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1162 clock-names = "i2c", "pclk"; 1163 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&i2c5m0_xfer>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 saradc1: adc@ffaa0000 { 1172 compatible = "rockchip,rk3562-saradc"; 1173 reg = <0x0 0xffaa0000 0x0 0x100>; 1174 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; 1176 clock-names = "saradc", "apb_pclk"; 1177 resets = <&cru SRST_P_SARADC_VCCIO156>; 1178 reset-names = "saradc-apb"; 1179 #io-channel-cells = <1>; 1180 status = "disabled"; 1181 }; 1182 }; 1183}; 1184 1185#include "rk3562-pinctrl.dtsi" 1186