xref: /linux/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts (revision 387b3bbac5ea6a0a105d685237f033ffe0f184f1)
1387b3bbaSTianling Shen// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2387b3bbaSTianling Shen/*
3387b3bbaSTianling Shen * Copyright (c) 2016 Xunlong Software. Co., Ltd.
4387b3bbaSTianling Shen * (http://www.orangepi.org)
5387b3bbaSTianling Shen *
6387b3bbaSTianling Shen * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
7387b3bbaSTianling Shen */
8387b3bbaSTianling Shen
9387b3bbaSTianling Shen/dts-v1/;
10387b3bbaSTianling Shen#include "rk3328-orangepi-r1-plus.dts"
11387b3bbaSTianling Shen
12387b3bbaSTianling Shen/ {
13387b3bbaSTianling Shen	model = "Xunlong Orange Pi R1 Plus LTS";
14387b3bbaSTianling Shen	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
15387b3bbaSTianling Shen};
16387b3bbaSTianling Shen
17387b3bbaSTianling Shen&gmac2io {
18387b3bbaSTianling Shen	phy-handle = <&yt8531c>;
19387b3bbaSTianling Shen	tx_delay = <0x19>;
20387b3bbaSTianling Shen	rx_delay = <0x05>;
21387b3bbaSTianling Shen
22387b3bbaSTianling Shen	mdio {
23387b3bbaSTianling Shen		/delete-node/ ethernet-phy@1;
24387b3bbaSTianling Shen
25387b3bbaSTianling Shen		yt8531c: ethernet-phy@0 {
26387b3bbaSTianling Shen			compatible = "ethernet-phy-ieee802.3-c22";
27387b3bbaSTianling Shen			reg = <0>;
28387b3bbaSTianling Shen
29387b3bbaSTianling Shen			motorcomm,clk-out-frequency-hz = <125000000>;
30387b3bbaSTianling Shen			motorcomm,keep-pll-enabled;
31387b3bbaSTianling Shen			motorcomm,auto-sleep-disabled;
32387b3bbaSTianling Shen
33387b3bbaSTianling Shen			pinctrl-0 = <&eth_phy_reset_pin>;
34387b3bbaSTianling Shen			pinctrl-names = "default";
35387b3bbaSTianling Shen			reset-assert-us = <15000>;
36387b3bbaSTianling Shen			reset-deassert-us = <50000>;
37387b3bbaSTianling Shen			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
38387b3bbaSTianling Shen		};
39387b3bbaSTianling Shen	};
40387b3bbaSTianling Shen};
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