1387b3bbaSTianling Shen// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2387b3bbaSTianling Shen/* 3387b3bbaSTianling Shen * Copyright (c) 2016 Xunlong Software. Co., Ltd. 4387b3bbaSTianling Shen * (http://www.orangepi.org) 5387b3bbaSTianling Shen * 6387b3bbaSTianling Shen * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> 7387b3bbaSTianling Shen */ 8387b3bbaSTianling Shen 9387b3bbaSTianling Shen/dts-v1/; 10f3c6526dSDragan Simic 11f3c6526dSDragan Simic#include "rk3328-orangepi-r1-plus.dtsi" 12387b3bbaSTianling Shen 13387b3bbaSTianling Shen/ { 14387b3bbaSTianling Shen model = "Xunlong Orange Pi R1 Plus LTS"; 15387b3bbaSTianling Shen compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; 16387b3bbaSTianling Shen}; 17387b3bbaSTianling Shen 18387b3bbaSTianling Shen&gmac2io { 19387b3bbaSTianling Shen phy-handle = <&yt8531c>; 20*a6a7cba1STianling Shen phy-mode = "rgmii-id"; 21f3c6526dSDragan Simic status = "okay"; 22387b3bbaSTianling Shen 23387b3bbaSTianling Shen mdio { 24387b3bbaSTianling Shen yt8531c: ethernet-phy@0 { 25387b3bbaSTianling Shen compatible = "ethernet-phy-ieee802.3-c22"; 26387b3bbaSTianling Shen reg = <0>; 27387b3bbaSTianling Shen 28fc5a80a4STianling Shen motorcomm,auto-sleep-disabled; 29387b3bbaSTianling Shen motorcomm,clk-out-frequency-hz = <125000000>; 30387b3bbaSTianling Shen motorcomm,keep-pll-enabled; 31fc5a80a4STianling Shen motorcomm,rx-clk-drv-microamp = <5020>; 32fc5a80a4STianling Shen motorcomm,rx-data-drv-microamp = <5020>; 33387b3bbaSTianling Shen 34387b3bbaSTianling Shen pinctrl-0 = <ð_phy_reset_pin>; 35387b3bbaSTianling Shen pinctrl-names = "default"; 36387b3bbaSTianling Shen reset-assert-us = <15000>; 37387b3bbaSTianling Shen reset-deassert-us = <50000>; 38387b3bbaSTianling Shen reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 39387b3bbaSTianling Shen }; 40387b3bbaSTianling Shen }; 41387b3bbaSTianling Shen}; 42