xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi (revision ec32d57b4bbf27d91c55c7a258bdb87690993ea6) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		i2c0 = &i2c0;
15		serial1 = &scif3;
16		serial3 = &scif0;
17		mmc1 = &sdhi1;
18	};
19
20	chosen {
21		bootargs = "ignore_loglevel";
22		stdout-path = "serial3:115200n8";
23	};
24
25	keys {
26		compatible = "gpio-keys";
27
28		key-1 {
29			interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
30			linux,code = <KEY_1>;
31			label = "USER_SW1";
32			wakeup-source;
33			debounce-interval = <20>;
34		};
35
36		key-2 {
37			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
38			linux,code = <KEY_2>;
39			label = "USER_SW2";
40			wakeup-source;
41			debounce-interval = <20>;
42		};
43
44		key-3 {
45			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
46			linux,code = <KEY_3>;
47			label = "USER_SW3";
48			wakeup-source;
49			debounce-interval = <20>;
50		};
51	};
52
53	snd_rzg3s: sound {
54		compatible = "simple-audio-card";
55		simple-audio-card,format = "i2s";
56		simple-audio-card,bitclock-master = <&cpu_dai>;
57		simple-audio-card,frame-master = <&cpu_dai>;
58		simple-audio-card,mclk-fs = <256>;
59
60		cpu_dai: simple-audio-card,cpu {
61			sound-dai = <&ssi3>;
62		};
63
64		codec_dai: simple-audio-card,codec {
65			sound-dai = <&da7212>;
66			clocks = <&versa3 1>;
67		};
68	};
69
70	vcc_sdhi1: regulator-vcc-sdhi1 {
71		compatible = "regulator-fixed";
72		regulator-name = "SDHI1 Vcc";
73		regulator-min-microvolt = <3300000>;
74		regulator-max-microvolt = <3300000>;
75		gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
76		enable-active-high;
77	};
78
79	vccq_sdhi1: regulator-vccq-sdhi1 {
80		compatible = "regulator-gpio";
81		regulator-name = "SDHI1 VccQ";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <3300000>;
84		gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
85		gpios-states = <1>;
86		states = <3300000 1>, <1800000 0>;
87	};
88};
89
90&audio_clk2 {
91	clock-frequency = <12288000>;
92};
93
94&i2c0 {
95	status = "okay";
96
97	clock-frequency = <1000000>;
98
99	da7212: codec@1a {
100		compatible = "dlg,da7212";
101		reg = <0x1a>;
102
103		clocks = <&versa3 1>;
104		clock-names = "mclk";
105
106		#sound-dai-cells = <0>;
107
108		dlg,micbias1-lvl = <2500>;
109		dlg,micbias2-lvl = <2500>;
110		dlg,dmic-data-sel = "lrise_rfall";
111		dlg,dmic-samplephase = "between_clkedge";
112		dlg,dmic-clkrate = <3000000>;
113
114		VDDA-supply = <&reg_1p8v>;
115		VDDSP-supply = <&reg_3p3v>;
116		VDDMIC-supply = <&reg_3p3v>;
117		VDDIO-supply = <&reg_1p8v>;
118	};
119};
120
121&i2c1 {
122	status = "okay";
123
124	clock-frequency = <400000>;
125
126	power-monitor@44 {
127		compatible = "renesas,isl28022";
128		reg = <0x44>;
129		shunt-resistor-micro-ohms = <8000>;
130		renesas,average-samples = <32>;
131	};
132};
133
134&pinctrl {
135	audio_clock_pins: audio-clock {
136		pins = "AUDIO_CLK1", "AUDIO_CLK2";
137		input-enable;
138	};
139
140	key-1-gpio-hog {
141		gpio-hog;
142		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
143		input;
144		line-name = "key-1-gpio-irq";
145	};
146
147	key-2-gpio-hog {
148		gpio-hog;
149		gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
150		input;
151		line-name = "key-2-gpio-irq";
152	};
153
154	key-3-gpio-hog {
155		gpio-hog;
156		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
157		input;
158		line-name = "key-3-gpio-irq";
159	};
160
161	scif0_pins: scif0 {
162		pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
163			 <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
164	};
165
166	scif3_pins: scif3 {
167		pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
168			 <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
169	};
170
171	sdhi1_pins: sd1 {
172		data {
173			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
174			power-source = <3300>;
175		};
176
177		ctrl {
178			pins = "SD1_CLK", "SD1_CMD";
179			power-source = <3300>;
180		};
181
182		cd {
183			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
184		};
185	};
186
187	sdhi1_pins_uhs: sd1-uhs {
188		data {
189			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
190			power-source = <1800>;
191		};
192
193		ctrl {
194			pins = "SD1_CLK", "SD1_CMD";
195			power-source = <1800>;
196		};
197
198		cd {
199			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
200		};
201	};
202
203	ssi3_pins: ssi3 {
204		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
205			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
206			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
207			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
208	};
209};
210
211&scif0 {
212	pinctrl-names = "default";
213	pinctrl-0 = <&scif0_pins>;
214	status = "okay";
215};
216
217&scif3 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&scif3_pins>;
220	status = "okay";
221};
222
223&sdhi1 {
224	pinctrl-0 = <&sdhi1_pins>;
225	pinctrl-1 = <&sdhi1_pins_uhs>;
226	pinctrl-names = "default", "state_uhs";
227	vmmc-supply = <&vcc_sdhi1>;
228	vqmmc-supply = <&vccq_sdhi1>;
229	bus-width = <4>;
230	sd-uhs-sdr50;
231	sd-uhs-sdr104;
232	max-frequency = <125000000>;
233	status = "okay";
234};
235
236&ssi3 {
237	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
238		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
239		 <&versa3 2>, <&audio_clk2>;
240	pinctrl-names = "default";
241	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
242	status = "okay";
243};
244