xref: /linux/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts (revision 6315d93541f8a5f77c5ef5c4f25233e66d189603) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2H EVK board
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
11#include <dt-bindings/gpio/gpio.h>
12#include "r9a09g057.dtsi"
13
14/ {
15	model = "Renesas RZ/V2H EVK Board based on r9a09g057h44";
16	compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057";
17
18	aliases {
19		i2c0 = &i2c0;
20		i2c1 = &i2c1;
21		i2c2 = &i2c2;
22		i2c3 = &i2c3;
23		i2c6 = &i2c6;
24		i2c7 = &i2c7;
25		i2c8 = &i2c8;
26		mmc1 = &sdhi1;
27		serial0 = &scif;
28	};
29
30	chosen {
31		bootargs = "ignore_loglevel";
32		stdout-path = "serial0:115200n8";
33	};
34
35	memory@48000000 {
36		device_type = "memory";
37		/* first 128MB is reserved for secure area. */
38		reg = <0x0 0x48000000 0x1 0xF8000000>;
39	};
40
41	memory@240000000 {
42		device_type = "memory";
43		reg = <0x2 0x40000000 0x2 0x00000000>;
44	};
45
46	reg_0p8v: regulator0 {
47		compatible = "regulator-fixed";
48
49		regulator-name = "fixed-0.8V";
50		regulator-min-microvolt = <800000>;
51		regulator-max-microvolt = <800000>;
52		regulator-boot-on;
53		regulator-always-on;
54	};
55
56	reg_3p3v: regulator1 {
57		compatible = "regulator-fixed";
58
59		regulator-name = "fixed-3.3V";
60		regulator-min-microvolt = <3300000>;
61		regulator-max-microvolt = <3300000>;
62		regulator-boot-on;
63		regulator-always-on;
64	};
65
66	vqmmc_sdhi1: regulator-vccq-sdhi1 {
67		compatible = "regulator-gpio";
68		regulator-name = "SDHI1 VccQ";
69		gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
70		regulator-min-microvolt = <1800000>;
71		regulator-max-microvolt = <3300000>;
72		gpios-states = <0>;
73		states = <3300000 0>, <1800000 1>;
74	};
75};
76
77&audio_extal_clk {
78	clock-frequency = <22579200>;
79};
80
81&gpu {
82	status = "okay";
83	mali-supply = <&reg_0p8v>;
84};
85
86&i2c0 {
87	pinctrl-0 = <&i2c0_pins>;
88	pinctrl-names = "default";
89	clock-frequency = <400000>;
90
91	status = "okay";
92};
93
94&i2c1 {
95	pinctrl-0 = <&i2c1_pins>;
96	pinctrl-names = "default";
97	clock-frequency = <400000>;
98
99	status = "okay";
100};
101
102&i2c2 {
103	pinctrl-0 = <&i2c2_pins>;
104	pinctrl-names = "default";
105	clock-frequency = <400000>;
106
107	status = "okay";
108};
109
110&i2c3 {
111	pinctrl-0 = <&i2c3_pins>;
112	pinctrl-names = "default";
113	clock-frequency = <400000>;
114
115	status = "okay";
116};
117
118&i2c6 {
119	pinctrl-0 = <&i2c6_pins>;
120	pinctrl-names = "default";
121	clock-frequency = <400000>;
122
123	status = "okay";
124};
125
126&i2c7 {
127	pinctrl-0 = <&i2c7_pins>;
128	pinctrl-names = "default";
129	clock-frequency = <400000>;
130
131	status = "okay";
132};
133
134&i2c8 {
135	pinctrl-0 = <&i2c8_pins>;
136	pinctrl-names = "default";
137	clock-frequency = <400000>;
138
139	status = "okay";
140};
141
142&ostm0 {
143	status = "okay";
144};
145
146&ostm1 {
147	status = "okay";
148};
149
150&ostm2 {
151	status = "okay";
152};
153
154&ostm3 {
155	status = "okay";
156};
157
158&ostm4 {
159	status = "okay";
160};
161
162&ostm5 {
163	status = "okay";
164};
165
166&ostm6 {
167	status = "okay";
168};
169
170&ostm7 {
171	status = "okay";
172};
173
174&pinctrl {
175	i2c0_pins: i2c0 {
176		pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
177			 <RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
178	};
179
180	i2c1_pins: i2c1 {
181		pinmux = <RZV2H_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
182			 <RZV2H_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
183	};
184
185	i2c2_pins: i2c2 {
186		pinmux = <RZV2H_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
187			 <RZV2H_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
188	};
189
190	i2c3_pins: i2c3 {
191		pinmux = <RZV2H_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
192			 <RZV2H_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
193	};
194
195	i2c6_pins: i2c6 {
196		pinmux = <RZV2H_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
197			 <RZV2H_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
198	};
199
200	i2c7_pins: i2c7 {
201		pinmux = <RZV2H_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
202			 <RZV2H_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
203	};
204
205	i2c8_pins: i2c8 {
206		pinmux = <RZV2H_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
207			 <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
208	};
209
210	scif_pins: scif {
211		pins = "SCIF_TXD", "SCIF_RXD";
212		renesas,output-impedance = <1>;
213	};
214
215	sd1-pwr-en-hog {
216		gpio-hog;
217		gpios = <RZV2H_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
218		output-high;
219		line-name = "sd1_pwr_en";
220	};
221
222	sdhi1_pins: sd1 {
223		sd1_dat_cmd {
224			pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
225			input-enable;
226			renesas,output-impedance = <3>;
227			slew-rate = <0>;
228		};
229
230		sd1_clk {
231			pins = "SD1CLK";
232			renesas,output-impedance = <3>;
233			slew-rate = <0>;
234		};
235
236		sd1_cd {
237			pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
238		};
239	};
240};
241
242&qextal_clk {
243	clock-frequency = <24000000>;
244};
245
246&rtxin_clk {
247	clock-frequency = <32768>;
248};
249
250&scif {
251	pinctrl-0 = <&scif_pins>;
252	pinctrl-names = "default";
253
254	status = "okay";
255};
256
257&sdhi1 {
258	pinctrl-0 = <&sdhi1_pins>;
259	pinctrl-1 = <&sdhi1_pins>;
260	pinctrl-names = "default", "state_uhs";
261	vmmc-supply = <&reg_3p3v>;
262	vqmmc-supply = <&vqmmc_sdhi1>;
263	bus-width = <4>;
264	sd-uhs-sdr50;
265	sd-uhs-sdr104;
266	status = "okay";
267};
268
269&wdt1 {
270	status = "okay";
271};
272