1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 audio_extal_clk: audio-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 /* This value must be overridden by the board */ 38 clock-frequency = <0>; 39 }; 40 41 /* 42 * The default cluster table is based on the assumption that the PLLCA55 clock 43 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 44 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 45 * clocked to 1.8GHz as well). The table below should be overridden in the board 46 * DTS based on the PLLCA55 clock frequency. 47 */ 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 51 opp-1700000000 { 52 opp-hz = /bits/ 64 <1700000000>; 53 opp-microvolt = <900000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-850000000 { 57 opp-hz = /bits/ 64 <850000000>; 58 opp-microvolt = <800000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-425000000 { 62 opp-hz = /bits/ 64 <425000000>; 63 opp-microvolt = <800000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-212500000 { 67 opp-hz = /bits/ 64 <212500000>; 68 opp-microvolt = <800000>; 69 clock-latency-ns = <300000>; 70 opp-suspend; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a55"; 80 reg = <0>; 81 device_type = "cpu"; 82 next-level-cache = <&L3_CA55>; 83 enable-method = "psci"; 84 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 85 operating-points-v2 = <&cluster0_opp>; 86 }; 87 88 cpu1: cpu@100 { 89 compatible = "arm,cortex-a55"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu2: cpu@200 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x200>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 115 operating-points-v2 = <&cluster0_opp>; 116 }; 117 118 L3_CA55: cache-controller-0 { 119 compatible = "cache"; 120 cache-unified; 121 cache-size = <0x100000>; 122 cache-level = <3>; 123 }; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0", "arm,psci-0.2"; 128 method = "smc"; 129 }; 130 131 qextal_clk: qextal-clk { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 /* This value must be overridden by the board */ 135 clock-frequency = <0>; 136 }; 137 138 rtxin_clk: rtxin-clk { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 /* This value must be overridden by the board */ 142 clock-frequency = <0>; 143 }; 144 145 soc: soc { 146 compatible = "simple-bus"; 147 interrupt-parent = <&gic>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 pinctrl: pinctrl@10410000 { 153 compatible = "renesas,r9a09g056-pinctrl"; 154 reg = <0 0x10410000 0 0x10000>; 155 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 gpio-ranges = <&pinctrl 0 0 96>; 159 power-domains = <&cpg>; 160 resets = <&cpg 0xa5>, <&cpg 0xa6>; 161 }; 162 163 cpg: clock-controller@10420000 { 164 compatible = "renesas,r9a09g056-cpg"; 165 reg = <0 0x10420000 0 0x10000>; 166 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 167 clock-names = "audio_extal", "rtxin", "qextal"; 168 #clock-cells = <2>; 169 #reset-cells = <1>; 170 #power-domain-cells = <0>; 171 }; 172 173 sys: system-controller@10430000 { 174 compatible = "renesas,r9a09g056-sys"; 175 reg = <0 0x10430000 0 0x10000>; 176 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 177 resets = <&cpg 0x30>; 178 }; 179 180 ostm0: timer@11800000 { 181 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 182 reg = <0x0 0x11800000 0x0 0x1000>; 183 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 184 clocks = <&cpg CPG_MOD 0x43>; 185 resets = <&cpg 0x6d>; 186 power-domains = <&cpg>; 187 status = "disabled"; 188 }; 189 190 ostm1: timer@11801000 { 191 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 192 reg = <0x0 0x11801000 0x0 0x1000>; 193 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 194 clocks = <&cpg CPG_MOD 0x44>; 195 resets = <&cpg 0x6e>; 196 power-domains = <&cpg>; 197 status = "disabled"; 198 }; 199 200 ostm2: timer@14000000 { 201 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 202 reg = <0x0 0x14000000 0x0 0x1000>; 203 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 204 clocks = <&cpg CPG_MOD 0x45>; 205 resets = <&cpg 0x6f>; 206 power-domains = <&cpg>; 207 status = "disabled"; 208 }; 209 210 ostm3: timer@14001000 { 211 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 212 reg = <0x0 0x14001000 0x0 0x1000>; 213 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 214 clocks = <&cpg CPG_MOD 0x46>; 215 resets = <&cpg 0x70>; 216 power-domains = <&cpg>; 217 status = "disabled"; 218 }; 219 220 ostm4: timer@12c00000 { 221 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 222 reg = <0x0 0x12c00000 0x0 0x1000>; 223 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 224 clocks = <&cpg CPG_MOD 0x47>; 225 resets = <&cpg 0x71>; 226 power-domains = <&cpg>; 227 status = "disabled"; 228 }; 229 230 ostm5: timer@12c01000 { 231 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 232 reg = <0x0 0x12c01000 0x0 0x1000>; 233 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 234 clocks = <&cpg CPG_MOD 0x48>; 235 resets = <&cpg 0x72>; 236 power-domains = <&cpg>; 237 status = "disabled"; 238 }; 239 240 ostm6: timer@12c02000 { 241 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 242 reg = <0x0 0x12c02000 0x0 0x1000>; 243 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 244 clocks = <&cpg CPG_MOD 0x49>; 245 resets = <&cpg 0x73>; 246 power-domains = <&cpg>; 247 status = "disabled"; 248 }; 249 250 ostm7: timer@12c03000 { 251 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 252 reg = <0x0 0x12c03000 0x0 0x1000>; 253 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 254 clocks = <&cpg CPG_MOD 0x4a>; 255 resets = <&cpg 0x74>; 256 power-domains = <&cpg>; 257 status = "disabled"; 258 }; 259 260 scif: serial@11c01400 { 261 compatible = "renesas,scif-r9a09g056", 262 "renesas,scif-r9a09g057"; 263 reg = <0 0x11c01400 0 0x400>; 264 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 273 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 274 "tei", "tei-dri", "rxi-edge", "txi-edge"; 275 clocks = <&cpg CPG_MOD 0x8f>; 276 clock-names = "fck"; 277 power-domains = <&cpg>; 278 resets = <&cpg 0x95>; 279 status = "disabled"; 280 }; 281 282 i2c0: i2c@14400400 { 283 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 284 reg = <0 0x14400400 0 0x400>; 285 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "tei", "ri", "ti", "spi", "sti", 294 "naki", "ali", "tmoi"; 295 clocks = <&cpg CPG_MOD 0x94>; 296 resets = <&cpg 0x98>; 297 power-domains = <&cpg>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i2c1: i2c@14400800 { 304 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 305 reg = <0 0x14400800 0 0x400>; 306 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "tei", "ri", "ti", "spi", "sti", 315 "naki", "ali", "tmoi"; 316 clocks = <&cpg CPG_MOD 0x95>; 317 resets = <&cpg 0x99>; 318 power-domains = <&cpg>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 }; 323 324 i2c2: i2c@14400c00 { 325 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 326 reg = <0 0x14400c00 0 0x400>; 327 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-names = "tei", "ri", "ti", "spi", "sti", 336 "naki", "ali", "tmoi"; 337 clocks = <&cpg CPG_MOD 0x96>; 338 resets = <&cpg 0x9a>; 339 power-domains = <&cpg>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 i2c3: i2c@14401000 { 346 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 347 reg = <0 0x14401000 0 0x400>; 348 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 356 interrupt-names = "tei", "ri", "ti", "spi", "sti", 357 "naki", "ali", "tmoi"; 358 clocks = <&cpg CPG_MOD 0x97>; 359 resets = <&cpg 0x9b>; 360 power-domains = <&cpg>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 i2c4: i2c@14401400 { 367 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 368 reg = <0 0x14401400 0 0x400>; 369 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 371 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-names = "tei", "ri", "ti", "spi", "sti", 378 "naki", "ali", "tmoi"; 379 clocks = <&cpg CPG_MOD 0x98>; 380 resets = <&cpg 0x9c>; 381 power-domains = <&cpg>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 387 i2c5: i2c@14401800 { 388 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 389 reg = <0 0x14401800 0 0x400>; 390 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "tei", "ri", "ti", "spi", "sti", 399 "naki", "ali", "tmoi"; 400 clocks = <&cpg CPG_MOD 0x99>; 401 resets = <&cpg 0x9d>; 402 power-domains = <&cpg>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 i2c6: i2c@14401c00 { 409 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 410 reg = <0 0x14401c00 0 0x400>; 411 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 419 interrupt-names = "tei", "ri", "ti", "spi", "sti", 420 "naki", "ali", "tmoi"; 421 clocks = <&cpg CPG_MOD 0x9a>; 422 resets = <&cpg 0x9e>; 423 power-domains = <&cpg>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 i2c7: i2c@14402000 { 430 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 431 reg = <0 0x14402000 0 0x400>; 432 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 435 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "tei", "ri", "ti", "spi", "sti", 441 "naki", "ali", "tmoi"; 442 clocks = <&cpg CPG_MOD 0x9b>; 443 resets = <&cpg 0x9f>; 444 power-domains = <&cpg>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 i2c8: i2c@11c01000 { 451 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 452 reg = <0 0x11c01000 0 0x400>; 453 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "tei", "ri", "ti", "spi", "sti", 462 "naki", "ali", "tmoi"; 463 clocks = <&cpg CPG_MOD 0x93>; 464 resets = <&cpg 0xa0>; 465 power-domains = <&cpg>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 status = "disabled"; 469 }; 470 471 gic: interrupt-controller@14900000 { 472 compatible = "arm,gic-v3"; 473 reg = <0x0 0x14900000 0 0x20000>, 474 <0x0 0x14940000 0 0x80000>; 475 #interrupt-cells = <3>; 476 #address-cells = <0>; 477 interrupt-controller; 478 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 479 }; 480 481 sdhi0: mmc@15c00000 { 482 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 483 reg = <0x0 0x15c00000 0 0x10000>; 484 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 487 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 488 clock-names = "core", "clkh", "cd", "aclk"; 489 resets = <&cpg 0xa7>; 490 power-domains = <&cpg>; 491 status = "disabled"; 492 493 sdhi0_vqmmc: vqmmc-regulator { 494 regulator-name = "SDHI0-VQMMC"; 495 regulator-min-microvolt = <1800000>; 496 regulator-max-microvolt = <3300000>; 497 status = "disabled"; 498 }; 499 }; 500 501 sdhi1: mmc@15c10000 { 502 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 503 reg = <0x0 0x15c10000 0 0x10000>; 504 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 507 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 508 clock-names = "core", "clkh", "cd", "aclk"; 509 resets = <&cpg 0xa8>; 510 power-domains = <&cpg>; 511 status = "disabled"; 512 513 sdhi1_vqmmc: vqmmc-regulator { 514 regulator-name = "SDHI1-VQMMC"; 515 regulator-min-microvolt = <1800000>; 516 regulator-max-microvolt = <3300000>; 517 status = "disabled"; 518 }; 519 }; 520 521 sdhi2: mmc@15c20000 { 522 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 523 reg = <0x0 0x15c20000 0 0x10000>; 524 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 527 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 528 clock-names = "core", "clkh", "cd", "aclk"; 529 resets = <&cpg 0xa9>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 533 sdhi2_vqmmc: vqmmc-regulator { 534 regulator-name = "SDHI2-VQMMC"; 535 regulator-min-microvolt = <1800000>; 536 regulator-max-microvolt = <3300000>; 537 status = "disabled"; 538 }; 539 }; 540 541 eth0: ethernet@15c30000 { 542 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 543 "snps,dwmac-5.20"; 544 reg = <0 0x15c30000 0 0x10000>; 545 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 556 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 557 "rx-queue-0", "rx-queue-1", "rx-queue-2", 558 "rx-queue-3", "tx-queue-0", "tx-queue-1", 559 "tx-queue-2", "tx-queue-3"; 560 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 561 <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 562 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 563 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 564 clock-names = "stmmaceth", "pclk", "ptp_ref", 565 "tx", "rx", "tx-180", "rx-180"; 566 resets = <&cpg 0xb0>; 567 power-domains = <&cpg>; 568 snps,multicast-filter-bins = <256>; 569 snps,perfect-filter-entries = <128>; 570 rx-fifo-depth = <8192>; 571 tx-fifo-depth = <8192>; 572 snps,fixed-burst; 573 snps,no-pbl-x8; 574 snps,force_thresh_dma_mode; 575 snps,axi-config = <&stmmac_axi_setup>; 576 snps,mtl-rx-config = <&mtl_rx_setup0>; 577 snps,mtl-tx-config = <&mtl_tx_setup0>; 578 snps,txpbl = <32>; 579 snps,rxpbl = <32>; 580 status = "disabled"; 581 582 mdio0: mdio { 583 compatible = "snps,dwmac-mdio"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 }; 587 588 mtl_rx_setup0: rx-queues-config { 589 snps,rx-queues-to-use = <4>; 590 snps,rx-sched-sp; 591 592 queue0 { 593 snps,dcb-algorithm; 594 snps,priority = <0x1>; 595 snps,map-to-dma-channel = <0>; 596 }; 597 598 queue1 { 599 snps,dcb-algorithm; 600 snps,priority = <0x2>; 601 snps,map-to-dma-channel = <1>; 602 }; 603 604 queue2 { 605 snps,dcb-algorithm; 606 snps,priority = <0x4>; 607 snps,map-to-dma-channel = <2>; 608 }; 609 610 queue3 { 611 snps,dcb-algorithm; 612 snps,priority = <0x8>; 613 snps,map-to-dma-channel = <3>; 614 }; 615 }; 616 617 mtl_tx_setup0: tx-queues-config { 618 snps,tx-queues-to-use = <4>; 619 620 queue0 { 621 snps,dcb-algorithm; 622 snps,priority = <0x1>; 623 }; 624 625 queue1 { 626 snps,dcb-algorithm; 627 snps,priority = <0x2>; 628 }; 629 630 queue2 { 631 snps,dcb-algorithm; 632 snps,priority = <0x4>; 633 }; 634 635 queue3 { 636 snps,dcb-algorithm; 637 snps,priority = <0x8>; 638 }; 639 }; 640 }; 641 642 eth1: ethernet@15c40000 { 643 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 644 "snps,dwmac-5.20"; 645 reg = <0 0x15c40000 0 0x10000>; 646 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 658 "rx-queue-0", "rx-queue-1", "rx-queue-2", 659 "rx-queue-3", "tx-queue-0", "tx-queue-1", 660 "tx-queue-2", "tx-queue-3"; 661 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 662 <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 663 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 664 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 665 clock-names = "stmmaceth", "pclk", "ptp_ref", 666 "tx", "rx", "tx-180", "rx-180"; 667 resets = <&cpg 0xb1>; 668 power-domains = <&cpg>; 669 snps,multicast-filter-bins = <256>; 670 snps,perfect-filter-entries = <128>; 671 rx-fifo-depth = <8192>; 672 tx-fifo-depth = <8192>; 673 snps,fixed-burst; 674 snps,no-pbl-x8; 675 snps,force_thresh_dma_mode; 676 snps,axi-config = <&stmmac_axi_setup>; 677 snps,mtl-rx-config = <&mtl_rx_setup1>; 678 snps,mtl-tx-config = <&mtl_tx_setup1>; 679 snps,txpbl = <32>; 680 snps,rxpbl = <32>; 681 status = "disabled"; 682 683 mdio1: mdio { 684 compatible = "snps,dwmac-mdio"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 }; 688 689 mtl_rx_setup1: rx-queues-config { 690 snps,rx-queues-to-use = <4>; 691 snps,rx-sched-sp; 692 693 queue0 { 694 snps,dcb-algorithm; 695 snps,priority = <0x1>; 696 snps,map-to-dma-channel = <0>; 697 }; 698 699 queue1 { 700 snps,dcb-algorithm; 701 snps,priority = <0x2>; 702 snps,map-to-dma-channel = <1>; 703 }; 704 705 queue2 { 706 snps,dcb-algorithm; 707 snps,priority = <0x4>; 708 snps,map-to-dma-channel = <2>; 709 }; 710 711 queue3 { 712 snps,dcb-algorithm; 713 snps,priority = <0x8>; 714 snps,map-to-dma-channel = <3>; 715 }; 716 }; 717 718 mtl_tx_setup1: tx-queues-config { 719 snps,tx-queues-to-use = <4>; 720 721 queue0 { 722 snps,dcb-algorithm; 723 snps,priority = <0x1>; 724 }; 725 726 queue1 { 727 snps,dcb-algorithm; 728 snps,priority = <0x2>; 729 }; 730 731 queue2 { 732 snps,dcb-algorithm; 733 snps,priority = <0x4>; 734 }; 735 736 queue3 { 737 snps,dcb-algorithm; 738 snps,priority = <0x8>; 739 }; 740 }; 741 }; 742 }; 743 744 stmmac_axi_setup: stmmac-axi-config { 745 snps,lpi_en; 746 snps,wr_osr_lmt = <0xf>; 747 snps,rd_osr_lmt = <0xf>; 748 snps,blen = <16 8 4 0 0 0 0>; 749 }; 750 751 timer { 752 compatible = "arm,armv8-timer"; 753 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 754 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 755 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 756 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 757 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 758 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 759 }; 760}; 761