1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 audio_extal_clk: audio-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 /* This value must be overridden by the board */ 38 clock-frequency = <0>; 39 }; 40 41 /* 42 * The default cluster table is based on the assumption that the PLLCA55 clock 43 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 44 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 45 * clocked to 1.8GHz as well). The table below should be overridden in the board 46 * DTS based on the PLLCA55 clock frequency. 47 */ 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 51 opp-1700000000 { 52 opp-hz = /bits/ 64 <1700000000>; 53 opp-microvolt = <900000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-850000000 { 57 opp-hz = /bits/ 64 <850000000>; 58 opp-microvolt = <800000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-425000000 { 62 opp-hz = /bits/ 64 <425000000>; 63 opp-microvolt = <800000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-212500000 { 67 opp-hz = /bits/ 64 <212500000>; 68 opp-microvolt = <800000>; 69 clock-latency-ns = <300000>; 70 opp-suspend; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a55"; 80 reg = <0>; 81 device_type = "cpu"; 82 next-level-cache = <&L3_CA55>; 83 enable-method = "psci"; 84 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 85 operating-points-v2 = <&cluster0_opp>; 86 }; 87 88 cpu1: cpu@100 { 89 compatible = "arm,cortex-a55"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu2: cpu@200 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x200>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 115 operating-points-v2 = <&cluster0_opp>; 116 }; 117 118 L3_CA55: cache-controller-0 { 119 compatible = "cache"; 120 cache-unified; 121 cache-size = <0x100000>; 122 cache-level = <3>; 123 }; 124 }; 125 126 gpu_opp_table: opp-table-1 { 127 compatible = "operating-points-v2"; 128 129 opp-630000000 { 130 opp-hz = /bits/ 64 <630000000>; 131 opp-microvolt = <800000>; 132 }; 133 134 opp-315000000 { 135 opp-hz = /bits/ 64 <315000000>; 136 opp-microvolt = <800000>; 137 }; 138 139 opp-157500000 { 140 opp-hz = /bits/ 64 <157500000>; 141 opp-microvolt = <800000>; 142 }; 143 144 opp-78750000 { 145 opp-hz = /bits/ 64 <78750000>; 146 opp-microvolt = <800000>; 147 }; 148 149 opp-19687500 { 150 opp-hz = /bits/ 64 <19687500>; 151 opp-microvolt = <800000>; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0", "arm,psci-0.2"; 157 method = "smc"; 158 }; 159 160 qextal_clk: qextal-clk { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 /* This value must be overridden by the board */ 164 clock-frequency = <0>; 165 }; 166 167 rtxin_clk: rtxin-clk { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 /* This value must be overridden by the board */ 171 clock-frequency = <0>; 172 }; 173 174 soc: soc { 175 compatible = "simple-bus"; 176 interrupt-parent = <&gic>; 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 pinctrl: pinctrl@10410000 { 182 compatible = "renesas,r9a09g056-pinctrl"; 183 reg = <0 0x10410000 0 0x10000>; 184 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 185 gpio-controller; 186 #gpio-cells = <2>; 187 gpio-ranges = <&pinctrl 0 0 96>; 188 power-domains = <&cpg>; 189 resets = <&cpg 0xa5>, <&cpg 0xa6>; 190 }; 191 192 cpg: clock-controller@10420000 { 193 compatible = "renesas,r9a09g056-cpg"; 194 reg = <0 0x10420000 0 0x10000>; 195 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 196 clock-names = "audio_extal", "rtxin", "qextal"; 197 #clock-cells = <2>; 198 #reset-cells = <1>; 199 #power-domain-cells = <0>; 200 }; 201 202 sys: system-controller@10430000 { 203 compatible = "renesas,r9a09g056-sys"; 204 reg = <0 0x10430000 0 0x10000>; 205 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 206 resets = <&cpg 0x30>; 207 }; 208 209 xspi: spi@11030000 { 210 compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; 211 reg = <0 0x11030000 0 0x10000>, 212 <0 0x20000000 0 0x10000000>; 213 reg-names = "regs", "dirmap"; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 216 interrupt-names = "pulse", "err_pulse"; 217 clocks = <&cpg CPG_MOD 0x9f>, 218 <&cpg CPG_MOD 0xa0>, 219 <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>, 220 <&cpg CPG_MOD 0xa1>; 221 clock-names = "ahb", "axi", "spi", "spix2"; 222 resets = <&cpg 0xa3>, <&cpg 0xa4>; 223 reset-names = "hresetn", "aresetn"; 224 power-domains = <&cpg>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "disabled"; 228 }; 229 230 ostm0: timer@11800000 { 231 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 232 reg = <0x0 0x11800000 0x0 0x1000>; 233 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 234 clocks = <&cpg CPG_MOD 0x43>; 235 resets = <&cpg 0x6d>; 236 power-domains = <&cpg>; 237 status = "disabled"; 238 }; 239 240 ostm1: timer@11801000 { 241 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 242 reg = <0x0 0x11801000 0x0 0x1000>; 243 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 244 clocks = <&cpg CPG_MOD 0x44>; 245 resets = <&cpg 0x6e>; 246 power-domains = <&cpg>; 247 status = "disabled"; 248 }; 249 250 ostm2: timer@14000000 { 251 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 252 reg = <0x0 0x14000000 0x0 0x1000>; 253 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 254 clocks = <&cpg CPG_MOD 0x45>; 255 resets = <&cpg 0x6f>; 256 power-domains = <&cpg>; 257 status = "disabled"; 258 }; 259 260 ostm3: timer@14001000 { 261 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 262 reg = <0x0 0x14001000 0x0 0x1000>; 263 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 264 clocks = <&cpg CPG_MOD 0x46>; 265 resets = <&cpg 0x70>; 266 power-domains = <&cpg>; 267 status = "disabled"; 268 }; 269 270 ostm4: timer@12c00000 { 271 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 272 reg = <0x0 0x12c00000 0x0 0x1000>; 273 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 274 clocks = <&cpg CPG_MOD 0x47>; 275 resets = <&cpg 0x71>; 276 power-domains = <&cpg>; 277 status = "disabled"; 278 }; 279 280 ostm5: timer@12c01000 { 281 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 282 reg = <0x0 0x12c01000 0x0 0x1000>; 283 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 284 clocks = <&cpg CPG_MOD 0x48>; 285 resets = <&cpg 0x72>; 286 power-domains = <&cpg>; 287 status = "disabled"; 288 }; 289 290 ostm6: timer@12c02000 { 291 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 292 reg = <0x0 0x12c02000 0x0 0x1000>; 293 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 294 clocks = <&cpg CPG_MOD 0x49>; 295 resets = <&cpg 0x73>; 296 power-domains = <&cpg>; 297 status = "disabled"; 298 }; 299 300 ostm7: timer@12c03000 { 301 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 302 reg = <0x0 0x12c03000 0x0 0x1000>; 303 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 304 clocks = <&cpg CPG_MOD 0x4a>; 305 resets = <&cpg 0x74>; 306 power-domains = <&cpg>; 307 status = "disabled"; 308 }; 309 310 wdt0: watchdog@11c00400 { 311 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 312 reg = <0 0x11c00400 0 0x400>; 313 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 314 clock-names = "pclk", "oscclk"; 315 resets = <&cpg 0x75>; 316 power-domains = <&cpg>; 317 status = "disabled"; 318 }; 319 320 wdt1: watchdog@14400000 { 321 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 322 reg = <0 0x14400000 0 0x400>; 323 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 324 clock-names = "pclk", "oscclk"; 325 resets = <&cpg 0x76>; 326 power-domains = <&cpg>; 327 status = "disabled"; 328 }; 329 330 wdt2: watchdog@13000000 { 331 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 332 reg = <0 0x13000000 0 0x400>; 333 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 334 clock-names = "pclk", "oscclk"; 335 resets = <&cpg 0x77>; 336 power-domains = <&cpg>; 337 status = "disabled"; 338 }; 339 340 wdt3: watchdog@13000400 { 341 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 342 reg = <0 0x13000400 0 0x400>; 343 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 344 clock-names = "pclk", "oscclk"; 345 resets = <&cpg 0x78>; 346 power-domains = <&cpg>; 347 status = "disabled"; 348 }; 349 350 scif: serial@11c01400 { 351 compatible = "renesas,scif-r9a09g056", 352 "renesas,scif-r9a09g057"; 353 reg = <0 0x11c01400 0 0x400>; 354 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 363 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 364 "tei", "tei-dri", "rxi-edge", "txi-edge"; 365 clocks = <&cpg CPG_MOD 0x8f>; 366 clock-names = "fck"; 367 power-domains = <&cpg>; 368 resets = <&cpg 0x95>; 369 status = "disabled"; 370 }; 371 372 i2c0: i2c@14400400 { 373 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 374 reg = <0 0x14400400 0 0x400>; 375 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 383 interrupt-names = "tei", "ri", "ti", "spi", "sti", 384 "naki", "ali", "tmoi"; 385 clocks = <&cpg CPG_MOD 0x94>; 386 resets = <&cpg 0x98>; 387 power-domains = <&cpg>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 i2c1: i2c@14400800 { 394 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 395 reg = <0 0x14400800 0 0x400>; 396 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 399 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 404 interrupt-names = "tei", "ri", "ti", "spi", "sti", 405 "naki", "ali", "tmoi"; 406 clocks = <&cpg CPG_MOD 0x95>; 407 resets = <&cpg 0x99>; 408 power-domains = <&cpg>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c2: i2c@14400c00 { 415 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 416 reg = <0 0x14400c00 0 0x400>; 417 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "tei", "ri", "ti", "spi", "sti", 426 "naki", "ali", "tmoi"; 427 clocks = <&cpg CPG_MOD 0x96>; 428 resets = <&cpg 0x9a>; 429 power-domains = <&cpg>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 435 i2c3: i2c@14401000 { 436 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 437 reg = <0 0x14401000 0 0x400>; 438 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 440 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "tei", "ri", "ti", "spi", "sti", 447 "naki", "ali", "tmoi"; 448 clocks = <&cpg CPG_MOD 0x97>; 449 resets = <&cpg 0x9b>; 450 power-domains = <&cpg>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 status = "disabled"; 454 }; 455 456 i2c4: i2c@14401400 { 457 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 458 reg = <0 0x14401400 0 0x400>; 459 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 461 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "tei", "ri", "ti", "spi", "sti", 468 "naki", "ali", "tmoi"; 469 clocks = <&cpg CPG_MOD 0x98>; 470 resets = <&cpg 0x9c>; 471 power-domains = <&cpg>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 i2c5: i2c@14401800 { 478 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 479 reg = <0 0x14401800 0 0x400>; 480 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-names = "tei", "ri", "ti", "spi", "sti", 489 "naki", "ali", "tmoi"; 490 clocks = <&cpg CPG_MOD 0x99>; 491 resets = <&cpg 0x9d>; 492 power-domains = <&cpg>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 i2c6: i2c@14401c00 { 499 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 500 reg = <0 0x14401c00 0 0x400>; 501 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 503 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 504 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 509 interrupt-names = "tei", "ri", "ti", "spi", "sti", 510 "naki", "ali", "tmoi"; 511 clocks = <&cpg CPG_MOD 0x9a>; 512 resets = <&cpg 0x9e>; 513 power-domains = <&cpg>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 i2c7: i2c@14402000 { 520 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 521 reg = <0 0x14402000 0 0x400>; 522 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 524 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "tei", "ri", "ti", "spi", "sti", 531 "naki", "ali", "tmoi"; 532 clocks = <&cpg CPG_MOD 0x9b>; 533 resets = <&cpg 0x9f>; 534 power-domains = <&cpg>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 i2c8: i2c@11c01000 { 541 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 542 reg = <0 0x11c01000 0 0x400>; 543 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "tei", "ri", "ti", "spi", "sti", 552 "naki", "ali", "tmoi"; 553 clocks = <&cpg CPG_MOD 0x93>; 554 resets = <&cpg 0xa0>; 555 power-domains = <&cpg>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 gpu: gpu@14850000 { 562 compatible = "renesas,r9a09g056-mali", 563 "arm,mali-bifrost"; 564 reg = <0x0 0x14850000 0x0 0x10000>; 565 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "job", "mmu", "gpu", "event"; 570 clocks = <&cpg CPG_MOD 0xf0>, 571 <&cpg CPG_MOD 0xf1>, 572 <&cpg CPG_MOD 0xf2>; 573 clock-names = "gpu", "bus", "bus_ace"; 574 resets = <&cpg 0xdd>, 575 <&cpg 0xde>, 576 <&cpg 0xdf>; 577 reset-names = "rst", "axi_rst", "ace_rst"; 578 power-domains = <&cpg>; 579 operating-points-v2 = <&gpu_opp_table>; 580 status = "disabled"; 581 }; 582 583 gic: interrupt-controller@14900000 { 584 compatible = "arm,gic-v3"; 585 reg = <0x0 0x14900000 0 0x20000>, 586 <0x0 0x14940000 0 0x80000>; 587 #interrupt-cells = <3>; 588 #address-cells = <0>; 589 interrupt-controller; 590 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 591 }; 592 593 ohci0: usb@15800000 { 594 compatible = "generic-ohci"; 595 reg = <0 0x15800000 0 0x100>; 596 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 598 resets = <&usb20phyrst>, <&cpg 0xac>; 599 phys = <&usb2_phy0 1>; 600 phy-names = "usb"; 601 power-domains = <&cpg>; 602 status = "disabled"; 603 }; 604 605 ehci0: usb@15800100 { 606 compatible = "generic-ehci"; 607 reg = <0 0x15800100 0 0x100>; 608 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 610 resets = <&usb20phyrst>, <&cpg 0xac>; 611 phys = <&usb2_phy0 2>; 612 phy-names = "usb"; 613 companion = <&ohci0>; 614 power-domains = <&cpg>; 615 status = "disabled"; 616 }; 617 618 usb2_phy0: usb-phy@15800200 { 619 compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057"; 620 reg = <0 0x15800200 0 0x700>; 621 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cpg CPG_MOD 0xb3>, 623 <&cpg CPG_CORE R9A09G056_USB2_0_CLK_CORE0>; 624 clock-names = "fck", "usb_x1"; 625 resets = <&usb20phyrst>; 626 #phy-cells = <1>; 627 power-domains = <&cpg>; 628 status = "disabled"; 629 }; 630 631 hsusb: usb@15820000 { 632 compatible = "renesas,usbhs-r9a09g056", 633 "renesas,rzg2l-usbhs"; 634 reg = <0 0x15820000 0 0x10000>; 635 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 636 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 640 resets = <&usb20phyrst>, 641 <&cpg 0xae>; 642 phys = <&usb2_phy0 3>; 643 phy-names = "usb"; 644 power-domains = <&cpg>; 645 status = "disabled"; 646 }; 647 648 usb20phyrst: usb20phy-reset@15830000 { 649 compatible = "renesas,r9a09g056-usb2phy-reset", 650 "renesas,r9a09g057-usb2phy-reset"; 651 reg = <0 0x15830000 0 0x10000>; 652 clocks = <&cpg CPG_MOD 0xb6>; 653 resets = <&cpg 0xaf>; 654 power-domains = <&cpg>; 655 #reset-cells = <0>; 656 status = "disabled"; 657 }; 658 659 sdhi0: mmc@15c00000 { 660 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 661 reg = <0x0 0x15c00000 0 0x10000>; 662 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 665 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 666 clock-names = "core", "clkh", "cd", "aclk"; 667 resets = <&cpg 0xa7>; 668 power-domains = <&cpg>; 669 status = "disabled"; 670 671 sdhi0_vqmmc: vqmmc-regulator { 672 regulator-name = "SDHI0-VQMMC"; 673 regulator-min-microvolt = <1800000>; 674 regulator-max-microvolt = <3300000>; 675 status = "disabled"; 676 }; 677 }; 678 679 sdhi1: mmc@15c10000 { 680 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 681 reg = <0x0 0x15c10000 0 0x10000>; 682 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 685 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 686 clock-names = "core", "clkh", "cd", "aclk"; 687 resets = <&cpg 0xa8>; 688 power-domains = <&cpg>; 689 status = "disabled"; 690 691 sdhi1_vqmmc: vqmmc-regulator { 692 regulator-name = "SDHI1-VQMMC"; 693 regulator-min-microvolt = <1800000>; 694 regulator-max-microvolt = <3300000>; 695 status = "disabled"; 696 }; 697 }; 698 699 sdhi2: mmc@15c20000 { 700 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 701 reg = <0x0 0x15c20000 0 0x10000>; 702 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 705 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 706 clock-names = "core", "clkh", "cd", "aclk"; 707 resets = <&cpg 0xa9>; 708 power-domains = <&cpg>; 709 status = "disabled"; 710 711 sdhi2_vqmmc: vqmmc-regulator { 712 regulator-name = "SDHI2-VQMMC"; 713 regulator-min-microvolt = <1800000>; 714 regulator-max-microvolt = <3300000>; 715 status = "disabled"; 716 }; 717 }; 718 719 eth0: ethernet@15c30000 { 720 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 721 "snps,dwmac-5.20"; 722 reg = <0 0x15c30000 0 0x10000>; 723 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 734 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 735 "rx-queue-0", "rx-queue-1", "rx-queue-2", 736 "rx-queue-3", "tx-queue-0", "tx-queue-1", 737 "tx-queue-2", "tx-queue-3"; 738 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 739 <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 740 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 741 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 742 clock-names = "stmmaceth", "pclk", "ptp_ref", 743 "tx", "rx", "tx-180", "rx-180"; 744 resets = <&cpg 0xb0>; 745 power-domains = <&cpg>; 746 snps,multicast-filter-bins = <256>; 747 snps,perfect-filter-entries = <128>; 748 rx-fifo-depth = <8192>; 749 tx-fifo-depth = <8192>; 750 snps,fixed-burst; 751 snps,no-pbl-x8; 752 snps,force_thresh_dma_mode; 753 snps,axi-config = <&stmmac_axi_setup>; 754 snps,mtl-rx-config = <&mtl_rx_setup0>; 755 snps,mtl-tx-config = <&mtl_tx_setup0>; 756 snps,txpbl = <32>; 757 snps,rxpbl = <32>; 758 status = "disabled"; 759 760 mdio0: mdio { 761 compatible = "snps,dwmac-mdio"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 }; 765 766 mtl_rx_setup0: rx-queues-config { 767 snps,rx-queues-to-use = <4>; 768 snps,rx-sched-sp; 769 770 queue0 { 771 snps,dcb-algorithm; 772 snps,priority = <0x1>; 773 snps,map-to-dma-channel = <0>; 774 }; 775 776 queue1 { 777 snps,dcb-algorithm; 778 snps,priority = <0x2>; 779 snps,map-to-dma-channel = <1>; 780 }; 781 782 queue2 { 783 snps,dcb-algorithm; 784 snps,priority = <0x4>; 785 snps,map-to-dma-channel = <2>; 786 }; 787 788 queue3 { 789 snps,dcb-algorithm; 790 snps,priority = <0x8>; 791 snps,map-to-dma-channel = <3>; 792 }; 793 }; 794 795 mtl_tx_setup0: tx-queues-config { 796 snps,tx-queues-to-use = <4>; 797 798 queue0 { 799 snps,dcb-algorithm; 800 snps,priority = <0x1>; 801 }; 802 803 queue1 { 804 snps,dcb-algorithm; 805 snps,priority = <0x2>; 806 }; 807 808 queue2 { 809 snps,dcb-algorithm; 810 snps,priority = <0x4>; 811 }; 812 813 queue3 { 814 snps,dcb-algorithm; 815 snps,priority = <0x8>; 816 }; 817 }; 818 }; 819 820 eth1: ethernet@15c40000 { 821 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 822 "snps,dwmac-5.20"; 823 reg = <0 0x15c40000 0 0x10000>; 824 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 836 "rx-queue-0", "rx-queue-1", "rx-queue-2", 837 "rx-queue-3", "tx-queue-0", "tx-queue-1", 838 "tx-queue-2", "tx-queue-3"; 839 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 840 <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 841 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 842 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 843 clock-names = "stmmaceth", "pclk", "ptp_ref", 844 "tx", "rx", "tx-180", "rx-180"; 845 resets = <&cpg 0xb1>; 846 power-domains = <&cpg>; 847 snps,multicast-filter-bins = <256>; 848 snps,perfect-filter-entries = <128>; 849 rx-fifo-depth = <8192>; 850 tx-fifo-depth = <8192>; 851 snps,fixed-burst; 852 snps,no-pbl-x8; 853 snps,force_thresh_dma_mode; 854 snps,axi-config = <&stmmac_axi_setup>; 855 snps,mtl-rx-config = <&mtl_rx_setup1>; 856 snps,mtl-tx-config = <&mtl_tx_setup1>; 857 snps,txpbl = <32>; 858 snps,rxpbl = <32>; 859 status = "disabled"; 860 861 mdio1: mdio { 862 compatible = "snps,dwmac-mdio"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 }; 866 867 mtl_rx_setup1: rx-queues-config { 868 snps,rx-queues-to-use = <4>; 869 snps,rx-sched-sp; 870 871 queue0 { 872 snps,dcb-algorithm; 873 snps,priority = <0x1>; 874 snps,map-to-dma-channel = <0>; 875 }; 876 877 queue1 { 878 snps,dcb-algorithm; 879 snps,priority = <0x2>; 880 snps,map-to-dma-channel = <1>; 881 }; 882 883 queue2 { 884 snps,dcb-algorithm; 885 snps,priority = <0x4>; 886 snps,map-to-dma-channel = <2>; 887 }; 888 889 queue3 { 890 snps,dcb-algorithm; 891 snps,priority = <0x8>; 892 snps,map-to-dma-channel = <3>; 893 }; 894 }; 895 896 mtl_tx_setup1: tx-queues-config { 897 snps,tx-queues-to-use = <4>; 898 899 queue0 { 900 snps,dcb-algorithm; 901 snps,priority = <0x1>; 902 }; 903 904 queue1 { 905 snps,dcb-algorithm; 906 snps,priority = <0x2>; 907 }; 908 909 queue2 { 910 snps,dcb-algorithm; 911 snps,priority = <0x4>; 912 }; 913 914 queue3 { 915 snps,dcb-algorithm; 916 snps,priority = <0x8>; 917 }; 918 }; 919 }; 920 }; 921 922 stmmac_axi_setup: stmmac-axi-config { 923 snps,lpi_en; 924 snps,wr_osr_lmt = <0xf>; 925 snps,rd_osr_lmt = <0xf>; 926 snps,blen = <16 8 4 0 0 0 0>; 927 }; 928 929 timer { 930 compatible = "arm,armv8-timer"; 931 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 932 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 933 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 934 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 935 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 936 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 937 }; 938}; 939