1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 audio_extal_clk: audio-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 /* This value must be overridden by the board */ 38 clock-frequency = <0>; 39 }; 40 41 /* 42 * The default cluster table is based on the assumption that the PLLCA55 clock 43 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 44 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 45 * clocked to 1.8GHz as well). The table below should be overridden in the board 46 * DTS based on the PLLCA55 clock frequency. 47 */ 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 51 opp-1700000000 { 52 opp-hz = /bits/ 64 <1700000000>; 53 opp-microvolt = <900000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-850000000 { 57 opp-hz = /bits/ 64 <850000000>; 58 opp-microvolt = <800000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-425000000 { 62 opp-hz = /bits/ 64 <425000000>; 63 opp-microvolt = <800000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-212500000 { 67 opp-hz = /bits/ 64 <212500000>; 68 opp-microvolt = <800000>; 69 clock-latency-ns = <300000>; 70 opp-suspend; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a55"; 80 reg = <0>; 81 device_type = "cpu"; 82 next-level-cache = <&L3_CA55>; 83 enable-method = "psci"; 84 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 85 operating-points-v2 = <&cluster0_opp>; 86 }; 87 88 cpu1: cpu@100 { 89 compatible = "arm,cortex-a55"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu2: cpu@200 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x200>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 115 operating-points-v2 = <&cluster0_opp>; 116 }; 117 118 L3_CA55: cache-controller-0 { 119 compatible = "cache"; 120 cache-unified; 121 cache-size = <0x100000>; 122 cache-level = <3>; 123 }; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0", "arm,psci-0.2"; 128 method = "smc"; 129 }; 130 131 qextal_clk: qextal-clk { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 /* This value must be overridden by the board */ 135 clock-frequency = <0>; 136 }; 137 138 rtxin_clk: rtxin-clk { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 /* This value must be overridden by the board */ 142 clock-frequency = <0>; 143 }; 144 145 soc: soc { 146 compatible = "simple-bus"; 147 interrupt-parent = <&gic>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 pinctrl: pinctrl@10410000 { 153 compatible = "renesas,r9a09g056-pinctrl"; 154 reg = <0 0x10410000 0 0x10000>; 155 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 gpio-ranges = <&pinctrl 0 0 96>; 159 power-domains = <&cpg>; 160 resets = <&cpg 0xa5>, <&cpg 0xa6>; 161 }; 162 163 cpg: clock-controller@10420000 { 164 compatible = "renesas,r9a09g056-cpg"; 165 reg = <0 0x10420000 0 0x10000>; 166 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 167 clock-names = "audio_extal", "rtxin", "qextal"; 168 #clock-cells = <2>; 169 #reset-cells = <1>; 170 #power-domain-cells = <0>; 171 }; 172 173 sys: system-controller@10430000 { 174 compatible = "renesas,r9a09g056-sys"; 175 reg = <0 0x10430000 0 0x10000>; 176 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 177 resets = <&cpg 0x30>; 178 }; 179 180 ostm0: timer@11800000 { 181 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 182 reg = <0x0 0x11800000 0x0 0x1000>; 183 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 184 clocks = <&cpg CPG_MOD 0x43>; 185 resets = <&cpg 0x6d>; 186 power-domains = <&cpg>; 187 status = "disabled"; 188 }; 189 190 ostm1: timer@11801000 { 191 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 192 reg = <0x0 0x11801000 0x0 0x1000>; 193 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 194 clocks = <&cpg CPG_MOD 0x44>; 195 resets = <&cpg 0x6e>; 196 power-domains = <&cpg>; 197 status = "disabled"; 198 }; 199 200 ostm2: timer@14000000 { 201 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 202 reg = <0x0 0x14000000 0x0 0x1000>; 203 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 204 clocks = <&cpg CPG_MOD 0x45>; 205 resets = <&cpg 0x6f>; 206 power-domains = <&cpg>; 207 status = "disabled"; 208 }; 209 210 ostm3: timer@14001000 { 211 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 212 reg = <0x0 0x14001000 0x0 0x1000>; 213 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 214 clocks = <&cpg CPG_MOD 0x46>; 215 resets = <&cpg 0x70>; 216 power-domains = <&cpg>; 217 status = "disabled"; 218 }; 219 220 ostm4: timer@12c00000 { 221 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 222 reg = <0x0 0x12c00000 0x0 0x1000>; 223 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 224 clocks = <&cpg CPG_MOD 0x47>; 225 resets = <&cpg 0x71>; 226 power-domains = <&cpg>; 227 status = "disabled"; 228 }; 229 230 ostm5: timer@12c01000 { 231 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 232 reg = <0x0 0x12c01000 0x0 0x1000>; 233 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 234 clocks = <&cpg CPG_MOD 0x48>; 235 resets = <&cpg 0x72>; 236 power-domains = <&cpg>; 237 status = "disabled"; 238 }; 239 240 ostm6: timer@12c02000 { 241 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 242 reg = <0x0 0x12c02000 0x0 0x1000>; 243 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 244 clocks = <&cpg CPG_MOD 0x49>; 245 resets = <&cpg 0x73>; 246 power-domains = <&cpg>; 247 status = "disabled"; 248 }; 249 250 ostm7: timer@12c03000 { 251 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 252 reg = <0x0 0x12c03000 0x0 0x1000>; 253 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 254 clocks = <&cpg CPG_MOD 0x4a>; 255 resets = <&cpg 0x74>; 256 power-domains = <&cpg>; 257 status = "disabled"; 258 }; 259 260 scif: serial@11c01400 { 261 compatible = "renesas,scif-r9a09g056", 262 "renesas,scif-r9a09g057"; 263 reg = <0 0x11c01400 0 0x400>; 264 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 273 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 274 "tei", "tei-dri", "rxi-edge", "txi-edge"; 275 clocks = <&cpg CPG_MOD 0x8f>; 276 clock-names = "fck"; 277 power-domains = <&cpg>; 278 resets = <&cpg 0x95>; 279 status = "disabled"; 280 }; 281 282 gic: interrupt-controller@14900000 { 283 compatible = "arm,gic-v3"; 284 reg = <0x0 0x14900000 0 0x20000>, 285 <0x0 0x14940000 0 0x80000>; 286 #interrupt-cells = <3>; 287 #address-cells = <0>; 288 interrupt-controller; 289 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 290 }; 291 292 sdhi0: mmc@15c00000 { 293 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 294 reg = <0x0 0x15c00000 0 0x10000>; 295 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 298 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 299 clock-names = "core", "clkh", "cd", "aclk"; 300 resets = <&cpg 0xa7>; 301 power-domains = <&cpg>; 302 status = "disabled"; 303 304 sdhi0_vqmmc: vqmmc-regulator { 305 regulator-name = "SDHI0-VQMMC"; 306 regulator-min-microvolt = <1800000>; 307 regulator-max-microvolt = <3300000>; 308 status = "disabled"; 309 }; 310 }; 311 312 sdhi1: mmc@15c10000 { 313 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 314 reg = <0x0 0x15c10000 0 0x10000>; 315 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 318 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 319 clock-names = "core", "clkh", "cd", "aclk"; 320 resets = <&cpg 0xa8>; 321 power-domains = <&cpg>; 322 status = "disabled"; 323 324 sdhi1_vqmmc: vqmmc-regulator { 325 regulator-name = "SDHI1-VQMMC"; 326 regulator-min-microvolt = <1800000>; 327 regulator-max-microvolt = <3300000>; 328 status = "disabled"; 329 }; 330 }; 331 332 sdhi2: mmc@15c20000 { 333 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 334 reg = <0x0 0x15c20000 0 0x10000>; 335 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 338 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 339 clock-names = "core", "clkh", "cd", "aclk"; 340 resets = <&cpg 0xa9>; 341 power-domains = <&cpg>; 342 status = "disabled"; 343 344 sdhi2_vqmmc: vqmmc-regulator { 345 regulator-name = "SDHI2-VQMMC"; 346 regulator-min-microvolt = <1800000>; 347 regulator-max-microvolt = <3300000>; 348 status = "disabled"; 349 }; 350 }; 351 352 eth0: ethernet@15c30000 { 353 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 354 "snps,dwmac-5.20"; 355 reg = <0 0x15c30000 0 0x10000>; 356 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 367 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 368 "rx-queue-0", "rx-queue-1", "rx-queue-2", 369 "rx-queue-3", "tx-queue-0", "tx-queue-1", 370 "tx-queue-2", "tx-queue-3"; 371 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 372 <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 373 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 374 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 375 clock-names = "stmmaceth", "pclk", "ptp_ref", 376 "tx", "rx", "tx-180", "rx-180"; 377 resets = <&cpg 0xb0>; 378 power-domains = <&cpg>; 379 snps,multicast-filter-bins = <256>; 380 snps,perfect-filter-entries = <128>; 381 rx-fifo-depth = <8192>; 382 tx-fifo-depth = <8192>; 383 snps,fixed-burst; 384 snps,no-pbl-x8; 385 snps,force_thresh_dma_mode; 386 snps,axi-config = <&stmmac_axi_setup>; 387 snps,mtl-rx-config = <&mtl_rx_setup0>; 388 snps,mtl-tx-config = <&mtl_tx_setup0>; 389 snps,txpbl = <32>; 390 snps,rxpbl = <32>; 391 status = "disabled"; 392 393 mdio0: mdio { 394 compatible = "snps,dwmac-mdio"; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 }; 398 399 mtl_rx_setup0: rx-queues-config { 400 snps,rx-queues-to-use = <4>; 401 snps,rx-sched-sp; 402 403 queue0 { 404 snps,dcb-algorithm; 405 snps,priority = <0x1>; 406 snps,map-to-dma-channel = <0>; 407 }; 408 409 queue1 { 410 snps,dcb-algorithm; 411 snps,priority = <0x2>; 412 snps,map-to-dma-channel = <1>; 413 }; 414 415 queue2 { 416 snps,dcb-algorithm; 417 snps,priority = <0x4>; 418 snps,map-to-dma-channel = <2>; 419 }; 420 421 queue3 { 422 snps,dcb-algorithm; 423 snps,priority = <0x8>; 424 snps,map-to-dma-channel = <3>; 425 }; 426 }; 427 428 mtl_tx_setup0: tx-queues-config { 429 snps,tx-queues-to-use = <4>; 430 431 queue0 { 432 snps,dcb-algorithm; 433 snps,priority = <0x1>; 434 }; 435 436 queue1 { 437 snps,dcb-algorithm; 438 snps,priority = <0x2>; 439 }; 440 441 queue2 { 442 snps,dcb-algorithm; 443 snps,priority = <0x4>; 444 }; 445 446 queue3 { 447 snps,dcb-algorithm; 448 snps,priority = <0x8>; 449 }; 450 }; 451 }; 452 453 eth1: ethernet@15c40000 { 454 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 455 "snps,dwmac-5.20"; 456 reg = <0 0x15c40000 0 0x10000>; 457 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 469 "rx-queue-0", "rx-queue-1", "rx-queue-2", 470 "rx-queue-3", "tx-queue-0", "tx-queue-1", 471 "tx-queue-2", "tx-queue-3"; 472 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 473 <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 474 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 475 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 476 clock-names = "stmmaceth", "pclk", "ptp_ref", 477 "tx", "rx", "tx-180", "rx-180"; 478 resets = <&cpg 0xb1>; 479 power-domains = <&cpg>; 480 snps,multicast-filter-bins = <256>; 481 snps,perfect-filter-entries = <128>; 482 rx-fifo-depth = <8192>; 483 tx-fifo-depth = <8192>; 484 snps,fixed-burst; 485 snps,no-pbl-x8; 486 snps,force_thresh_dma_mode; 487 snps,axi-config = <&stmmac_axi_setup>; 488 snps,mtl-rx-config = <&mtl_rx_setup1>; 489 snps,mtl-tx-config = <&mtl_tx_setup1>; 490 snps,txpbl = <32>; 491 snps,rxpbl = <32>; 492 status = "disabled"; 493 494 mdio1: mdio { 495 compatible = "snps,dwmac-mdio"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 }; 499 500 mtl_rx_setup1: rx-queues-config { 501 snps,rx-queues-to-use = <4>; 502 snps,rx-sched-sp; 503 504 queue0 { 505 snps,dcb-algorithm; 506 snps,priority = <0x1>; 507 snps,map-to-dma-channel = <0>; 508 }; 509 510 queue1 { 511 snps,dcb-algorithm; 512 snps,priority = <0x2>; 513 snps,map-to-dma-channel = <1>; 514 }; 515 516 queue2 { 517 snps,dcb-algorithm; 518 snps,priority = <0x4>; 519 snps,map-to-dma-channel = <2>; 520 }; 521 522 queue3 { 523 snps,dcb-algorithm; 524 snps,priority = <0x8>; 525 snps,map-to-dma-channel = <3>; 526 }; 527 }; 528 529 mtl_tx_setup1: tx-queues-config { 530 snps,tx-queues-to-use = <4>; 531 532 queue0 { 533 snps,dcb-algorithm; 534 snps,priority = <0x1>; 535 }; 536 537 queue1 { 538 snps,dcb-algorithm; 539 snps,priority = <0x2>; 540 }; 541 542 queue2 { 543 snps,dcb-algorithm; 544 snps,priority = <0x4>; 545 }; 546 547 queue3 { 548 snps,dcb-algorithm; 549 snps,priority = <0x8>; 550 }; 551 }; 552 }; 553 }; 554 555 stmmac_axi_setup: stmmac-axi-config { 556 snps,lpi_en; 557 snps,wr_osr_lmt = <0xf>; 558 snps,rd_osr_lmt = <0xf>; 559 snps,blen = <16 8 4 0 0 0 0>; 560 }; 561 562 timer { 563 compatible = "arm,armv8-timer"; 564 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 565 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 566 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 567 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 568 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 569 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 570 }; 571}; 572