1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Spider Ethernet sub-board 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8/ { 9 aliases { 10 ethernet0 = &rswitch_port0; 11 ethernet1 = &rswitch_port1; 12 ethernet2 = &rswitch_port2; 13 }; 14}; 15 16ð_serdes { 17 status = "okay"; 18}; 19 20&i2c4 { 21 eeprom@52 { 22 compatible = "rohm,br24g01", "atmel,24c01"; 23 label = "ethernet-sub-board"; 24 reg = <0x52>; 25 pagesize = <8>; 26 }; 27}; 28 29&pfc { 30 tsn0_pins: tsn0 { 31 groups = "tsn0_mdio_b", "tsn0_link_b"; 32 function = "tsn0"; 33 power-source = <1800>; 34 }; 35 36 tsn1_pins: tsn1 { 37 groups = "tsn1_mdio_b", "tsn1_link_b"; 38 function = "tsn1"; 39 power-source = <1800>; 40 }; 41 42 tsn2_pins: tsn2 { 43 groups = "tsn2_mdio_b", "tsn2_link_b"; 44 function = "tsn2"; 45 power-source = <1800>; 46 }; 47}; 48 49&rswitch { 50 pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; 51 pinctrl-names = "default"; 52 status = "okay"; 53}; 54 55&rswitch_port0 { 56 reg = <0>; 57 phy-handle = <&u101>; 58 phy-mode = "sgmii"; 59 phys = <ð_serdes 0>; 60 61 mdio { 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 u101: ethernet-phy@1 { 66 reg = <1>; 67 compatible = "ethernet-phy-ieee802.3-c45"; 68 interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; 69 }; 70 }; 71}; 72 73&rswitch_port1 { 74 reg = <1>; 75 phy-handle = <&u201>; 76 phy-mode = "sgmii"; 77 phys = <ð_serdes 1>; 78 79 mdio { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 u201: ethernet-phy@2 { 84 reg = <2>; 85 compatible = "ethernet-phy-ieee802.3-c45"; 86 interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; 87 }; 88 }; 89}; 90 91&rswitch_port2 { 92 reg = <2>; 93 phy-handle = <&u301>; 94 phy-mode = "sgmii"; 95 phys = <ð_serdes 2>; 96 97 mdio { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 u301: ethernet-phy@3 { 102 reg = <3>; 103 compatible = "ethernet-phy-ieee802.3-c45"; 104 interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; 105 }; 106 }; 107}; 108