1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-msm8976.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 cpu-idle-states = <&little_cpu_sleep_0>; 41 capacity-dmips-mhz = <573>; 42 next-level-cache = <&l2_0>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x1>; 50 enable-method = "psci"; 51 cpu-idle-states = <&little_cpu_sleep_0>; 52 capacity-dmips-mhz = <573>; 53 next-level-cache = <&l2_0>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x2>; 61 enable-method = "psci"; 62 cpu-idle-states = <&little_cpu_sleep_0>; 63 capacity-dmips-mhz = <573>; 64 next-level-cache = <&l2_0>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x3>; 72 enable-method = "psci"; 73 cpu-idle-states = <&little_cpu_sleep_0>; 74 capacity-dmips-mhz = <573>; 75 next-level-cache = <&l2_0>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu4: cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a72"; 82 reg = <0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 85 capacity-dmips-mhz = <1024>; 86 next-level-cache = <&l2_1>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu5: cpu@101 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a72"; 93 reg = <0x101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 96 capacity-dmips-mhz = <1024>; 97 next-level-cache = <&l2_1>; 98 #cooling-cells = <2>; 99 }; 100 101 cpu6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72"; 104 reg = <0x102>; 105 enable-method = "psci"; 106 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 107 capacity-dmips-mhz = <1024>; 108 next-level-cache = <&l2_1>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu7: cpu@103 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 reg = <0x103>; 116 enable-method = "psci"; 117 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 118 capacity-dmips-mhz = <1024>; 119 next-level-cache = <&l2_1>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu4>; 145 }; 146 147 core1 { 148 cpu = <&cpu5>; 149 }; 150 151 core2 { 152 cpu = <&cpu6>; 153 }; 154 155 core3 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 161 idle-states { 162 entry-method = "psci"; 163 164 little_cpu_sleep_0: cpu-sleep-0-0 { 165 compatible = "arm,idle-state"; 166 idle-state-name = "little-power-collapse"; 167 arm,psci-suspend-param = <0x40000003>; 168 entry-latency-us = <181>; 169 exit-latency-us = <149>; 170 min-residency-us = <703>; 171 local-timer-stop; 172 }; 173 174 big_cpu_sleep_0: cpu-sleep-1-0 { 175 compatible = "arm,idle-state"; 176 idle-state-name = "big-retention"; 177 arm,psci-suspend-param = <0x00000002>; 178 entry-latency-us = <142>; 179 exit-latency-us = <99>; 180 min-residency-us = <242>; 181 }; 182 183 big_cpu_sleep_1: cpu-sleep-1-1 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "big-power-collapse"; 186 arm,psci-suspend-param = <0x40000003>; 187 entry-latency-us = <158>; 188 exit-latency-us = <144>; 189 min-residency-us = <863>; 190 local-timer-stop; 191 }; 192 }; 193 194 l2_0: l2-cache0 { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 }; 199 200 l2_1: l2-cache1 { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-msm8976", "qcom,scm"; 210 clocks = <&gcc GCC_CRYPTO_CLK>, 211 <&gcc GCC_CRYPTO_AXI_CLK>, 212 <&gcc GCC_CRYPTO_AHB_CLK>; 213 clock-names = "core", "bus", "iface"; 214 #reset-cells = <1>; 215 216 qcom,dload-mode = <&tcsr 0x6100>; 217 }; 218 }; 219 220 memory@80000000 { 221 device_type = "memory"; 222 /* We expect the bootloader to fill in the size */ 223 reg = <0x0 0x80000000 0x0 0x0>; 224 }; 225 226 pmu-a53 { 227 compatible = "arm,cortex-a53-pmu"; 228 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 229 }; 230 231 pmu_a72: pmu-a72 { 232 compatible = "arm,cortex-a72-pmu"; 233 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; 234 }; 235 236 237 psci { 238 compatible = "arm,psci-1.0"; 239 method = "smc"; 240 }; 241 242 rpm: remoteproc { 243 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc"; 244 245 smd-edge { 246 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 247 mboxes = <&apcs 0>; 248 qcom,smd-edge = <15>; 249 250 rpm_requests: rpm-requests { 251 compatible = "qcom,rpm-msm8976", "qcom,smd-rpm"; 252 qcom,smd-channels = "rpm_requests"; 253 254 rpmcc: clock-controller { 255 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 256 clocks = <&xo_board>; 257 clock-names = "xo"; 258 #clock-cells = <1>; 259 }; 260 261 rpmpd: power-controller { 262 compatible = "qcom,msm8976-rpmpd"; 263 #power-domain-cells = <1>; 264 operating-points-v2 = <&rpmpd_opp_table>; 265 266 rpmpd_opp_table: opp-table { 267 compatible = "operating-points-v2"; 268 269 rpmpd_opp_ret: opp1 { 270 opp-level = <RPM_SMD_LEVEL_RETENTION>; 271 }; 272 273 rpmpd_opp_ret_plus: opp2 { 274 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 275 }; 276 277 rpmpd_opp_min_svs: opp3 { 278 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 279 }; 280 281 rpmpd_opp_low_svs: opp4 { 282 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 283 }; 284 285 rpmpd_opp_svs: opp5 { 286 opp-level = <RPM_SMD_LEVEL_SVS>; 287 }; 288 289 rpmpd_opp_svs_plus: opp6 { 290 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 291 }; 292 293 rpmpd_opp_nom: opp7 { 294 opp-level = <RPM_SMD_LEVEL_NOM>; 295 }; 296 297 rpmpd_opp_nom_plus: opp8 { 298 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 299 }; 300 301 rpmpd_opp_turbo: opp9 { 302 opp-level = <RPM_SMD_LEVEL_TURBO>; 303 }; 304 305 rpmpd_opp_turbo_no_cpr: opp10 { 306 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 307 }; 308 309 rpmpd_opp_turbo_high: opp111 { 310 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 311 }; 312 }; 313 }; 314 }; 315 }; 316 }; 317 318 reserved-memory { 319 #address-cells = <2>; 320 #size-cells = <2>; 321 ranges; 322 323 ext-region@85b00000 { 324 reg = <0x0 0x85b00000 0x0 0x500000>; 325 no-map; 326 }; 327 328 smem@86300000 { 329 compatible = "qcom,smem"; 330 reg = <0x0 0x86300000 0x0 0x100000>; 331 no-map; 332 333 hwlocks = <&tcsr_mutex 3>; 334 qcom,rpm-msg-ram = <&rpm_msg_ram>; 335 }; 336 337 reserved@86400000 { 338 reg = <0x0 0x86400000 0x0 0x800000>; 339 no-map; 340 }; 341 342 mpss_mem: mpss@86c00000 { 343 reg = <0x0 0x86c00000 0x0 0x5600000>; 344 no-map; 345 }; 346 347 lpass_mem: lpass@8c200000 { 348 reg = <0x0 0x8c200000 0x0 0x1000000>; 349 no-map; 350 }; 351 352 wcnss_fw_mem: wcnss@8d200000 { 353 reg = <0x0 0x8d200000 0x0 0x800000>; 354 no-map; 355 }; 356 357 venus_mem: memory@8da00000 { 358 reg = <0x0 0x8da00000 0x0 0x2600000>; 359 no-map; 360 }; 361 362 tz-apps@8dd00000 { 363 reg = <0x0 0x8dd00000 0x0 0x1400000>; 364 no-map; 365 }; 366 }; 367 368 smp2p-hexagon { 369 compatible = "qcom,smp2p"; 370 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 371 mboxes = <&apcs 10>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <2>; 375 qcom,smem = <443>, <429>; 376 377 adsp_smp2p_out: master-kernel { 378 qcom,entry-name = "master-kernel"; 379 380 #qcom,smem-state-cells = <1>; 381 }; 382 383 adsp_smp2p_in: slave-kernel { 384 qcom,entry-name = "slave-kernel"; 385 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smp2p-modem { 392 compatible = "qcom,smp2p"; 393 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&apcs 14>; 395 396 qcom,local-pid = <0>; 397 qcom,remote-pid = <1>; 398 qcom,smem = <435>, <428>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 403 #qcom,smem-state-cells = <1>; 404 }; 405 406 modem_smp2p_in: slave-kernel { 407 qcom,entry-name = "slave-kernel"; 408 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 }; 412 }; 413 414 smp2p-wcnss { 415 compatible = "qcom,smp2p"; 416 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 417 mboxes = <&apcs 18>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <4>; 421 qcom,smem = <451>, <431>; 422 423 wcnss_smp2p_out: master-kernel { 424 qcom,entry-name = "master-kernel"; 425 426 #qcom,smem-state-cells = <1>; 427 }; 428 429 wcnss_smp2p_in: slave-kernel { 430 qcom,entry-name = "slave-kernel"; 431 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 }; 436 437 smsm { 438 compatible = "qcom,smsm"; 439 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 444 445 apps_smsm: apps@0 { 446 reg = <0>; 447 #qcom,smem-state-cells = <1>; 448 }; 449 450 hexagon_smsm: hexagon@1 { 451 reg = <1>; 452 interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 458 wcnss_smsm: wcnss@6 { 459 reg = <6>; 460 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 461 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 }; 465 }; 466 467 soc: soc@0 { 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0 0 0 0xffffffff>; 471 compatible = "simple-bus"; 472 473 rng@22000 { 474 compatible = "qcom,prng"; 475 reg = <0x00022000 0x140>; 476 clocks = <&gcc GCC_PRNG_AHB_CLK>; 477 clock-names = "core"; 478 }; 479 480 rpm_msg_ram: sram@60000 { 481 compatible = "qcom,rpm-msg-ram"; 482 reg = <0x00060000 0x8000>; 483 }; 484 485 usb_hs_phy: phy@6c000 { 486 compatible = "qcom,usb-hs-28nm-femtophy"; 487 reg = <0x0006c000 0x200>; 488 #phy-cells = <0>; 489 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 490 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 491 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 492 clock-names = "ref", "ahb", "sleep"; 493 resets = <&gcc RST_QUSB2_PHY_BCR>, 494 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 495 reset-names = "phy", "por"; 496 status = "disabled"; 497 }; 498 499 qfprom: qfprom@a4000 { 500 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 501 reg = <0x000a4000 0x1000>; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 505 tsens_base1: base1@218 { 506 reg = <0x218 1>; 507 bits = <0 8>; 508 }; 509 510 tsens_s0_p1: s0-p1@219 { 511 reg = <0x219 0x1>; 512 bits = <0 6>; 513 }; 514 515 tsens_s0_p2: s0-p2@219 { 516 reg = <0x219 0x2>; 517 bits = <6 6>; 518 }; 519 520 tsens_s1_p1: s1-p1@21a { 521 reg = <0x21a 0x2>; 522 bits = <4 6>; 523 }; 524 525 tsens_s1_p2: s1-p2@21b { 526 reg = <0x21b 0x1>; 527 bits = <2 6>; 528 }; 529 530 tsens_s2_p1: s2-p1@21c { 531 reg = <0x21c 0x1>; 532 bits = <0 6>; 533 }; 534 535 tsens_s2_p2: s2-p2@21c { 536 reg = <0x21c 0x2>; 537 bits = <6 6>; 538 }; 539 540 tsens_s3_p1: s3-p1@21d { 541 reg = <0x21d 0x2>; 542 bits = <4 6>; 543 }; 544 545 tsens_s3_p2: s3-p2@21e { 546 reg = <0x21e 0x1>; 547 bits = <2 6>; 548 }; 549 550 tsens_base2: base2@220 { 551 reg = <0x220 1>; 552 bits = <0 8>; 553 }; 554 555 tsens_s4_p1: s4-p1@221 { 556 reg = <0x221 0x1>; 557 bits = <0 6>; 558 }; 559 560 tsens_s4_p2: s4-p2@221 { 561 reg = <0x221 0x2>; 562 bits = <6 6>; 563 }; 564 565 tsens_s5_p1: s5-p1@222 { 566 reg = <0x222 0x2>; 567 bits = <4 6>; 568 }; 569 570 tsens_s5_p2: s5-p2@223 { 571 reg = <0x224 0x1>; 572 bits = <2 6>; 573 }; 574 575 tsens_s6_p1: s6-p1@224 { 576 reg = <0x224 0x1>; 577 bits = <0 6>; 578 }; 579 580 tsens_s6_p2: s6-p2@224 { 581 reg = <0x224 0x2>; 582 bits = <6 6>; 583 }; 584 585 tsens_s7_p1: s7-p1@225 { 586 reg = <0x225 0x2>; 587 bits = <4 6>; 588 }; 589 590 tsens_s7_p2: s7-p2@226 { 591 reg = <0x226 0x2>; 592 bits = <2 6>; 593 }; 594 595 tsens_mode: mode@228 { 596 reg = <0x228 1>; 597 bits = <0 3>; 598 }; 599 600 tsens_s8_p1: s8-p1@228 { 601 reg = <0x228 0x2>; 602 bits = <3 6>; 603 }; 604 605 tsens_s8_p2: s8-p2@229 { 606 reg = <0x229 0x1>; 607 bits = <1 6>; 608 }; 609 610 tsens_s9_p1: s9-p1@229 { 611 reg = <0x229 0x2>; 612 bits = <7 6>; 613 }; 614 615 tsens_s9_p2: s9-p2@22a { 616 reg = <0x22a 0x2>; 617 bits = <5 6>; 618 }; 619 620 tsens_s10_p1: s10-p1@22b { 621 reg = <0x22b 0x2>; 622 bits = <3 6>; 623 }; 624 625 tsens_s10_p2: s10-p2@22c { 626 reg = <0x22c 0x1>; 627 bits = <1 6>; 628 }; 629 }; 630 631 tsens: thermal-sensor@4a9000 { 632 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 633 reg = <0x004a9000 0x1000>, /* TM */ 634 <0x004a8000 0x1000>; /* SROT */ 635 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "uplow"; 637 nvmem-cells = <&tsens_mode>, 638 <&tsens_base1>, <&tsens_base2>, 639 <&tsens_s0_p1>, <&tsens_s0_p2>, 640 <&tsens_s1_p1>, <&tsens_s1_p2>, 641 <&tsens_s2_p1>, <&tsens_s2_p2>, 642 <&tsens_s3_p1>, <&tsens_s3_p2>, 643 <&tsens_s4_p1>, <&tsens_s4_p2>, 644 <&tsens_s5_p1>, <&tsens_s5_p2>, 645 <&tsens_s6_p1>, <&tsens_s6_p2>, 646 <&tsens_s7_p1>, <&tsens_s7_p2>, 647 <&tsens_s8_p1>, <&tsens_s8_p2>, 648 <&tsens_s9_p1>, <&tsens_s9_p2>, 649 <&tsens_s10_p1>, <&tsens_s10_p2>; 650 nvmem-cell-names = "mode", 651 "base1", "base2", 652 "s0_p1", "s0_p2", 653 "s1_p1", "s1_p2", 654 "s2_p1", "s2_p2", 655 "s3_p1", "s3_p2", 656 "s4_p1", "s4_p2", 657 "s5_p1", "s5_p2", 658 "s6_p1", "s6_p2", 659 "s7_p1", "s7_p2", 660 "s8_p1", "s8_p2", 661 "s9_p1", "s9_p2", 662 "s10_p1", "s10_p2"; 663 #qcom,sensors = <11>; 664 #thermal-sensor-cells = <1>; 665 }; 666 667 restart@4ab000 { 668 compatible = "qcom,pshold"; 669 reg = <0x004ab000 0x4>; 670 }; 671 672 tlmm: pinctrl@1000000 { 673 compatible = "qcom,msm8976-pinctrl"; 674 reg = <0x01000000 0x300000>; 675 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 676 #gpio-cells = <2>; 677 gpio-controller; 678 gpio-ranges = <&tlmm 0 0 145>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 682 spi1_default: spi0-default-state { 683 spi-pins { 684 pins = "gpio0", "gpio1", "gpio3"; 685 function = "blsp_spi1"; 686 drive-strength = <12>; 687 bias-disable; 688 }; 689 690 cs-pins { 691 pins = "gpio2"; 692 function = "blsp_spi1"; 693 drive-strength = <2>; 694 bias-disable; 695 }; 696 }; 697 698 spi1_sleep: spi0-sleep-state { 699 spi-pins { 700 pins = "gpio0", "gpio1", "gpio3"; 701 function = "gpio"; 702 drive-strength = <2>; 703 bias-pull-down; 704 }; 705 706 cs-pins { 707 pins = "gpio2"; 708 function = "gpio"; 709 drive-strength = <2>; 710 bias-disable; 711 }; 712 }; 713 714 blsp1_i2c2_default: blsp1-i2c2-default-state { 715 pins = "gpio6", "gpio7"; 716 function = "blsp_i2c2"; 717 drive-strength = <2>; 718 bias-disable; 719 }; 720 721 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 722 pins = "gpio6", "gpio7"; 723 function = "gpio"; 724 drive-strength = <2>; 725 bias-disable; 726 }; 727 728 blsp1_i2c4_default: blsp1-i2c4-default-state { 729 pins = "gpio14", "gpio15"; 730 function = "blsp_i2c4"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 736 pins = "gpio14", "gpio15"; 737 function = "gpio"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 blsp2_uart2_active: blsp2-uart2-active-state { 743 pins = "gpio20", "gpio21"; 744 function = "blsp_uart6"; 745 drive-strength = <4>; 746 bias-disable; 747 }; 748 749 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 750 pins = "gpio20", "gpio21"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 757 blsp2_i2c2_default: blsp2-i2c2-default-state { 758 pins = "gpio22", "gpio23"; 759 function = "blsp_i2c6"; 760 drive-strength = <2>; 761 bias-disable; 762 }; 763 764 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 765 pins = "gpio22", "gpio23"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-disable; 769 }; 770 771 blsp2_i2c4_default: blsp2-i2c4-default-state { 772 pins = "gpio18", "gpio19"; 773 function = "blsp_i2c8"; 774 drive-strength = <2>; 775 bias-disable; 776 }; 777 778 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 779 pins = "gpio18", "gpio19"; 780 function = "gpio"; 781 drive-strength = <2>; 782 bias-disable; 783 }; 784 785 wcss_wlan_default: wcss-wlan-default-state { 786 wcss-wlan2-pins { 787 pins = "gpio40"; 788 function = "wcss_wlan2"; 789 drive-strength = <6>; 790 bias-pull-up; 791 }; 792 793 wcss-wlan1-pins { 794 pins = "gpio41"; 795 function = "wcss_wlan1"; 796 drive-strength = <6>; 797 bias-pull-up; 798 }; 799 800 wcss-wlan0-pins { 801 pins = "gpio42"; 802 function = "wcss_wlan0"; 803 drive-strength = <6>; 804 bias-pull-up; 805 }; 806 807 wcss-wlan-pins { 808 pins = "gpio43", "gpio44"; 809 function = "wcss_wlan"; 810 drive-strength = <6>; 811 bias-pull-up; 812 }; 813 }; 814 }; 815 816 gcc: clock-controller@1800000 { 817 compatible = "qcom,gcc-msm8976"; 818 reg = <0x01800000 0x80000>; 819 #clock-cells = <1>; 820 #reset-cells = <1>; 821 #power-domain-cells = <1>; 822 823 assigned-clocks = <&gcc GPLL3>; 824 assigned-clock-rates = <1100000000>; 825 826 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 827 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 828 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 829 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 830 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 831 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 832 clock-names = "xo", 833 "xo_a", 834 "dsi0pll", 835 "dsi0pllbyte", 836 "dsi1pll", 837 "dsi1pllbyte"; 838 }; 839 840 tcsr_mutex: hwlock@1905000 { 841 compatible = "qcom,tcsr-mutex"; 842 reg = <0x01905000 0x20000>; 843 #hwlock-cells = <1>; 844 }; 845 846 tcsr: syscon@1937000 { 847 compatible = "qcom,msm8976-tcsr", "syscon"; 848 reg = <0x01937000 0x30000>; 849 }; 850 851 mdss: display-subsystem@1a00000 { 852 compatible = "qcom,mdss"; 853 854 reg = <0x01a00000 0x1000>, 855 <0x01ab0000 0x3000>; 856 reg-names = "mdss_phys", "vbif_phys"; 857 858 power-domains = <&gcc MDSS_GDSC>; 859 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 860 861 interrupt-controller; 862 #interrupt-cells = <1>; 863 864 clocks = <&gcc GCC_MDSS_AHB_CLK>, 865 <&gcc GCC_MDSS_AXI_CLK>, 866 <&gcc GCC_MDSS_VSYNC_CLK>, 867 <&gcc GCC_MDSS_MDP_CLK>; 868 clock-names = "iface", 869 "bus", 870 "vsync", 871 "core"; 872 873 #address-cells = <1>; 874 #size-cells = <1>; 875 ranges; 876 877 status = "disabled"; 878 879 mdss_mdp: display-controller@1a01000 { 880 compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; 881 reg = <0x01a01000 0x89000>; 882 reg-names = "mdp_phys"; 883 884 interrupt-parent = <&mdss>; 885 interrupts = <0>; 886 887 clocks = <&gcc GCC_MDSS_AHB_CLK>, 888 <&gcc GCC_MDSS_AXI_CLK>, 889 <&gcc GCC_MDSS_MDP_CLK>, 890 <&gcc GCC_MDSS_VSYNC_CLK>, 891 <&gcc GCC_MDP_TBU_CLK>, 892 <&gcc GCC_MDP_RT_TBU_CLK>; 893 clock-names = "iface", 894 "bus", 895 "core", 896 "vsync", 897 "tbu", 898 "tbu_rt"; 899 900 operating-points-v2 = <&mdp_opp_table>; 901 power-domains = <&gcc MDSS_GDSC>; 902 903 iommus = <&apps_iommu 22>; 904 905 ports { 906 #address-cells = <1>; 907 #size-cells = <0>; 908 909 port@0 { 910 reg = <0>; 911 912 mdss_mdp5_intf1_out: endpoint { 913 remote-endpoint = <&mdss_dsi0_in>; 914 }; 915 }; 916 917 port@1 { 918 reg = <1>; 919 920 mdss_mdp5_intf2_out: endpoint { 921 remote-endpoint = <&mdss_dsi1_in>; 922 }; 923 }; 924 }; 925 926 mdp_opp_table: opp-table { 927 compatible = "operating-points-v2"; 928 929 opp-177780000 { 930 opp-hz = /bits/ 64 <177780000>; 931 required-opps = <&rpmpd_opp_svs>; 932 }; 933 934 opp-270000000 { 935 opp-hz = /bits/ 64 <270000000>; 936 required-opps = <&rpmpd_opp_svs_plus>; 937 }; 938 939 opp-320000000 { 940 opp-hz = /bits/ 64 <320000000>; 941 required-opps = <&rpmpd_opp_nom>; 942 }; 943 944 opp-360000000 { 945 opp-hz = /bits/ 64 <360000000>; 946 required-opps = <&rpmpd_opp_turbo>; 947 }; 948 }; 949 }; 950 951 mdss_dsi0: dsi@1a94000 { 952 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 953 reg = <0x01a94000 0x300>; 954 reg-names = "dsi_ctrl"; 955 956 interrupt-parent = <&mdss>; 957 interrupts = <4>; 958 959 clocks = <&gcc GCC_MDSS_MDP_CLK>, 960 <&gcc GCC_MDSS_AHB_CLK>, 961 <&gcc GCC_MDSS_AXI_CLK>, 962 <&gcc GCC_MDSS_BYTE0_CLK>, 963 <&gcc GCC_MDSS_PCLK0_CLK>, 964 <&gcc GCC_MDSS_ESC0_CLK>; 965 clock-names = "mdp_core", 966 "iface", 967 "bus", 968 "byte", 969 "pixel", 970 "core"; 971 972 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, 973 <&gcc GCC_MDSS_PCLK0_CLK_SRC>; 974 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 975 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 976 977 phys = <&mdss_dsi0_phy>; 978 979 operating-points-v2 = <&dsi0_opp_table>; 980 power-domains = <&gcc MDSS_GDSC>; 981 982 #address-cells = <1>; 983 #size-cells = <0>; 984 985 status = "disabled"; 986 987 ports { 988 #address-cells = <1>; 989 #size-cells = <0>; 990 991 port@0 { 992 reg = <0>; 993 994 mdss_dsi0_in: endpoint { 995 remote-endpoint = <&mdss_mdp5_intf1_out>; 996 }; 997 }; 998 999 port@1 { 1000 reg = <1>; 1001 1002 mdss_dsi0_out: endpoint { 1003 }; 1004 }; 1005 }; 1006 1007 dsi0_opp_table: opp-table { 1008 compatible = "operating-points-v2"; 1009 1010 opp-125000000 { 1011 opp-hz = /bits/ 64 <125000000>; 1012 required-opps = <&rpmpd_opp_svs>; 1013 }; 1014 1015 opp-161250000 { 1016 opp-hz = /bits/ 64 <161250000>; 1017 required-opps = <&rpmpd_opp_svs_plus>; 1018 }; 1019 1020 opp-187500000 { 1021 opp-hz = /bits/ 64 <187500000>; 1022 required-opps = <&rpmpd_opp_nom>; 1023 }; 1024 }; 1025 }; 1026 1027 mdss_dsi1: dsi@1a96000 { 1028 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1029 reg = <0x01a96000 0x300>; 1030 reg-names = "dsi_ctrl"; 1031 1032 interrupt-parent = <&mdss>; 1033 interrupts = <5>; 1034 1035 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1036 <&gcc GCC_MDSS_AHB_CLK>, 1037 <&gcc GCC_MDSS_AXI_CLK>, 1038 <&gcc GCC_MDSS_BYTE1_CLK>, 1039 <&gcc GCC_MDSS_PCLK1_CLK>, 1040 <&gcc GCC_MDSS_ESC1_CLK>; 1041 clock-names = "mdp_core", 1042 "iface", 1043 "bus", 1044 "byte", 1045 "pixel", 1046 "core"; 1047 1048 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, 1049 <&gcc GCC_MDSS_PCLK1_CLK_SRC>; 1050 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1051 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1052 1053 phys = <&mdss_dsi1_phy>; 1054 1055 operating-points-v2 = <&dsi0_opp_table>; 1056 power-domains = <&gcc MDSS_GDSC>; 1057 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 1061 status = "disabled"; 1062 1063 ports { 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 port@0 { 1068 reg = <0>; 1069 1070 mdss_dsi1_in: endpoint { 1071 remote-endpoint = <&mdss_mdp5_intf2_out>; 1072 }; 1073 }; 1074 1075 port@1 { 1076 reg = <1>; 1077 1078 mdss_dsi1_out: endpoint { 1079 }; 1080 }; 1081 }; 1082 }; 1083 1084 mdss_dsi0_phy: phy@1a94a00 { 1085 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1086 reg = <0x01a94a00 0xd4>, 1087 <0x01a94400 0x280>, 1088 <0x01a94b80 0x30>; 1089 reg-names = "dsi_pll", 1090 "dsi_phy", 1091 "dsi_phy_regulator"; 1092 1093 #clock-cells = <1>; 1094 #phy-cells = <0>; 1095 1096 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1097 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1098 clock-names = "iface", "ref"; 1099 1100 status = "disabled"; 1101 }; 1102 1103 mdss_dsi1_phy: phy@1a96a00 { 1104 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1105 reg = <0x01a96a00 0xd4>, 1106 <0x01a96400 0x280>, 1107 <0x01a96b80 0x30>; 1108 reg-names = "dsi_pll", 1109 "dsi_phy", 1110 "dsi_phy_regulator"; 1111 1112 #clock-cells = <1>; 1113 #phy-cells = <0>; 1114 1115 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1116 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1117 clock-names = "iface", "ref"; 1118 1119 status = "disabled"; 1120 }; 1121 }; 1122 1123 adreno_gpu: gpu@1c00000 { 1124 compatible = "qcom,adreno-510.0", "qcom,adreno"; 1125 1126 reg = <0x01c00000 0x40000>; 1127 reg-names = "kgsl_3d0_reg_memory"; 1128 1129 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1130 interrupt-names = "kgsl_3d0_irq"; 1131 1132 clocks = <&gcc GCC_GFX3D_OXILI_CLK>, 1133 <&gcc GCC_GFX3D_OXILI_AHB_CLK>, 1134 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, 1135 <&gcc GCC_GFX3D_BIMC_CLK>, 1136 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, 1137 <&gcc GCC_GFX3D_OXILI_AON_CLK>; 1138 clock-names = "core", 1139 "iface", 1140 "mem", 1141 "mem_iface", 1142 "rbbmtimer", 1143 "alwayson"; 1144 1145 power-domains = <&gcc OXILI_GX_GDSC>; 1146 1147 iommus = <&gpu_iommu 0>; 1148 1149 operating-points-v2 = <&gpu_opp_table>; 1150 1151 status = "disabled"; 1152 1153 gpu_opp_table: opp-table { 1154 compatible = "operating-points-v2"; 1155 1156 opp-200000000 { 1157 opp-hz = /bits/ 64 <200000000>; 1158 required-opps = <&rpmpd_opp_low_svs>; 1159 opp-supported-hw = <0xff>; 1160 }; 1161 1162 opp-300000000 { 1163 opp-hz = /bits/ 64 <300000000>; 1164 required-opps = <&rpmpd_opp_svs>; 1165 opp-supported-hw = <0xff>; 1166 }; 1167 1168 opp-400000000 { 1169 opp-hz = /bits/ 64 <400000000>; 1170 required-opps = <&rpmpd_opp_nom>; 1171 opp-supported-hw = <0xff>; 1172 }; 1173 1174 opp-480000000 { 1175 opp-hz = /bits/ 64 <480000000>; 1176 required-opps = <&rpmpd_opp_nom_plus>; 1177 opp-supported-hw = <0xff>; 1178 }; 1179 1180 opp-540000000 { 1181 opp-hz = /bits/ 64 <540000000>; 1182 required-opps = <&rpmpd_opp_turbo>; 1183 opp-supported-hw = <0xff>; 1184 }; 1185 1186 opp-600000000 { 1187 opp-hz = /bits/ 64 <600000000>; 1188 required-opps = <&rpmpd_opp_turbo>; 1189 opp-supported-hw = <0xff>; 1190 }; 1191 }; 1192 }; 1193 1194 apps_iommu: iommu@1ee0000 { 1195 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1196 reg = <0x01ee0000 0x3000>; 1197 ranges = <0 0x01e20000 0x20000>; 1198 1199 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1200 <&gcc GCC_APSS_TCU_CLK>; 1201 clock-names = "iface", "bus"; 1202 1203 qcom,iommu-secure-id = <17>; 1204 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 #iommu-cells = <1>; 1208 1209 /* VFE */ 1210 iommu-ctx@15000 { 1211 compatible = "qcom,msm-iommu-v2-ns"; 1212 reg = <0x15000 0x1000>; 1213 qcom,ctx-asid = <20>; 1214 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1215 }; 1216 1217 /* VENUS NS */ 1218 iommu-ctx@16000 { 1219 compatible = "qcom,msm-iommu-v2-ns"; 1220 reg = <0x16000 0x1000>; 1221 qcom,ctx-asid = <21>; 1222 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1223 }; 1224 1225 /* MDP0 */ 1226 iommu-ctx@17000 { 1227 compatible = "qcom,msm-iommu-v2-ns"; 1228 reg = <0x17000 0x1000>; 1229 qcom,ctx-asid = <22>; 1230 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1231 }; 1232 }; 1233 1234 gpu_iommu: iommu@1f08000 { 1235 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1236 ranges = <0 0x01f08000 0x8000>; 1237 1238 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1239 <&gcc GCC_GFX3D_TCU_CLK>; 1240 clock-names = "iface", "bus"; 1241 1242 power-domains = <&gcc OXILI_CX_GDSC>; 1243 1244 qcom,iommu-secure-id = <18>; 1245 1246 #address-cells = <1>; 1247 #size-cells = <1>; 1248 #iommu-cells = <1>; 1249 1250 /* gfx3d user */ 1251 iommu-ctx@0 { 1252 compatible = "qcom,msm-iommu-v2-ns"; 1253 reg = <0x0 0x1000>; 1254 qcom,ctx-asid = <0>; 1255 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1256 }; 1257 1258 /* gfx3d secure */ 1259 iommu-ctx@1000 { 1260 compatible = "qcom,msm-iommu-v2-sec"; 1261 reg = <0x1000 0x1000>; 1262 qcom,ctx-asid = <2>; 1263 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1264 }; 1265 1266 /* gfx3d priv */ 1267 iommu-ctx@2000 { 1268 compatible = "qcom,msm-iommu-v2-sec"; 1269 reg = <0x2000 0x1000>; 1270 qcom,ctx-asid = <1>; 1271 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1272 }; 1273 }; 1274 1275 spmi_bus: spmi@200f000 { 1276 compatible = "qcom,spmi-pmic-arb"; 1277 reg = <0x0200f000 0x1000>, 1278 <0x02400000 0x800000>, 1279 <0x02c00000 0x800000>, 1280 <0x03800000 0x200000>, 1281 <0x0200a000 0x2100>; 1282 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1283 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1284 interrupt-names = "periph_irq"; 1285 qcom,channel = <0>; 1286 qcom,ee = <0>; 1287 1288 #address-cells = <2>; 1289 #size-cells = <0>; 1290 interrupt-controller; 1291 #interrupt-cells = <4>; 1292 }; 1293 1294 sdhc_1: mmc@7824900 { 1295 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1296 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1297 reg-names = "hc", "core"; 1298 1299 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1301 interrupt-names = "hc_irq", "pwr_irq"; 1302 1303 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1304 <&gcc GCC_SDCC1_APPS_CLK>, 1305 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1306 clock-names = "iface", "core", "xo"; 1307 status = "disabled"; 1308 }; 1309 1310 sdhc_2: mmc@7864900 { 1311 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1312 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1313 reg-names = "hc", "core"; 1314 1315 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1317 interrupt-names = "hc_irq", "pwr_irq"; 1318 1319 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1320 <&gcc GCC_SDCC2_APPS_CLK>, 1321 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1322 clock-names = "iface", "core", "xo"; 1323 status = "disabled"; 1324 }; 1325 1326 blsp1_dma: dma-controller@7884000 { 1327 compatible = "qcom,bam-v1.7.0"; 1328 reg = <0x07884000 0x1f000>; 1329 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1331 clock-names = "bam_clk"; 1332 #dma-cells = <1>; 1333 qcom,ee = <0>; 1334 }; 1335 1336 blsp1_uart1: serial@78af000 { 1337 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1338 reg = <0x078af000 0x200>; 1339 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1341 clock-names = "core", "iface"; 1342 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1343 dma-names = "tx", "rx"; 1344 status = "disabled"; 1345 }; 1346 1347 blsp1_uart2: serial@78b0000 { 1348 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1349 reg = <0x078b0000 0x200>; 1350 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1352 clock-names = "core", "iface"; 1353 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1354 dma-names = "tx", "rx"; 1355 status = "disabled"; 1356 }; 1357 1358 blsp1_spi1: spi@78b5000 { 1359 compatible = "qcom,spi-qup-v2.2.1"; 1360 reg = <0x078b5000 0x500>; 1361 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1363 clock-names = "core", "iface"; 1364 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1365 dma-names = "tx", "rx"; 1366 pinctrl-names = "default", "sleep"; 1367 pinctrl-0 = <&spi1_default>; 1368 pinctrl-1 = <&spi1_sleep>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 blsp1_i2c2: i2c@78b6000 { 1375 compatible = "qcom,i2c-qup-v2.2.1"; 1376 reg = <0x078b6000 0x500>; 1377 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1379 clock-names = "core", "iface"; 1380 clock-frequency = <400000>; 1381 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1382 dma-names = "tx", "rx"; 1383 pinctrl-names = "default", "sleep"; 1384 pinctrl-0 = <&blsp1_i2c2_default>; 1385 pinctrl-1 = <&blsp1_i2c2_default>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 blsp1_i2c4: i2c@78b8000 { 1392 compatible = "qcom,i2c-qup-v2.2.1"; 1393 reg = <0x078b8000 0x500>; 1394 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1396 clock-names = "core", "iface"; 1397 clock-frequency = <400000>; 1398 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1399 dma-names = "tx", "rx"; 1400 pinctrl-names = "default", "sleep"; 1401 pinctrl-0 = <&blsp1_i2c4_default>; 1402 pinctrl-1 = <&blsp1_i2c4_sleep>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 otg: usb@78db000 { 1409 compatible = "qcom,ci-hdrc"; 1410 reg = <0x078db000 0x200>, 1411 <0x078db200 0x200>; 1412 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1414 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 1415 clock-names = "iface", "core"; 1416 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1417 assigned-clock-rates = <80000000>; 1418 resets = <&gcc RST_USB_HS_BCR>; 1419 reset-names = "core"; 1420 ahb-burst-config = <0>; 1421 dr_mode = "peripheral"; 1422 phy_type = "ulpi"; 1423 phy-names = "usb-phy"; 1424 phys = <&usb_hs_phy>; 1425 status = "disabled"; 1426 #reset-cells = <1>; 1427 }; 1428 1429 sdhc_3: mmc@7a24900 { 1430 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1431 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 1432 reg-names = "hc", "core"; 1433 1434 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1436 interrupt-names = "hc_irq", "pwr_irq"; 1437 1438 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 1439 <&gcc GCC_SDCC3_APPS_CLK>, 1440 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1441 clock-names = "iface", "core", "xo"; 1442 1443 status = "disabled"; 1444 }; 1445 1446 blsp2_dma: dma-controller@7ac4000 { 1447 compatible = "qcom,bam-v1.7.0"; 1448 reg = <0x07ac4000 0x1f000>; 1449 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1451 clock-names = "bam_clk"; 1452 #dma-cells = <1>; 1453 qcom,ee = <0>; 1454 }; 1455 1456 blsp2_uart2: serial@7af0000 { 1457 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1458 reg = <0x07af0000 0x200>; 1459 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1461 clock-names = "core", "iface"; 1462 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1463 dma-names = "tx", "rx"; 1464 status = "disabled"; 1465 }; 1466 1467 blsp2_i2c2: i2c@7af6000 { 1468 compatible = "qcom,i2c-qup-v2.2.1"; 1469 reg = <0x07af6000 0x600>; 1470 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1472 clock-names = "core", "iface"; 1473 clock-frequency = <400000>; 1474 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1475 dma-names = "tx", "rx"; 1476 pinctrl-names = "default", "sleep"; 1477 pinctrl-0 = <&blsp2_i2c2_default>; 1478 pinctrl-1 = <&blsp2_i2c2_sleep>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 blsp2_i2c4: i2c@7af8000 { 1485 compatible = "qcom,i2c-qup-v2.2.1"; 1486 reg = <0x07af8000 0x600>; 1487 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1489 clock-names = "core", "iface"; 1490 clock-frequency = <400000>; 1491 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1492 dma-names = "tx", "rx"; 1493 pinctrl-names = "default", "sleep"; 1494 pinctrl-0 = <&blsp2_i2c4_default>; 1495 pinctrl-1 = <&blsp2_i2c4_sleep>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 wcnss: remoteproc@a204000 { 1502 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1503 reg = <0x0a204000 0x2000>, 1504 <0x0a202000 0x1000>, 1505 <0x0a21b000 0x3000>; 1506 reg-names = "ccu", 1507 "dxe", 1508 "pmu"; 1509 1510 memory-region = <&wcnss_fw_mem>; 1511 1512 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1513 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1514 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1515 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1516 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1517 interrupt-names = "wdog", 1518 "fatal", 1519 "ready", 1520 "handover", 1521 "stop-ack"; 1522 1523 power-domains = <&rpmpd MSM8976_VDDCX>, 1524 <&rpmpd MSM8976_VDDMX>; 1525 power-domain-names = "cx", "mx"; 1526 1527 qcom,smem-states = <&wcnss_smp2p_out 0>; 1528 qcom,smem-state-names = "stop"; 1529 1530 pinctrl-0 = <&wcss_wlan_default>; 1531 pinctrl-names = "default"; 1532 1533 status = "disabled"; 1534 1535 wcnss_iris: iris { 1536 /* Separate chip, compatible is board-specific */ 1537 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1538 clock-names = "xo"; 1539 }; 1540 1541 smd-edge { 1542 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1543 1544 mboxes = <&apcs 17>; 1545 qcom,smd-edge = <6>; 1546 qcom,remote-pid = <4>; 1547 1548 label = "pronto"; 1549 1550 wcnss_ctrl: wcnss { 1551 compatible = "qcom,wcnss"; 1552 qcom,smd-channels = "WCNSS_CTRL"; 1553 1554 qcom,mmio = <&wcnss>; 1555 1556 wcnss_bt: bluetooth { 1557 compatible = "qcom,wcnss-bt"; 1558 }; 1559 1560 wcnss_wifi: wifi { 1561 compatible = "qcom,wcnss-wlan"; 1562 1563 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1565 interrupt-names = "tx", "rx"; 1566 1567 qcom,smem-states = <&apps_smsm 10>, 1568 <&apps_smsm 9>; 1569 qcom,smem-state-names = "tx-enable", 1570 "tx-rings-empty"; 1571 }; 1572 }; 1573 }; 1574 }; 1575 1576 intc: interrupt-controller@b000000 { 1577 compatible = "qcom,msm-qgic2"; 1578 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1579 interrupt-controller; 1580 #interrupt-cells = <3>; 1581 }; 1582 1583 apcs: mailbox@b011000 { 1584 compatible = "qcom,msm8976-apcs-kpss-global", 1585 "qcom,msm8994-apcs-kpss-global", "syscon"; 1586 reg = <0x0b011000 0x1000>; 1587 #mbox-cells = <1>; 1588 }; 1589 1590 timer@b120000 { 1591 compatible = "arm,armv7-timer-mem"; 1592 reg = <0x0b120000 0x1000>; 1593 #address-cells = <1>; 1594 #size-cells = <1>; 1595 ranges; 1596 clock-frequency = <19200000>; 1597 1598 frame@b121000 { 1599 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1600 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1602 frame-number = <0>; 1603 }; 1604 1605 frame@b123000 { 1606 reg = <0x0b123000 0x1000>; 1607 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1608 frame-number = <1>; 1609 status = "disabled"; 1610 }; 1611 1612 frame@b124000 { 1613 reg = <0x0b124000 0x1000>; 1614 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1615 frame-number = <2>; 1616 status = "disabled"; 1617 }; 1618 1619 frame@b125000 { 1620 reg = <0x0b125000 0x1000>; 1621 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1622 frame-number = <3>; 1623 status = "disabled"; 1624 }; 1625 1626 frame@b126000 { 1627 reg = <0x0b126000 0x1000>; 1628 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1629 frame-number = <4>; 1630 status = "disabled"; 1631 }; 1632 1633 frame@b127000 { 1634 reg = <0x0b127000 0x1000>; 1635 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1636 frame-number = <5>; 1637 status = "disabled"; 1638 }; 1639 1640 frame@b128000 { 1641 reg = <0x0b128000 0x1000>; 1642 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1643 frame-number = <6>; 1644 status = "disabled"; 1645 }; 1646 }; 1647 1648 imem: sram@8600000 { 1649 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1650 reg = <0x08600000 0x1000>; 1651 #address-cells = <1>; 1652 #size-cells = <1>; 1653 1654 ranges = <0 0x08600000 0x1000>; 1655 1656 pil-reloc@94c { 1657 compatible = "qcom,pil-reloc-info"; 1658 reg = <0x94c 0xc8>; 1659 }; 1660 }; 1661 }; 1662 1663 thermal-zones { 1664 aoss0-thermal { 1665 polling-delay-passive = <250>; 1666 1667 thermal-sensors = <&tsens 0>; 1668 1669 trips { 1670 aoss0_alert0: trip-point0 { 1671 temperature = <75000>; 1672 hysteresis = <2000>; 1673 type = "hot"; 1674 }; 1675 }; 1676 }; 1677 1678 modem-thermal { 1679 polling-delay-passive = <250>; 1680 1681 thermal-sensors = <&tsens 1>; 1682 trips { 1683 modem_alert0: trip-point0 { 1684 temperature = <75000>; 1685 hysteresis = <2000>; 1686 type = "hot"; 1687 }; 1688 }; 1689 }; 1690 1691 qdsp-thermal { 1692 polling-delay-passive = <250>; 1693 1694 thermal-sensors = <&tsens 2>; 1695 trips { 1696 qdsp_alert0: trip-point0 { 1697 temperature = <75000>; 1698 hysteresis = <2000>; 1699 type = "hot"; 1700 }; 1701 }; 1702 }; 1703 1704 cam-isp-thermal { 1705 polling-delay-passive = <250>; 1706 1707 thermal-sensors = <&tsens 3>; 1708 trips { 1709 cam_isp_alert0: trip-point0 { 1710 temperature = <75000>; 1711 hysteresis = <2000>; 1712 type = "hot"; 1713 }; 1714 }; 1715 }; 1716 1717 cpu4-thermal { 1718 polling-delay-passive = <250>; 1719 1720 thermal-sensors = <&tsens 4>; 1721 1722 trips { 1723 cpu4_alert0: trip-point0 { 1724 temperature = <50000>; 1725 hysteresis = <2000>; 1726 type = "hot"; 1727 }; 1728 cpu4_alert1: trip-point1 { 1729 temperature = <55000>; 1730 hysteresis = <2000>; 1731 type = "passive"; 1732 }; 1733 cpu4_crit: cpu-crit { 1734 temperature = <75000>; 1735 hysteresis = <2000>; 1736 type = "critical"; 1737 }; 1738 }; 1739 }; 1740 1741 cpu5-thermal { 1742 polling-delay-passive = <250>; 1743 1744 thermal-sensors = <&tsens 5>; 1745 1746 trips { 1747 cpu5_alert0: trip-point0 { 1748 temperature = <50000>; 1749 hysteresis = <2000>; 1750 type = "hot"; 1751 }; 1752 cpu5_alert1: trip-point1 { 1753 temperature = <55000>; 1754 hysteresis = <2000>; 1755 type = "passive"; 1756 }; 1757 cpu5_crit: cpu-crit { 1758 temperature = <75000>; 1759 hysteresis = <2000>; 1760 type = "critical"; 1761 }; 1762 }; 1763 }; 1764 1765 cpu6-thermal { 1766 polling-delay-passive = <250>; 1767 1768 thermal-sensors = <&tsens 6>; 1769 1770 trips { 1771 cpu6_alert0: trip-point0 { 1772 temperature = <50000>; 1773 hysteresis = <2000>; 1774 type = "hot"; 1775 }; 1776 cpu6_alert1: trip-point1 { 1777 temperature = <55000>; 1778 hysteresis = <2000>; 1779 type = "passive"; 1780 }; 1781 cpu6_crit: cpu-crit { 1782 temperature = <75000>; 1783 hysteresis = <2000>; 1784 type = "critical"; 1785 }; 1786 }; 1787 }; 1788 1789 cpu7-thermal { 1790 polling-delay-passive = <250>; 1791 1792 thermal-sensors = <&tsens 7>; 1793 1794 trips { 1795 cpu7_alert0: trip-point0 { 1796 temperature = <50000>; 1797 hysteresis = <2000>; 1798 type = "hot"; 1799 }; 1800 cpu7_alert1: trip-point1 { 1801 temperature = <55000>; 1802 hysteresis = <2000>; 1803 type = "passive"; 1804 }; 1805 cpu7_crit: cpu-crit { 1806 temperature = <75000>; 1807 hysteresis = <2000>; 1808 type = "critical"; 1809 }; 1810 }; 1811 }; 1812 1813 big-l2-thermal { 1814 polling-delay-passive = <250>; 1815 1816 thermal-sensors = <&tsens 8>; 1817 1818 trips { 1819 l2_alert0: trip-point0 { 1820 temperature = <50000>; 1821 hysteresis = <2000>; 1822 type = "hot"; 1823 }; 1824 l2_alert1: trip-point1 { 1825 temperature = <55000>; 1826 hysteresis = <2000>; 1827 type = "passive"; 1828 }; 1829 l2_crit: l2-crit { 1830 temperature = <75000>; 1831 hysteresis = <2000>; 1832 type = "critical"; 1833 }; 1834 }; 1835 }; 1836 1837 cpu0-thermal { 1838 polling-delay-passive = <250>; 1839 1840 thermal-sensors = <&tsens 9>; 1841 1842 trips { 1843 cpu0_alert0: trip-point0 { 1844 temperature = <50000>; 1845 hysteresis = <2000>; 1846 type = "hot"; 1847 }; 1848 cpu0_alert1: trip-point1 { 1849 temperature = <55000>; 1850 hysteresis = <2000>; 1851 type = "passive"; 1852 }; 1853 cpu0_crit: cpu-crit { 1854 temperature = <75000>; 1855 hysteresis = <2000>; 1856 type = "critical"; 1857 }; 1858 }; 1859 }; 1860 1861 gpu-thermal { 1862 polling-delay-passive = <250>; 1863 1864 thermal-sensors = <&tsens 10>; 1865 1866 trips { 1867 gpu_alert0: trip-point0 { 1868 temperature = <50000>; 1869 hysteresis = <2000>; 1870 type = "hot"; 1871 }; 1872 gpu_alert1: trip-point1 { 1873 temperature = <55000>; 1874 hysteresis = <2000>; 1875 type = "passive"; 1876 }; 1877 gpu_crit: gpu-crit { 1878 temperature = <75000>; 1879 hysteresis = <2000>; 1880 type = "critical"; 1881 }; 1882 }; 1883 }; 1884 }; 1885 1886 timer { 1887 compatible = "arm,armv8-timer"; 1888 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1889 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1890 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1891 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1892 clock-frequency = <19200000>; 1893 }; 1894}; 1895