1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno 4 * <angelogioacchino.delregno@collabora.com> 5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org> 7 */ 8 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-msm8976.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 enable-method = "psci"; 40 cpu-idle-states = <&little_cpu_sleep_0>; 41 capacity-dmips-mhz = <573>; 42 next-level-cache = <&l2_0>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x1>; 50 enable-method = "psci"; 51 cpu-idle-states = <&little_cpu_sleep_0>; 52 capacity-dmips-mhz = <573>; 53 next-level-cache = <&l2_0>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x2>; 61 enable-method = "psci"; 62 cpu-idle-states = <&little_cpu_sleep_0>; 63 capacity-dmips-mhz = <573>; 64 next-level-cache = <&l2_0>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x3>; 72 enable-method = "psci"; 73 cpu-idle-states = <&little_cpu_sleep_0>; 74 capacity-dmips-mhz = <573>; 75 next-level-cache = <&l2_0>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu4: cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a72"; 82 reg = <0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 85 capacity-dmips-mhz = <1024>; 86 next-level-cache = <&l2_1>; 87 #cooling-cells = <2>; 88 }; 89 90 cpu5: cpu@101 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a72"; 93 reg = <0x101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 96 capacity-dmips-mhz = <1024>; 97 next-level-cache = <&l2_1>; 98 #cooling-cells = <2>; 99 }; 100 101 cpu6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72"; 104 reg = <0x102>; 105 enable-method = "psci"; 106 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 107 capacity-dmips-mhz = <1024>; 108 next-level-cache = <&l2_1>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu7: cpu@103 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 reg = <0x103>; 116 enable-method = "psci"; 117 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 118 capacity-dmips-mhz = <1024>; 119 next-level-cache = <&l2_1>; 120 #cooling-cells = <2>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu4>; 145 }; 146 147 core1 { 148 cpu = <&cpu5>; 149 }; 150 151 core2 { 152 cpu = <&cpu6>; 153 }; 154 155 core3 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 161 idle-states { 162 entry-method = "psci"; 163 164 little_cpu_sleep_0: cpu-sleep-0-0 { 165 compatible = "arm,idle-state"; 166 idle-state-name = "little-power-collapse"; 167 arm,psci-suspend-param = <0x40000003>; 168 entry-latency-us = <181>; 169 exit-latency-us = <149>; 170 min-residency-us = <703>; 171 local-timer-stop; 172 }; 173 174 big_cpu_sleep_0: cpu-sleep-1-0 { 175 compatible = "arm,idle-state"; 176 idle-state-name = "big-retention"; 177 arm,psci-suspend-param = <0x00000002>; 178 entry-latency-us = <142>; 179 exit-latency-us = <99>; 180 min-residency-us = <242>; 181 }; 182 183 big_cpu_sleep_1: cpu-sleep-1-1 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "big-power-collapse"; 186 arm,psci-suspend-param = <0x40000003>; 187 entry-latency-us = <158>; 188 exit-latency-us = <144>; 189 min-residency-us = <863>; 190 local-timer-stop; 191 }; 192 }; 193 194 l2_0: l2-cache0 { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 }; 199 200 l2_1: l2-cache1 { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-msm8976", "qcom,scm"; 210 clocks = <&gcc GCC_CRYPTO_CLK>, 211 <&gcc GCC_CRYPTO_AXI_CLK>, 212 <&gcc GCC_CRYPTO_AHB_CLK>; 213 clock-names = "core", "bus", "iface"; 214 #reset-cells = <1>; 215 216 qcom,dload-mode = <&tcsr 0x6100>; 217 }; 218 }; 219 220 memory@80000000 { 221 device_type = "memory"; 222 /* We expect the bootloader to fill in the size */ 223 reg = <0x0 0x80000000 0x0 0x0>; 224 }; 225 226 pmu-a53 { 227 compatible = "arm,cortex-a53-pmu"; 228 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 229 }; 230 231 pmu_a72: pmu-a72 { 232 compatible = "arm,cortex-a72-pmu"; 233 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; 234 }; 235 236 237 psci { 238 compatible = "arm,psci-1.0"; 239 method = "smc"; 240 }; 241 242 rpm: remoteproc { 243 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc"; 244 245 smd-edge { 246 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 247 mboxes = <&apcs 0>; 248 qcom,smd-edge = <15>; 249 250 rpm_requests: rpm-requests { 251 compatible = "qcom,rpm-msm8976", "qcom,smd-rpm"; 252 qcom,smd-channels = "rpm_requests"; 253 254 rpmcc: clock-controller { 255 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; 256 clocks = <&xo_board>; 257 clock-names = "xo"; 258 #clock-cells = <1>; 259 }; 260 261 rpmpd: power-controller { 262 compatible = "qcom,msm8976-rpmpd"; 263 #power-domain-cells = <1>; 264 operating-points-v2 = <&rpmpd_opp_table>; 265 266 rpmpd_opp_table: opp-table { 267 compatible = "operating-points-v2"; 268 269 rpmpd_opp_ret: opp1 { 270 opp-level = <RPM_SMD_LEVEL_RETENTION>; 271 }; 272 273 rpmpd_opp_ret_plus: opp2 { 274 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 275 }; 276 277 rpmpd_opp_min_svs: opp3 { 278 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 279 }; 280 281 rpmpd_opp_low_svs: opp4 { 282 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 283 }; 284 285 rpmpd_opp_svs: opp5 { 286 opp-level = <RPM_SMD_LEVEL_SVS>; 287 }; 288 289 rpmpd_opp_svs_plus: opp6 { 290 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 291 }; 292 293 rpmpd_opp_nom: opp7 { 294 opp-level = <RPM_SMD_LEVEL_NOM>; 295 }; 296 297 rpmpd_opp_nom_plus: opp8 { 298 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 299 }; 300 301 rpmpd_opp_turbo: opp9 { 302 opp-level = <RPM_SMD_LEVEL_TURBO>; 303 }; 304 305 rpmpd_opp_turbo_no_cpr: opp10 { 306 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 307 }; 308 309 rpmpd_opp_turbo_high: opp111 { 310 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; 311 }; 312 }; 313 }; 314 }; 315 }; 316 }; 317 318 reserved-memory { 319 #address-cells = <2>; 320 #size-cells = <2>; 321 ranges; 322 323 ext-region@85b00000 { 324 reg = <0x0 0x85b00000 0x0 0x500000>; 325 no-map; 326 }; 327 328 smem@86300000 { 329 compatible = "qcom,smem"; 330 reg = <0x0 0x86300000 0x0 0x100000>; 331 no-map; 332 333 hwlocks = <&tcsr_mutex 3>; 334 qcom,rpm-msg-ram = <&rpm_msg_ram>; 335 }; 336 337 reserved@86400000 { 338 reg = <0x0 0x86400000 0x0 0x800000>; 339 no-map; 340 }; 341 342 mpss_mem: mpss@86c00000 { 343 reg = <0x0 0x86c00000 0x0 0x5600000>; 344 no-map; 345 }; 346 347 lpass_mem: lpass@8c200000 { 348 reg = <0x0 0x8c200000 0x0 0x1000000>; 349 no-map; 350 }; 351 352 wcnss_fw_mem: wcnss@8d200000 { 353 reg = <0x0 0x8d200000 0x0 0x800000>; 354 no-map; 355 }; 356 357 venus_mem: memory@8da00000 { 358 reg = <0x0 0x8da00000 0x0 0x2600000>; 359 no-map; 360 }; 361 362 tz-apps@8dd00000 { 363 reg = <0x0 0x8dd00000 0x0 0x1400000>; 364 no-map; 365 }; 366 }; 367 368 smp2p-hexagon { 369 compatible = "qcom,smp2p"; 370 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 371 mboxes = <&apcs 10>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <2>; 375 qcom,smem = <443>, <429>; 376 377 adsp_smp2p_out: master-kernel { 378 qcom,entry-name = "master-kernel"; 379 380 #qcom,smem-state-cells = <1>; 381 }; 382 383 adsp_smp2p_in: slave-kernel { 384 qcom,entry-name = "slave-kernel"; 385 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smp2p-modem { 392 compatible = "qcom,smp2p"; 393 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&apcs 14>; 395 396 qcom,local-pid = <0>; 397 qcom,remote-pid = <1>; 398 qcom,smem = <435>, <428>; 399 400 modem_smp2p_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 403 #qcom,smem-state-cells = <1>; 404 }; 405 406 modem_smp2p_in: slave-kernel { 407 qcom,entry-name = "slave-kernel"; 408 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 }; 412 }; 413 414 smp2p-wcnss { 415 compatible = "qcom,smp2p"; 416 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 417 mboxes = <&apcs 18>; 418 419 qcom,local-pid = <0>; 420 qcom,remote-pid = <4>; 421 qcom,smem = <451>, <431>; 422 423 wcnss_smp2p_out: master-kernel { 424 qcom,entry-name = "master-kernel"; 425 426 #qcom,smem-state-cells = <1>; 427 }; 428 429 wcnss_smp2p_in: slave-kernel { 430 qcom,entry-name = "slave-kernel"; 431 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 }; 435 }; 436 437 smsm { 438 compatible = "qcom,smsm"; 439 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; 444 445 apps_smsm: apps@0 { 446 reg = <0>; 447 #qcom,smem-state-cells = <1>; 448 }; 449 450 hexagon_smsm: hexagon@1 { 451 reg = <1>; 452 interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 458 wcnss_smsm: wcnss@6 { 459 reg = <6>; 460 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 461 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 }; 465 }; 466 467 soc: soc@0 { 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0 0 0 0xffffffff>; 471 compatible = "simple-bus"; 472 473 rng@22000 { 474 compatible = "qcom,prng"; 475 reg = <0x00022000 0x140>; 476 clocks = <&gcc GCC_PRNG_AHB_CLK>; 477 clock-names = "core"; 478 }; 479 480 rpm_msg_ram: sram@60000 { 481 compatible = "qcom,rpm-msg-ram"; 482 reg = <0x00060000 0x8000>; 483 }; 484 485 usb_hs_phy: phy@6c000 { 486 compatible = "qcom,usb-hs-28nm-femtophy"; 487 reg = <0x0006c000 0x200>; 488 #phy-cells = <0>; 489 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 490 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 491 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 492 clock-names = "ref", "ahb", "sleep"; 493 resets = <&gcc RST_QUSB2_PHY_BCR>, 494 <&gcc RST_USB2_HS_PHY_ONLY_BCR>; 495 reset-names = "phy", "por"; 496 status = "disabled"; 497 }; 498 499 qfprom: qfprom@a4000 { 500 compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; 501 reg = <0x000a4000 0x1000>; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 505 tsens_base1: base1@218 { 506 reg = <0x218 1>; 507 bits = <0 8>; 508 }; 509 510 tsens_s0_p1: s0-p1@219 { 511 reg = <0x219 0x1>; 512 bits = <0 6>; 513 }; 514 515 tsens_s0_p2: s0-p2@219 { 516 reg = <0x219 0x2>; 517 bits = <6 6>; 518 }; 519 520 tsens_s1_p1: s1-p1@21a { 521 reg = <0x21a 0x2>; 522 bits = <4 6>; 523 }; 524 525 tsens_s1_p2: s1-p2@21b { 526 reg = <0x21b 0x1>; 527 bits = <2 6>; 528 }; 529 530 tsens_s2_p1: s2-p1@21c { 531 reg = <0x21c 0x1>; 532 bits = <0 6>; 533 }; 534 535 tsens_s2_p2: s2-p2@21c { 536 reg = <0x21c 0x2>; 537 bits = <6 6>; 538 }; 539 540 tsens_s3_p1: s3-p1@21d { 541 reg = <0x21d 0x2>; 542 bits = <4 6>; 543 }; 544 545 tsens_s3_p2: s3-p2@21e { 546 reg = <0x21e 0x1>; 547 bits = <2 6>; 548 }; 549 550 tsens_base2: base2@220 { 551 reg = <0x220 1>; 552 bits = <0 8>; 553 }; 554 555 tsens_s4_p1: s4-p1@221 { 556 reg = <0x221 0x1>; 557 bits = <0 6>; 558 }; 559 560 tsens_s4_p2: s4-p2@221 { 561 reg = <0x221 0x2>; 562 bits = <6 6>; 563 }; 564 565 tsens_s5_p1: s5-p1@222 { 566 reg = <0x222 0x2>; 567 bits = <4 6>; 568 }; 569 570 tsens_s5_p2: s5-p2@223 { 571 reg = <0x224 0x1>; 572 bits = <2 6>; 573 }; 574 575 tsens_s6_p1: s6-p1@224 { 576 reg = <0x224 0x1>; 577 bits = <0 6>; 578 }; 579 580 tsens_s6_p2: s6-p2@224 { 581 reg = <0x224 0x2>; 582 bits = <6 6>; 583 }; 584 585 tsens_s7_p1: s7-p1@225 { 586 reg = <0x225 0x2>; 587 bits = <4 6>; 588 }; 589 590 tsens_s7_p2: s7-p2@226 { 591 reg = <0x226 0x2>; 592 bits = <2 6>; 593 }; 594 595 tsens_mode: mode@228 { 596 reg = <0x228 1>; 597 bits = <0 3>; 598 }; 599 600 tsens_s8_p1: s8-p1@228 { 601 reg = <0x228 0x2>; 602 bits = <3 6>; 603 }; 604 605 tsens_s8_p2: s8-p2@229 { 606 reg = <0x229 0x1>; 607 bits = <1 6>; 608 }; 609 610 tsens_s9_p1: s9-p1@229 { 611 reg = <0x229 0x2>; 612 bits = <7 6>; 613 }; 614 615 tsens_s9_p2: s9-p2@22a { 616 reg = <0x22a 0x2>; 617 bits = <5 6>; 618 }; 619 620 tsens_s10_p1: s10-p1@22b { 621 reg = <0x22b 0x2>; 622 bits = <3 6>; 623 }; 624 625 tsens_s10_p2: s10-p2@22c { 626 reg = <0x22c 0x1>; 627 bits = <1 6>; 628 }; 629 }; 630 631 tsens: thermal-sensor@4a9000 { 632 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; 633 reg = <0x004a9000 0x1000>, /* TM */ 634 <0x004a8000 0x1000>; /* SROT */ 635 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "uplow"; 637 nvmem-cells = <&tsens_mode>, 638 <&tsens_base1>, <&tsens_base2>, 639 <&tsens_s0_p1>, <&tsens_s0_p2>, 640 <&tsens_s1_p1>, <&tsens_s1_p2>, 641 <&tsens_s2_p1>, <&tsens_s2_p2>, 642 <&tsens_s3_p1>, <&tsens_s3_p2>, 643 <&tsens_s4_p1>, <&tsens_s4_p2>, 644 <&tsens_s5_p1>, <&tsens_s5_p2>, 645 <&tsens_s6_p1>, <&tsens_s6_p2>, 646 <&tsens_s7_p1>, <&tsens_s7_p2>, 647 <&tsens_s8_p1>, <&tsens_s8_p2>, 648 <&tsens_s9_p1>, <&tsens_s9_p2>, 649 <&tsens_s10_p1>, <&tsens_s10_p2>; 650 nvmem-cell-names = "mode", 651 "base1", "base2", 652 "s0_p1", "s0_p2", 653 "s1_p1", "s1_p2", 654 "s2_p1", "s2_p2", 655 "s3_p1", "s3_p2", 656 "s4_p1", "s4_p2", 657 "s5_p1", "s5_p2", 658 "s6_p1", "s6_p2", 659 "s7_p1", "s7_p2", 660 "s8_p1", "s8_p2", 661 "s9_p1", "s9_p2", 662 "s10_p1", "s10_p2"; 663 #qcom,sensors = <11>; 664 #thermal-sensor-cells = <1>; 665 }; 666 667 restart@4ab000 { 668 compatible = "qcom,pshold"; 669 reg = <0x004ab000 0x4>; 670 }; 671 672 tlmm: pinctrl@1000000 { 673 compatible = "qcom,msm8976-pinctrl"; 674 reg = <0x01000000 0x300000>; 675 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 676 #gpio-cells = <2>; 677 gpio-controller; 678 gpio-ranges = <&tlmm 0 0 145>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 682 spi1_default: spi0-default-state { 683 spi-pins { 684 pins = "gpio0", "gpio1", "gpio3"; 685 function = "blsp_spi1"; 686 drive-strength = <12>; 687 bias-disable; 688 }; 689 690 cs-pins { 691 pins = "gpio2"; 692 function = "blsp_spi1"; 693 drive-strength = <2>; 694 bias-disable; 695 }; 696 }; 697 698 spi1_sleep: spi0-sleep-state { 699 spi-pins { 700 pins = "gpio0", "gpio1", "gpio3"; 701 function = "gpio"; 702 drive-strength = <2>; 703 bias-pull-down; 704 }; 705 706 cs-pins { 707 pins = "gpio2"; 708 function = "gpio"; 709 drive-strength = <2>; 710 bias-disable; 711 }; 712 }; 713 714 blsp1_i2c2_default: blsp1-i2c2-default-state { 715 pins = "gpio6", "gpio7"; 716 function = "blsp_i2c2"; 717 drive-strength = <2>; 718 bias-disable; 719 }; 720 721 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 722 pins = "gpio6", "gpio7"; 723 function = "gpio"; 724 drive-strength = <2>; 725 bias-disable; 726 }; 727 728 blsp1_i2c4_default: blsp1-i2c4-default-state { 729 pins = "gpio14", "gpio15"; 730 function = "blsp_i2c4"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 736 pins = "gpio14", "gpio15"; 737 function = "gpio"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 blsp2_uart2_active: blsp2-uart2-active-state { 743 pins = "gpio20", "gpio21"; 744 function = "blsp_uart6"; 745 drive-strength = <4>; 746 bias-disable; 747 }; 748 749 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 750 pins = "gpio20", "gpio21"; 751 function = "gpio"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ 757 blsp2_i2c2_default: blsp2-i2c2-default-state { 758 pins = "gpio22", "gpio23"; 759 function = "blsp_i2c6"; 760 drive-strength = <2>; 761 bias-disable; 762 }; 763 764 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 765 pins = "gpio22", "gpio23"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-disable; 769 }; 770 771 blsp2_i2c4_default: blsp2-i2c4-default-state { 772 pins = "gpio18", "gpio19"; 773 function = "blsp_i2c8"; 774 drive-strength = <2>; 775 bias-disable; 776 }; 777 778 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 779 pins = "gpio18", "gpio19"; 780 function = "gpio"; 781 drive-strength = <2>; 782 bias-disable; 783 }; 784 785 sdc2_default: sdc2-default-state { 786 clk-pins { 787 pins = "sdc2_clk"; 788 bias-disable; 789 drive-strength = <16>; 790 }; 791 cmd-pins { 792 pins = "sdc2_cmd"; 793 bias-pull-up; 794 drive-strength = <10>; 795 }; 796 data-pins { 797 pins = "sdc2_data"; 798 bias-pull-up; 799 drive-strength = <10>; 800 }; 801 }; 802 803 sdc2_sleep: sdc2-sleep-state { 804 clk-pins { 805 pins = "sdc2_clk"; 806 bias-disable; 807 drive-strength = <2>; 808 }; 809 cmd-pins { 810 pins = "sdc2_cmd"; 811 bias-pull-up; 812 drive-strength = <2>; 813 }; 814 data-pins { 815 pins = "sdc2_data"; 816 bias-pull-up; 817 drive-strength = <2>; 818 }; 819 }; 820 821 wcss_wlan_default: wcss-wlan-default-state { 822 wcss-wlan2-pins { 823 pins = "gpio40"; 824 function = "wcss_wlan2"; 825 drive-strength = <6>; 826 bias-pull-up; 827 }; 828 829 wcss-wlan1-pins { 830 pins = "gpio41"; 831 function = "wcss_wlan1"; 832 drive-strength = <6>; 833 bias-pull-up; 834 }; 835 836 wcss-wlan0-pins { 837 pins = "gpio42"; 838 function = "wcss_wlan0"; 839 drive-strength = <6>; 840 bias-pull-up; 841 }; 842 843 wcss-wlan-pins { 844 pins = "gpio43", "gpio44"; 845 function = "wcss_wlan"; 846 drive-strength = <6>; 847 bias-pull-up; 848 }; 849 }; 850 }; 851 852 gcc: clock-controller@1800000 { 853 compatible = "qcom,gcc-msm8976"; 854 reg = <0x01800000 0x80000>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 #power-domain-cells = <1>; 858 859 assigned-clocks = <&gcc GPLL3>; 860 assigned-clock-rates = <1100000000>; 861 862 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 863 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 864 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 865 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 866 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 867 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 868 clock-names = "xo", 869 "xo_a", 870 "dsi0pll", 871 "dsi0pllbyte", 872 "dsi1pll", 873 "dsi1pllbyte"; 874 }; 875 876 tcsr_mutex: hwlock@1905000 { 877 compatible = "qcom,tcsr-mutex"; 878 reg = <0x01905000 0x20000>; 879 #hwlock-cells = <1>; 880 }; 881 882 tcsr: syscon@1937000 { 883 compatible = "qcom,msm8976-tcsr", "syscon"; 884 reg = <0x01937000 0x30000>; 885 }; 886 887 mdss: display-subsystem@1a00000 { 888 compatible = "qcom,mdss"; 889 890 reg = <0x01a00000 0x1000>, 891 <0x01ab0000 0x3000>; 892 reg-names = "mdss_phys", "vbif_phys"; 893 894 power-domains = <&gcc MDSS_GDSC>; 895 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 896 897 interrupt-controller; 898 #interrupt-cells = <1>; 899 900 clocks = <&gcc GCC_MDSS_AHB_CLK>, 901 <&gcc GCC_MDSS_AXI_CLK>, 902 <&gcc GCC_MDSS_VSYNC_CLK>, 903 <&gcc GCC_MDSS_MDP_CLK>; 904 clock-names = "iface", 905 "bus", 906 "vsync", 907 "core"; 908 909 #address-cells = <1>; 910 #size-cells = <1>; 911 ranges; 912 913 status = "disabled"; 914 915 mdss_mdp: display-controller@1a01000 { 916 compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; 917 reg = <0x01a01000 0x89000>; 918 reg-names = "mdp_phys"; 919 920 interrupt-parent = <&mdss>; 921 interrupts = <0>; 922 923 clocks = <&gcc GCC_MDSS_AHB_CLK>, 924 <&gcc GCC_MDSS_AXI_CLK>, 925 <&gcc GCC_MDSS_MDP_CLK>, 926 <&gcc GCC_MDSS_VSYNC_CLK>, 927 <&gcc GCC_MDP_TBU_CLK>, 928 <&gcc GCC_MDP_RT_TBU_CLK>; 929 clock-names = "iface", 930 "bus", 931 "core", 932 "vsync", 933 "tbu", 934 "tbu_rt"; 935 936 operating-points-v2 = <&mdp_opp_table>; 937 power-domains = <&gcc MDSS_GDSC>; 938 939 iommus = <&apps_iommu 22>; 940 941 ports { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 945 port@0 { 946 reg = <0>; 947 948 mdss_mdp5_intf1_out: endpoint { 949 remote-endpoint = <&mdss_dsi0_in>; 950 }; 951 }; 952 953 port@1 { 954 reg = <1>; 955 956 mdss_mdp5_intf2_out: endpoint { 957 remote-endpoint = <&mdss_dsi1_in>; 958 }; 959 }; 960 }; 961 962 mdp_opp_table: opp-table { 963 compatible = "operating-points-v2"; 964 965 opp-177780000 { 966 opp-hz = /bits/ 64 <177780000>; 967 required-opps = <&rpmpd_opp_svs>; 968 }; 969 970 opp-270000000 { 971 opp-hz = /bits/ 64 <270000000>; 972 required-opps = <&rpmpd_opp_svs_plus>; 973 }; 974 975 opp-320000000 { 976 opp-hz = /bits/ 64 <320000000>; 977 required-opps = <&rpmpd_opp_nom>; 978 }; 979 980 opp-360000000 { 981 opp-hz = /bits/ 64 <360000000>; 982 required-opps = <&rpmpd_opp_turbo>; 983 }; 984 }; 985 }; 986 987 mdss_dsi0: dsi@1a94000 { 988 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 989 reg = <0x01a94000 0x300>; 990 reg-names = "dsi_ctrl"; 991 992 interrupt-parent = <&mdss>; 993 interrupts = <4>; 994 995 clocks = <&gcc GCC_MDSS_MDP_CLK>, 996 <&gcc GCC_MDSS_AHB_CLK>, 997 <&gcc GCC_MDSS_AXI_CLK>, 998 <&gcc GCC_MDSS_BYTE0_CLK>, 999 <&gcc GCC_MDSS_PCLK0_CLK>, 1000 <&gcc GCC_MDSS_ESC0_CLK>; 1001 clock-names = "mdp_core", 1002 "iface", 1003 "bus", 1004 "byte", 1005 "pixel", 1006 "core"; 1007 1008 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, 1009 <&gcc GCC_MDSS_PCLK0_CLK_SRC>; 1010 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1011 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1012 1013 phys = <&mdss_dsi0_phy>; 1014 1015 operating-points-v2 = <&dsi0_opp_table>; 1016 power-domains = <&gcc MDSS_GDSC>; 1017 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 status = "disabled"; 1022 1023 ports { 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 1027 port@0 { 1028 reg = <0>; 1029 1030 mdss_dsi0_in: endpoint { 1031 remote-endpoint = <&mdss_mdp5_intf1_out>; 1032 }; 1033 }; 1034 1035 port@1 { 1036 reg = <1>; 1037 1038 mdss_dsi0_out: endpoint { 1039 }; 1040 }; 1041 }; 1042 1043 dsi0_opp_table: opp-table { 1044 compatible = "operating-points-v2"; 1045 1046 opp-125000000 { 1047 opp-hz = /bits/ 64 <125000000>; 1048 required-opps = <&rpmpd_opp_svs>; 1049 }; 1050 1051 opp-161250000 { 1052 opp-hz = /bits/ 64 <161250000>; 1053 required-opps = <&rpmpd_opp_svs_plus>; 1054 }; 1055 1056 opp-187500000 { 1057 opp-hz = /bits/ 64 <187500000>; 1058 required-opps = <&rpmpd_opp_nom>; 1059 }; 1060 }; 1061 }; 1062 1063 mdss_dsi1: dsi@1a96000 { 1064 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1065 reg = <0x01a96000 0x300>; 1066 reg-names = "dsi_ctrl"; 1067 1068 interrupt-parent = <&mdss>; 1069 interrupts = <5>; 1070 1071 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1072 <&gcc GCC_MDSS_AHB_CLK>, 1073 <&gcc GCC_MDSS_AXI_CLK>, 1074 <&gcc GCC_MDSS_BYTE1_CLK>, 1075 <&gcc GCC_MDSS_PCLK1_CLK>, 1076 <&gcc GCC_MDSS_ESC1_CLK>; 1077 clock-names = "mdp_core", 1078 "iface", 1079 "bus", 1080 "byte", 1081 "pixel", 1082 "core"; 1083 1084 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, 1085 <&gcc GCC_MDSS_PCLK1_CLK_SRC>; 1086 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1087 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1088 1089 phys = <&mdss_dsi1_phy>; 1090 1091 operating-points-v2 = <&dsi0_opp_table>; 1092 power-domains = <&gcc MDSS_GDSC>; 1093 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 status = "disabled"; 1098 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 reg = <0>; 1105 1106 mdss_dsi1_in: endpoint { 1107 remote-endpoint = <&mdss_mdp5_intf2_out>; 1108 }; 1109 }; 1110 1111 port@1 { 1112 reg = <1>; 1113 1114 mdss_dsi1_out: endpoint { 1115 }; 1116 }; 1117 }; 1118 }; 1119 1120 mdss_dsi0_phy: phy@1a94a00 { 1121 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1122 reg = <0x01a94a00 0xd4>, 1123 <0x01a94400 0x280>, 1124 <0x01a94b80 0x30>; 1125 reg-names = "dsi_pll", 1126 "dsi_phy", 1127 "dsi_phy_regulator"; 1128 1129 #clock-cells = <1>; 1130 #phy-cells = <0>; 1131 1132 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1133 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1134 clock-names = "iface", "ref"; 1135 1136 status = "disabled"; 1137 }; 1138 1139 mdss_dsi1_phy: phy@1a96a00 { 1140 compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; 1141 reg = <0x01a96a00 0xd4>, 1142 <0x01a96400 0x280>, 1143 <0x01a96b80 0x30>; 1144 reg-names = "dsi_pll", 1145 "dsi_phy", 1146 "dsi_phy_regulator"; 1147 1148 #clock-cells = <1>; 1149 #phy-cells = <0>; 1150 1151 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1152 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1153 clock-names = "iface", "ref"; 1154 1155 status = "disabled"; 1156 }; 1157 }; 1158 1159 adreno_gpu: gpu@1c00000 { 1160 compatible = "qcom,adreno-510.0", "qcom,adreno"; 1161 1162 reg = <0x01c00000 0x40000>; 1163 reg-names = "kgsl_3d0_reg_memory"; 1164 1165 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1166 interrupt-names = "kgsl_3d0_irq"; 1167 1168 clocks = <&gcc GCC_GFX3D_OXILI_CLK>, 1169 <&gcc GCC_GFX3D_OXILI_AHB_CLK>, 1170 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, 1171 <&gcc GCC_GFX3D_BIMC_CLK>, 1172 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, 1173 <&gcc GCC_GFX3D_OXILI_AON_CLK>; 1174 clock-names = "core", 1175 "iface", 1176 "mem", 1177 "mem_iface", 1178 "rbbmtimer", 1179 "alwayson"; 1180 1181 power-domains = <&gcc OXILI_GX_GDSC>; 1182 1183 iommus = <&gpu_iommu 0>; 1184 1185 operating-points-v2 = <&gpu_opp_table>; 1186 1187 status = "disabled"; 1188 1189 gpu_opp_table: opp-table { 1190 compatible = "operating-points-v2"; 1191 1192 opp-200000000 { 1193 opp-hz = /bits/ 64 <200000000>; 1194 required-opps = <&rpmpd_opp_low_svs>; 1195 opp-supported-hw = <0xff>; 1196 }; 1197 1198 opp-300000000 { 1199 opp-hz = /bits/ 64 <300000000>; 1200 required-opps = <&rpmpd_opp_svs>; 1201 opp-supported-hw = <0xff>; 1202 }; 1203 1204 opp-400000000 { 1205 opp-hz = /bits/ 64 <400000000>; 1206 required-opps = <&rpmpd_opp_nom>; 1207 opp-supported-hw = <0xff>; 1208 }; 1209 1210 opp-480000000 { 1211 opp-hz = /bits/ 64 <480000000>; 1212 required-opps = <&rpmpd_opp_nom_plus>; 1213 opp-supported-hw = <0xff>; 1214 }; 1215 1216 opp-540000000 { 1217 opp-hz = /bits/ 64 <540000000>; 1218 required-opps = <&rpmpd_opp_turbo>; 1219 opp-supported-hw = <0xff>; 1220 }; 1221 1222 opp-600000000 { 1223 opp-hz = /bits/ 64 <600000000>; 1224 required-opps = <&rpmpd_opp_turbo>; 1225 opp-supported-hw = <0xff>; 1226 }; 1227 }; 1228 }; 1229 1230 apps_iommu: iommu@1ee0000 { 1231 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1232 reg = <0x01ee0000 0x3000>; 1233 ranges = <0 0x01e20000 0x20000>; 1234 1235 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1236 <&gcc GCC_APSS_TCU_CLK>; 1237 clock-names = "iface", "bus"; 1238 1239 qcom,iommu-secure-id = <17>; 1240 1241 #address-cells = <1>; 1242 #size-cells = <1>; 1243 #iommu-cells = <1>; 1244 1245 /* VFE */ 1246 iommu-ctx@15000 { 1247 compatible = "qcom,msm-iommu-v2-ns"; 1248 reg = <0x15000 0x1000>; 1249 qcom,ctx-asid = <20>; 1250 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1251 }; 1252 1253 /* VENUS NS */ 1254 iommu-ctx@16000 { 1255 compatible = "qcom,msm-iommu-v2-ns"; 1256 reg = <0x16000 0x1000>; 1257 qcom,ctx-asid = <21>; 1258 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1259 }; 1260 1261 /* MDP0 */ 1262 iommu-ctx@17000 { 1263 compatible = "qcom,msm-iommu-v2-ns"; 1264 reg = <0x17000 0x1000>; 1265 qcom,ctx-asid = <22>; 1266 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1267 }; 1268 }; 1269 1270 gpu_iommu: iommu@1f08000 { 1271 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; 1272 ranges = <0 0x01f08000 0x8000>; 1273 1274 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1275 <&gcc GCC_GFX3D_TCU_CLK>; 1276 clock-names = "iface", "bus"; 1277 1278 power-domains = <&gcc OXILI_CX_GDSC>; 1279 1280 qcom,iommu-secure-id = <18>; 1281 1282 #address-cells = <1>; 1283 #size-cells = <1>; 1284 #iommu-cells = <1>; 1285 1286 /* gfx3d user */ 1287 iommu-ctx@0 { 1288 compatible = "qcom,msm-iommu-v2-ns"; 1289 reg = <0x0 0x1000>; 1290 qcom,ctx-asid = <0>; 1291 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1292 }; 1293 1294 /* gfx3d secure */ 1295 iommu-ctx@1000 { 1296 compatible = "qcom,msm-iommu-v2-sec"; 1297 reg = <0x1000 0x1000>; 1298 qcom,ctx-asid = <2>; 1299 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1300 }; 1301 1302 /* gfx3d priv */ 1303 iommu-ctx@2000 { 1304 compatible = "qcom,msm-iommu-v2-sec"; 1305 reg = <0x2000 0x1000>; 1306 qcom,ctx-asid = <1>; 1307 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1308 }; 1309 }; 1310 1311 spmi_bus: spmi@200f000 { 1312 compatible = "qcom,spmi-pmic-arb"; 1313 reg = <0x0200f000 0x1000>, 1314 <0x02400000 0x800000>, 1315 <0x02c00000 0x800000>, 1316 <0x03800000 0x200000>, 1317 <0x0200a000 0x2100>; 1318 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1319 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1320 interrupt-names = "periph_irq"; 1321 qcom,channel = <0>; 1322 qcom,ee = <0>; 1323 1324 #address-cells = <2>; 1325 #size-cells = <0>; 1326 interrupt-controller; 1327 #interrupt-cells = <4>; 1328 }; 1329 1330 sdhc_1: mmc@7824900 { 1331 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1332 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1333 reg-names = "hc", "core"; 1334 1335 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1337 interrupt-names = "hc_irq", "pwr_irq"; 1338 1339 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1340 <&gcc GCC_SDCC1_APPS_CLK>, 1341 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1342 clock-names = "iface", "core", "xo"; 1343 status = "disabled"; 1344 }; 1345 1346 sdhc_2: mmc@7864900 { 1347 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1348 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1349 reg-names = "hc", "core"; 1350 1351 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "hc_irq", "pwr_irq"; 1354 1355 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1356 <&gcc GCC_SDCC2_APPS_CLK>, 1357 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1358 clock-names = "iface", "core", "xo"; 1359 status = "disabled"; 1360 }; 1361 1362 blsp1_dma: dma-controller@7884000 { 1363 compatible = "qcom,bam-v1.7.0"; 1364 reg = <0x07884000 0x1f000>; 1365 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1366 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1367 clock-names = "bam_clk"; 1368 #dma-cells = <1>; 1369 qcom,ee = <0>; 1370 qcom,controlled-remotely; 1371 }; 1372 1373 blsp1_uart1: serial@78af000 { 1374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1375 reg = <0x078af000 0x200>; 1376 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1377 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1378 clock-names = "core", "iface"; 1379 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1380 dma-names = "tx", "rx"; 1381 status = "disabled"; 1382 }; 1383 1384 blsp1_uart2: serial@78b0000 { 1385 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1386 reg = <0x078b0000 0x200>; 1387 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1389 clock-names = "core", "iface"; 1390 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1391 dma-names = "tx", "rx"; 1392 status = "disabled"; 1393 }; 1394 1395 blsp1_spi1: spi@78b5000 { 1396 compatible = "qcom,spi-qup-v2.2.1"; 1397 reg = <0x078b5000 0x500>; 1398 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1400 clock-names = "core", "iface"; 1401 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1402 dma-names = "tx", "rx"; 1403 pinctrl-names = "default", "sleep"; 1404 pinctrl-0 = <&spi1_default>; 1405 pinctrl-1 = <&spi1_sleep>; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 status = "disabled"; 1409 }; 1410 1411 blsp1_i2c2: i2c@78b6000 { 1412 compatible = "qcom,i2c-qup-v2.2.1"; 1413 reg = <0x078b6000 0x500>; 1414 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1415 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1416 clock-names = "core", "iface"; 1417 clock-frequency = <400000>; 1418 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1419 dma-names = "tx", "rx"; 1420 pinctrl-names = "default", "sleep"; 1421 pinctrl-0 = <&blsp1_i2c2_default>; 1422 pinctrl-1 = <&blsp1_i2c2_default>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 blsp1_i2c4: i2c@78b8000 { 1429 compatible = "qcom,i2c-qup-v2.2.1"; 1430 reg = <0x078b8000 0x500>; 1431 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1433 clock-names = "core", "iface"; 1434 clock-frequency = <400000>; 1435 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1436 dma-names = "tx", "rx"; 1437 pinctrl-names = "default", "sleep"; 1438 pinctrl-0 = <&blsp1_i2c4_default>; 1439 pinctrl-1 = <&blsp1_i2c4_sleep>; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 otg: usb@78db000 { 1446 compatible = "qcom,ci-hdrc"; 1447 reg = <0x078db000 0x200>, 1448 <0x078db200 0x200>; 1449 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1451 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; 1452 clock-names = "iface", "core"; 1453 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1454 assigned-clock-rates = <80000000>; 1455 resets = <&gcc RST_USB_HS_BCR>; 1456 reset-names = "core"; 1457 ahb-burst-config = <0>; 1458 dr_mode = "peripheral"; 1459 phy_type = "ulpi"; 1460 phy-names = "usb-phy"; 1461 phys = <&usb_hs_phy>; 1462 status = "disabled"; 1463 #reset-cells = <1>; 1464 }; 1465 1466 sdhc_3: mmc@7a24900 { 1467 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; 1468 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; 1469 reg-names = "hc", "core"; 1470 1471 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1473 interrupt-names = "hc_irq", "pwr_irq"; 1474 1475 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 1476 <&gcc GCC_SDCC3_APPS_CLK>, 1477 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1478 clock-names = "iface", "core", "xo"; 1479 1480 status = "disabled"; 1481 }; 1482 1483 blsp2_dma: dma-controller@7ac4000 { 1484 compatible = "qcom,bam-v1.7.0"; 1485 reg = <0x07ac4000 0x1f000>; 1486 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1488 clock-names = "bam_clk"; 1489 #dma-cells = <1>; 1490 qcom,ee = <0>; 1491 qcom,controlled-remotely; 1492 }; 1493 1494 blsp2_uart2: serial@7af0000 { 1495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1496 reg = <0x07af0000 0x200>; 1497 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1499 clock-names = "core", "iface"; 1500 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1501 dma-names = "tx", "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 blsp2_i2c2: i2c@7af6000 { 1506 compatible = "qcom,i2c-qup-v2.2.1"; 1507 reg = <0x07af6000 0x600>; 1508 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1510 clock-names = "core", "iface"; 1511 clock-frequency = <400000>; 1512 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1513 dma-names = "tx", "rx"; 1514 pinctrl-names = "default", "sleep"; 1515 pinctrl-0 = <&blsp2_i2c2_default>; 1516 pinctrl-1 = <&blsp2_i2c2_sleep>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 status = "disabled"; 1520 }; 1521 1522 blsp2_i2c4: i2c@7af8000 { 1523 compatible = "qcom,i2c-qup-v2.2.1"; 1524 reg = <0x07af8000 0x600>; 1525 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1527 clock-names = "core", "iface"; 1528 clock-frequency = <400000>; 1529 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1530 dma-names = "tx", "rx"; 1531 pinctrl-names = "default", "sleep"; 1532 pinctrl-0 = <&blsp2_i2c4_default>; 1533 pinctrl-1 = <&blsp2_i2c4_sleep>; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 status = "disabled"; 1537 }; 1538 1539 wcnss: remoteproc@a204000 { 1540 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1541 reg = <0x0a204000 0x2000>, 1542 <0x0a202000 0x1000>, 1543 <0x0a21b000 0x3000>; 1544 reg-names = "ccu", 1545 "dxe", 1546 "pmu"; 1547 1548 memory-region = <&wcnss_fw_mem>; 1549 1550 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1551 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1552 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1553 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1554 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1555 interrupt-names = "wdog", 1556 "fatal", 1557 "ready", 1558 "handover", 1559 "stop-ack"; 1560 1561 power-domains = <&rpmpd MSM8976_VDDCX>, 1562 <&rpmpd MSM8976_VDDMX>; 1563 power-domain-names = "cx", "mx"; 1564 1565 qcom,smem-states = <&wcnss_smp2p_out 0>; 1566 qcom,smem-state-names = "stop"; 1567 1568 pinctrl-0 = <&wcss_wlan_default>; 1569 pinctrl-names = "default"; 1570 1571 status = "disabled"; 1572 1573 wcnss_iris: iris { 1574 /* Separate chip, compatible is board-specific */ 1575 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1576 clock-names = "xo"; 1577 }; 1578 1579 smd-edge { 1580 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1581 1582 mboxes = <&apcs 17>; 1583 qcom,smd-edge = <6>; 1584 qcom,remote-pid = <4>; 1585 1586 label = "pronto"; 1587 1588 wcnss_ctrl: wcnss { 1589 compatible = "qcom,wcnss"; 1590 qcom,smd-channels = "WCNSS_CTRL"; 1591 1592 qcom,mmio = <&wcnss>; 1593 1594 wcnss_bt: bluetooth { 1595 compatible = "qcom,wcnss-bt"; 1596 }; 1597 1598 wcnss_wifi: wifi { 1599 compatible = "qcom,wcnss-wlan"; 1600 1601 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1603 interrupt-names = "tx", "rx"; 1604 1605 qcom,smem-states = <&apps_smsm 10>, 1606 <&apps_smsm 9>; 1607 qcom,smem-state-names = "tx-enable", 1608 "tx-rings-empty"; 1609 }; 1610 }; 1611 }; 1612 }; 1613 1614 intc: interrupt-controller@b000000 { 1615 compatible = "qcom,msm-qgic2"; 1616 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1617 interrupt-controller; 1618 #interrupt-cells = <3>; 1619 }; 1620 1621 apcs: mailbox@b011000 { 1622 compatible = "qcom,msm8976-apcs-kpss-global", 1623 "qcom,msm8994-apcs-kpss-global", "syscon"; 1624 reg = <0x0b011000 0x1000>; 1625 #mbox-cells = <1>; 1626 }; 1627 1628 timer@b120000 { 1629 compatible = "arm,armv7-timer-mem"; 1630 reg = <0x0b120000 0x1000>; 1631 #address-cells = <1>; 1632 #size-cells = <1>; 1633 ranges; 1634 clock-frequency = <19200000>; 1635 1636 frame@b121000 { 1637 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; 1638 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1640 frame-number = <0>; 1641 }; 1642 1643 frame@b123000 { 1644 reg = <0x0b123000 0x1000>; 1645 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1646 frame-number = <1>; 1647 status = "disabled"; 1648 }; 1649 1650 frame@b124000 { 1651 reg = <0x0b124000 0x1000>; 1652 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1653 frame-number = <2>; 1654 status = "disabled"; 1655 }; 1656 1657 frame@b125000 { 1658 reg = <0x0b125000 0x1000>; 1659 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1660 frame-number = <3>; 1661 status = "disabled"; 1662 }; 1663 1664 frame@b126000 { 1665 reg = <0x0b126000 0x1000>; 1666 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1667 frame-number = <4>; 1668 status = "disabled"; 1669 }; 1670 1671 frame@b127000 { 1672 reg = <0x0b127000 0x1000>; 1673 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1674 frame-number = <5>; 1675 status = "disabled"; 1676 }; 1677 1678 frame@b128000 { 1679 reg = <0x0b128000 0x1000>; 1680 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1681 frame-number = <6>; 1682 status = "disabled"; 1683 }; 1684 }; 1685 1686 imem: sram@8600000 { 1687 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; 1688 reg = <0x08600000 0x1000>; 1689 #address-cells = <1>; 1690 #size-cells = <1>; 1691 1692 ranges = <0 0x08600000 0x1000>; 1693 1694 pil-reloc@94c { 1695 compatible = "qcom,pil-reloc-info"; 1696 reg = <0x94c 0xc8>; 1697 }; 1698 }; 1699 }; 1700 1701 thermal-zones { 1702 aoss0-thermal { 1703 polling-delay-passive = <250>; 1704 1705 thermal-sensors = <&tsens 0>; 1706 1707 trips { 1708 aoss0_alert0: trip-point0 { 1709 temperature = <75000>; 1710 hysteresis = <2000>; 1711 type = "hot"; 1712 }; 1713 }; 1714 }; 1715 1716 modem-thermal { 1717 polling-delay-passive = <250>; 1718 1719 thermal-sensors = <&tsens 1>; 1720 trips { 1721 modem_alert0: trip-point0 { 1722 temperature = <75000>; 1723 hysteresis = <2000>; 1724 type = "hot"; 1725 }; 1726 }; 1727 }; 1728 1729 qdsp-thermal { 1730 polling-delay-passive = <250>; 1731 1732 thermal-sensors = <&tsens 2>; 1733 trips { 1734 qdsp_alert0: trip-point0 { 1735 temperature = <75000>; 1736 hysteresis = <2000>; 1737 type = "hot"; 1738 }; 1739 }; 1740 }; 1741 1742 cam-isp-thermal { 1743 polling-delay-passive = <250>; 1744 1745 thermal-sensors = <&tsens 3>; 1746 trips { 1747 cam_isp_alert0: trip-point0 { 1748 temperature = <75000>; 1749 hysteresis = <2000>; 1750 type = "hot"; 1751 }; 1752 }; 1753 }; 1754 1755 cpu4-thermal { 1756 polling-delay-passive = <250>; 1757 1758 thermal-sensors = <&tsens 4>; 1759 1760 trips { 1761 cpu4_alert0: trip-point0 { 1762 temperature = <50000>; 1763 hysteresis = <2000>; 1764 type = "hot"; 1765 }; 1766 cpu4_alert1: trip-point1 { 1767 temperature = <55000>; 1768 hysteresis = <2000>; 1769 type = "passive"; 1770 }; 1771 cpu4_crit: cpu-crit { 1772 temperature = <75000>; 1773 hysteresis = <2000>; 1774 type = "critical"; 1775 }; 1776 }; 1777 }; 1778 1779 cpu5-thermal { 1780 polling-delay-passive = <250>; 1781 1782 thermal-sensors = <&tsens 5>; 1783 1784 trips { 1785 cpu5_alert0: trip-point0 { 1786 temperature = <50000>; 1787 hysteresis = <2000>; 1788 type = "hot"; 1789 }; 1790 cpu5_alert1: trip-point1 { 1791 temperature = <55000>; 1792 hysteresis = <2000>; 1793 type = "passive"; 1794 }; 1795 cpu5_crit: cpu-crit { 1796 temperature = <75000>; 1797 hysteresis = <2000>; 1798 type = "critical"; 1799 }; 1800 }; 1801 }; 1802 1803 cpu6-thermal { 1804 polling-delay-passive = <250>; 1805 1806 thermal-sensors = <&tsens 6>; 1807 1808 trips { 1809 cpu6_alert0: trip-point0 { 1810 temperature = <50000>; 1811 hysteresis = <2000>; 1812 type = "hot"; 1813 }; 1814 cpu6_alert1: trip-point1 { 1815 temperature = <55000>; 1816 hysteresis = <2000>; 1817 type = "passive"; 1818 }; 1819 cpu6_crit: cpu-crit { 1820 temperature = <75000>; 1821 hysteresis = <2000>; 1822 type = "critical"; 1823 }; 1824 }; 1825 }; 1826 1827 cpu7-thermal { 1828 polling-delay-passive = <250>; 1829 1830 thermal-sensors = <&tsens 7>; 1831 1832 trips { 1833 cpu7_alert0: trip-point0 { 1834 temperature = <50000>; 1835 hysteresis = <2000>; 1836 type = "hot"; 1837 }; 1838 cpu7_alert1: trip-point1 { 1839 temperature = <55000>; 1840 hysteresis = <2000>; 1841 type = "passive"; 1842 }; 1843 cpu7_crit: cpu-crit { 1844 temperature = <75000>; 1845 hysteresis = <2000>; 1846 type = "critical"; 1847 }; 1848 }; 1849 }; 1850 1851 big-l2-thermal { 1852 polling-delay-passive = <250>; 1853 1854 thermal-sensors = <&tsens 8>; 1855 1856 trips { 1857 l2_alert0: trip-point0 { 1858 temperature = <50000>; 1859 hysteresis = <2000>; 1860 type = "hot"; 1861 }; 1862 l2_alert1: trip-point1 { 1863 temperature = <55000>; 1864 hysteresis = <2000>; 1865 type = "passive"; 1866 }; 1867 l2_crit: l2-crit { 1868 temperature = <75000>; 1869 hysteresis = <2000>; 1870 type = "critical"; 1871 }; 1872 }; 1873 }; 1874 1875 cpu0-thermal { 1876 polling-delay-passive = <250>; 1877 1878 thermal-sensors = <&tsens 9>; 1879 1880 trips { 1881 cpu0_alert0: trip-point0 { 1882 temperature = <50000>; 1883 hysteresis = <2000>; 1884 type = "hot"; 1885 }; 1886 cpu0_alert1: trip-point1 { 1887 temperature = <55000>; 1888 hysteresis = <2000>; 1889 type = "passive"; 1890 }; 1891 cpu0_crit: cpu-crit { 1892 temperature = <75000>; 1893 hysteresis = <2000>; 1894 type = "critical"; 1895 }; 1896 }; 1897 }; 1898 1899 gpu-thermal { 1900 polling-delay-passive = <250>; 1901 1902 thermal-sensors = <&tsens 10>; 1903 1904 trips { 1905 gpu_alert0: trip-point0 { 1906 temperature = <50000>; 1907 hysteresis = <2000>; 1908 type = "hot"; 1909 }; 1910 gpu_alert1: trip-point1 { 1911 temperature = <55000>; 1912 hysteresis = <2000>; 1913 type = "passive"; 1914 }; 1915 gpu_crit: gpu-crit { 1916 temperature = <75000>; 1917 hysteresis = <2000>; 1918 type = "critical"; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 timer { 1925 compatible = "arm,armv8-timer"; 1926 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1927 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1928 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1929 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1930 clock-frequency = <19200000>; 1931 }; 1932}; 1933