1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 AP-MI01.2 board device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8/dts-v1/; 9 10#include "ipq5332-rdp-common.dtsi" 11 12/ { 13 model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; 14 compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; 15}; 16 17&blsp1_i2c1 { 18 clock-frequency = <400000>; 19 pinctrl-0 = <&i2c_1_pins>; 20 pinctrl-names = "default"; 21 status = "okay"; 22}; 23 24&sdhc { 25 bus-width = <4>; 26 max-frequency = <192000000>; 27 mmc-ddr-1_8v; 28 mmc-hs200-1_8v; 29 non-removable; 30 pinctrl-0 = <&sdc_default_state>; 31 pinctrl-names = "default"; 32 status = "okay"; 33}; 34 35&pcie0 { 36 pinctrl-0 = <&pcie0_default>; 37 pinctrl-names = "default"; 38 39 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; 40 wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; 41 42 status = "okay"; 43}; 44 45&pcie0_phy { 46 status = "okay"; 47}; 48 49&pcie1 { 50 pinctrl-0 = <&pcie1_default>; 51 pinctrl-names = "default"; 52 53 perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; 54 wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; 55 56 status = "okay"; 57}; 58 59&pcie1_phy { 60 status = "okay"; 61}; 62 63&tlmm { 64 i2c_1_pins: i2c-1-state { 65 pins = "gpio29", "gpio30"; 66 function = "blsp1_i2c0"; 67 drive-strength = <8>; 68 bias-pull-up; 69 }; 70 71 pcie0_default: pcie0-default-state { 72 clkreq-n-pins { 73 pins = "gpio37"; 74 function = "pcie0_clk"; 75 drive-strength = <8>; 76 bias-pull-up; 77 }; 78 79 perst-n-pins { 80 pins = "gpio38"; 81 function = "gpio"; 82 drive-strength = <8>; 83 bias-pull-up; 84 output-low; 85 }; 86 87 wake-n-pins { 88 pins = "gpio39"; 89 function = "pcie0_wake"; 90 drive-strength = <8>; 91 bias-pull-up; 92 }; 93 }; 94 95 pcie1_default: pcie1-default-state { 96 clkreq-n-pins { 97 pins = "gpio46"; 98 function = "pcie1_clk"; 99 drive-strength = <8>; 100 bias-pull-up; 101 }; 102 103 perst-n-pins { 104 pins = "gpio47"; 105 function = "gpio"; 106 drive-strength = <8>; 107 bias-pull-up; 108 output-low; 109 }; 110 111 wake-n-pins { 112 pins = "gpio48"; 113 function = "pcie1_wake"; 114 drive-strength = <8>; 115 bias-pull-up; 116 }; 117 }; 118 119 sdc_default_state: sdc-default-state { 120 clk-pins { 121 pins = "gpio13"; 122 function = "sdc_clk"; 123 drive-strength = <8>; 124 bias-disable; 125 }; 126 127 cmd-pins { 128 pins = "gpio12"; 129 function = "sdc_cmd"; 130 drive-strength = <8>; 131 bias-pull-up; 132 }; 133 134 data-pins { 135 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 136 function = "sdc_data"; 137 drive-strength = <8>; 138 bias-pull-up; 139 }; 140 }; 141}; 142