1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; 36 37 pci@1,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 43 nvidia,num-lanes = <4>; 44 status = "okay"; 45 }; 46 47 pci@2,0 { 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 49 phy-names = "pcie-0"; 50 status = "okay"; 51 52 ethernet@0,0 { 53 reg = <0x000000 0 0 0 0>; 54 local-mac-address = [ 00 00 00 00 00 00 ]; 55 }; 56 }; 57 }; 58 59 host1x@50000000 { 60 dpaux@54040000 { 61 status = "okay"; 62 }; 63 64 vi@54080000 { 65 status = "okay"; 66 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 68 69 csi@838 { 70 status = "okay"; 71 }; 72 }; 73 74 sor@54540000 { 75 status = "okay"; 76 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 79 80 nvidia,xbar-cfg = <2 1 0 3 4>; 81 nvidia,dpaux = <&dpaux>; 82 }; 83 84 sor@54580000 { 85 status = "okay"; 86 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 89 hdmi-supply = <&vdd_hdmi>; 90 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 93 GPIO_ACTIVE_LOW>; 94 nvidia,xbar-cfg = <0 1 2 3 4>; 95 }; 96 97 dpaux@545c0000 { 98 status = "okay"; 99 }; 100 101 i2c@546c0000 { 102 status = "okay"; 103 }; 104 }; 105 106 gpu@57000000 { 107 vdd-supply = <&vdd_gpu>; 108 status = "okay"; 109 }; 110 111 pinmux@700008d4 { 112 dvfs_pwm_active_state: pinmux-dvfs-pwm-active { 113 dvfs_pwm_pbb1 { 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 }; 117 }; 118 119 dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { 120 dvfs_pwm_pbb1 { 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 nvidia,tristate = <TEGRA_PIN_ENABLE>; 123 }; 124 }; 125 }; 126 127 /* debug port */ 128 serial@70006000 { 129 /delete-property/ dmas; 130 /delete-property/ dma-names; 131 status = "okay"; 132 }; 133 134 pwm@7000a000 { 135 status = "okay"; 136 }; 137 138 i2c@7000c500 { 139 status = "okay"; 140 clock-frequency = <100000>; 141 142 eeprom@50 { 143 compatible = "atmel,24c02"; 144 reg = <0x50>; 145 146 label = "module"; 147 vcc-supply = <&vdd_1v8>; 148 address-width = <8>; 149 pagesize = <8>; 150 size = <256>; 151 read-only; 152 }; 153 154 eeprom@57 { 155 compatible = "atmel,24c02"; 156 reg = <0x57>; 157 158 label = "system"; 159 vcc-supply = <&vdd_1v8>; 160 address-width = <8>; 161 pagesize = <8>; 162 size = <256>; 163 read-only; 164 }; 165 }; 166 167 hdmi_ddc: i2c@7000c700 { 168 status = "okay"; 169 clock-frequency = <100000>; 170 }; 171 172 i2c@7000d000 { 173 status = "okay"; 174 clock-frequency = <400000>; 175 176 pmic: pmic@3c { 177 compatible = "maxim,max77620"; 178 reg = <0x3c>; 179 interrupt-parent = <&tegra_pmc>; 180 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 181 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 185 #gpio-cells = <2>; 186 gpio-controller; 187 188 pinctrl-names = "default"; 189 pinctrl-0 = <&max77620_default>; 190 191 fps { 192 fps0 { 193 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 194 maxim,suspend-fps-time-period-us = <5120>; 195 }; 196 197 fps1 { 198 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 199 maxim,suspend-fps-time-period-us = <5120>; 200 }; 201 202 fps2 { 203 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 204 }; 205 }; 206 207 max77620_default: pinmux { 208 gpio0 { 209 pins = "gpio0"; 210 function = "gpio"; 211 }; 212 213 gpio1 { 214 pins = "gpio1"; 215 function = "fps-out"; 216 drive-push-pull = <1>; 217 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 218 maxim,active-fps-power-up-slot = <0>; 219 maxim,active-fps-power-down-slot = <7>; 220 }; 221 222 gpio2 { 223 pins = "gpio2"; 224 function = "fps-out"; 225 drive-open-drain = <1>; 226 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 227 maxim,active-fps-power-up-slot = <0>; 228 maxim,active-fps-power-down-slot = <7>; 229 }; 230 231 gpio3 { 232 pins = "gpio3"; 233 function = "fps-out"; 234 drive-open-drain = <1>; 235 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 236 maxim,active-fps-power-up-slot = <4>; 237 maxim,active-fps-power-down-slot = <3>; 238 }; 239 240 gpio4 { 241 pins = "gpio4"; 242 function = "32k-out1"; 243 }; 244 245 gpio5_6_7 { 246 pins = "gpio5", "gpio6", "gpio7"; 247 function = "gpio"; 248 drive-push-pull = <1>; 249 }; 250 }; 251 252 regulators { 253 in-ldo0-1-supply = <&vdd_pre>; 254 in-ldo2-supply = <&vdd_3v3_sys>; 255 in-ldo3-5-supply = <&vdd_1v8>; 256 in-ldo4-6-supply = <&vdd_5v0_sys>; 257 in-ldo7-8-supply = <&vdd_pre>; 258 in-sd0-supply = <&vdd_5v0_sys>; 259 in-sd1-supply = <&vdd_5v0_sys>; 260 in-sd2-supply = <&vdd_5v0_sys>; 261 in-sd3-supply = <&vdd_5v0_sys>; 262 263 vdd_soc: sd0 { 264 regulator-name = "VDD_SOC"; 265 regulator-min-microvolt = <1000000>; 266 regulator-max-microvolt = <1170000>; 267 regulator-enable-ramp-delay = <146>; 268 regulator-ramp-delay = <27500>; 269 regulator-always-on; 270 regulator-boot-on; 271 272 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 273 maxim,active-fps-power-up-slot = <1>; 274 maxim,active-fps-power-down-slot = <6>; 275 }; 276 277 vdd_ddr: sd1 { 278 regulator-name = "VDD_DDR_1V1_PMIC"; 279 regulator-min-microvolt = <1150000>; 280 regulator-max-microvolt = <1150000>; 281 regulator-enable-ramp-delay = <176>; 282 regulator-ramp-delay = <27500>; 283 regulator-always-on; 284 regulator-boot-on; 285 286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 287 maxim,active-fps-power-up-slot = <5>; 288 maxim,active-fps-power-down-slot = <2>; 289 }; 290 291 vdd_pre: sd2 { 292 regulator-name = "VDD_PRE_REG_1V35"; 293 regulator-min-microvolt = <1350000>; 294 regulator-max-microvolt = <1350000>; 295 regulator-enable-ramp-delay = <176>; 296 regulator-ramp-delay = <27500>; 297 regulator-always-on; 298 regulator-boot-on; 299 300 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 301 maxim,active-fps-power-up-slot = <2>; 302 maxim,active-fps-power-down-slot = <5>; 303 }; 304 305 vdd_1v8: sd3 { 306 regulator-name = "VDD_1V8"; 307 regulator-min-microvolt = <1800000>; 308 regulator-max-microvolt = <1800000>; 309 regulator-enable-ramp-delay = <242>; 310 regulator-ramp-delay = <27500>; 311 regulator-always-on; 312 regulator-boot-on; 313 314 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 315 maxim,active-fps-power-up-slot = <3>; 316 maxim,active-fps-power-down-slot = <4>; 317 }; 318 319 vdd_sys_1v2: ldo0 { 320 regulator-name = "AVDD_SYS_1V2"; 321 regulator-min-microvolt = <1200000>; 322 regulator-max-microvolt = <1200000>; 323 regulator-enable-ramp-delay = <26>; 324 regulator-ramp-delay = <100000>; 325 regulator-always-on; 326 regulator-boot-on; 327 328 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 329 maxim,active-fps-power-up-slot = <0>; 330 maxim,active-fps-power-down-slot = <7>; 331 }; 332 333 vdd_pex_1v05: ldo1 { 334 regulator-name = "VDD_PEX_1V05"; 335 regulator-min-microvolt = <1050000>; 336 regulator-max-microvolt = <1050000>; 337 regulator-enable-ramp-delay = <22>; 338 regulator-ramp-delay = <100000>; 339 340 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 341 maxim,active-fps-power-up-slot = <0>; 342 maxim,active-fps-power-down-slot = <7>; 343 }; 344 345 vddio_sdmmc: ldo2 { 346 regulator-name = "VDDIO_SDMMC"; 347 regulator-min-microvolt = <1800000>; 348 regulator-max-microvolt = <3300000>; 349 regulator-enable-ramp-delay = <62>; 350 regulator-ramp-delay = <100000>; 351 352 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 353 maxim,active-fps-power-up-slot = <0>; 354 maxim,active-fps-power-down-slot = <7>; 355 }; 356 357 ldo3 { 358 status = "disabled"; 359 }; 360 361 vdd_rtc: ldo4 { 362 regulator-name = "VDD_RTC"; 363 regulator-min-microvolt = <850000>; 364 regulator-max-microvolt = <1100000>; 365 regulator-enable-ramp-delay = <22>; 366 regulator-ramp-delay = <100000>; 367 regulator-disable-active-discharge; 368 regulator-always-on; 369 regulator-boot-on; 370 371 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 372 maxim,active-fps-power-up-slot = <1>; 373 maxim,active-fps-power-down-slot = <6>; 374 }; 375 376 ldo5 { 377 status = "disabled"; 378 }; 379 380 ldo6 { 381 status = "disabled"; 382 }; 383 384 avdd_1v05_pll: ldo7 { 385 regulator-name = "AVDD_1V05_PLL"; 386 regulator-min-microvolt = <1050000>; 387 regulator-max-microvolt = <1050000>; 388 regulator-enable-ramp-delay = <24>; 389 regulator-ramp-delay = <100000>; 390 391 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 392 maxim,active-fps-power-up-slot = <3>; 393 maxim,active-fps-power-down-slot = <4>; 394 }; 395 396 avdd_1v05: ldo8 { 397 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 398 regulator-min-microvolt = <1050000>; 399 regulator-max-microvolt = <1050000>; 400 regulator-enable-ramp-delay = <22>; 401 regulator-ramp-delay = <100000>; 402 403 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 404 maxim,active-fps-power-up-slot = <6>; 405 maxim,active-fps-power-down-slot = <1>; 406 }; 407 }; 408 }; 409 }; 410 411 pmc@7000e400 { 412 nvidia,invert-interrupt; 413 nvidia,suspend-mode = <0>; 414 nvidia,cpu-pwr-good-time = <0>; 415 nvidia,cpu-pwr-off-time = <0>; 416 nvidia,core-pwr-good-time = <4587 3876>; 417 nvidia,core-pwr-off-time = <39065>; 418 nvidia,core-power-req-active-high; 419 nvidia,sys-clock-req-active-high; 420 }; 421 422 cec@70015000 { 423 status = "okay"; 424 425 hdmi-phandle = <&sor1>; 426 }; 427 428 hda@70030000 { 429 nvidia,model = "NVIDIA Jetson Nano HDA"; 430 431 status = "okay"; 432 }; 433 434 usb@70090000 { 435 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 436 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 437 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 438 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 439 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 440 441 avdd-usb-supply = <&vdd_3v3_sys>; 442 dvddio-pex-supply = <&vdd_pex_1v05>; 443 hvddio-pex-supply = <&vdd_1v8>; 444 445 status = "okay"; 446 }; 447 448 padctl@7009f000 { 449 status = "okay"; 450 451 avdd-pll-utmip-supply = <&vdd_1v8>; 452 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 453 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 454 hvdd-pex-pll-e-supply = <&vdd_1v8>; 455 456 pads { 457 usb2 { 458 status = "okay"; 459 460 lanes { 461 micro_b: usb2-0 { 462 nvidia,function = "xusb"; 463 status = "okay"; 464 }; 465 466 usb2-1 { 467 nvidia,function = "xusb"; 468 status = "okay"; 469 }; 470 471 usb2-2 { 472 nvidia,function = "xusb"; 473 status = "okay"; 474 }; 475 }; 476 }; 477 478 pcie { 479 status = "okay"; 480 481 lanes { 482 pcie-0 { 483 nvidia,function = "pcie-x1"; 484 status = "okay"; 485 }; 486 487 pcie-1 { 488 nvidia,function = "pcie-x4"; 489 status = "okay"; 490 }; 491 492 pcie-2 { 493 nvidia,function = "pcie-x4"; 494 status = "okay"; 495 }; 496 497 pcie-3 { 498 nvidia,function = "pcie-x4"; 499 status = "okay"; 500 }; 501 502 pcie-4 { 503 nvidia,function = "pcie-x4"; 504 status = "okay"; 505 }; 506 507 pcie-5 { 508 nvidia,function = "usb3-ss"; 509 status = "okay"; 510 }; 511 512 pcie-6 { 513 nvidia,function = "usb3-ss"; 514 status = "okay"; 515 }; 516 }; 517 }; 518 }; 519 520 ports { 521 usb2-0 { 522 status = "okay"; 523 mode = "peripheral"; 524 usb-role-switch; 525 526 vbus-supply = <&vdd_5v0_usb>; 527 528 connector { 529 compatible = "gpio-usb-b-connector", 530 "usb-b-connector"; 531 label = "micro-USB"; 532 type = "micro"; 533 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 534 GPIO_ACTIVE_LOW>; 535 }; 536 }; 537 538 usb2-1 { 539 status = "okay"; 540 mode = "host"; 541 }; 542 543 usb2-2 { 544 status = "okay"; 545 mode = "host"; 546 }; 547 548 usb3-0 { 549 status = "okay"; 550 nvidia,usb2-companion = <1>; 551 vbus-supply = <&vdd_hub_3v3>; 552 }; 553 }; 554 }; 555 556 mmc@700b0000 { 557 status = "okay"; 558 bus-width = <4>; 559 560 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 561 disable-wp; 562 563 vqmmc-supply = <&vddio_sdmmc>; 564 vmmc-supply = <&vdd_3v3_sd>; 565 }; 566 567 mmc@700b0400 { 568 status = "okay"; 569 bus-width = <4>; 570 571 vqmmc-supply = <&vdd_1v8>; 572 vmmc-supply = <&vdd_3v3_sys>; 573 574 non-removable; 575 cap-sdio-irq; 576 keep-power-in-suspend; 577 wakeup-source; 578 }; 579 580 usb@700d0000 { 581 status = "okay"; 582 phys = <µ_b>; 583 phy-names = "usb2-0"; 584 avddio-usb-supply = <&vdd_3v3_sys>; 585 hvdd-usb-supply = <&vdd_1v8>; 586 }; 587 588 clock@70110000 { 589 status = "okay"; 590 591 nvidia,cf = <6>; 592 nvidia,ci = <0>; 593 nvidia,cg = <2>; 594 nvidia,droop-ctrl = <0x00000f00>; 595 nvidia,force-mode = <1>; 596 nvidia,sample-rate = <25000>; 597 598 nvidia,pwm-min-microvolts = <708000>; 599 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 600 nvidia,pwm-to-pmic; 601 nvidia,pwm-tristate-microvolts = <1000000>; 602 nvidia,pwm-voltage-step-microvolts = <19200>; 603 604 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 605 pinctrl-0 = <&dvfs_pwm_active_state>; 606 pinctrl-1 = <&dvfs_pwm_inactive_state>; 607 }; 608 609 aconnect@702c0000 { 610 status = "okay"; 611 612 ahub@702d0800 { 613 status = "okay"; 614 615 admaif@702d0000 { 616 status = "okay"; 617 }; 618 619 i2s@702d1200 { 620 status = "okay"; 621 622 ports { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 port@0 { 627 reg = <0>; 628 629 i2s3_cif_ep: endpoint { 630 remote-endpoint = <&xbar_i2s3_ep>; 631 }; 632 }; 633 634 i2s3_port: port@1 { 635 reg = <1>; 636 637 i2s3_dap_ep: endpoint { 638 dai-format = "i2s"; 639 /* Placeholder for external Codec */ 640 }; 641 }; 642 }; 643 }; 644 645 i2s@702d1300 { 646 status = "okay"; 647 648 ports { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 652 port@0 { 653 reg = <0>; 654 655 i2s4_cif_ep: endpoint { 656 remote-endpoint = <&xbar_i2s4_ep>; 657 }; 658 }; 659 660 i2s4_port: port@1 { 661 reg = <1>; 662 663 i2s4_dap_ep: endpoint { 664 dai-format = "i2s"; 665 /* Placeholder for external Codec */ 666 }; 667 }; 668 }; 669 }; 670 671 sfc@702d2000 { 672 status = "okay"; 673 674 ports { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 678 port@0 { 679 reg = <0>; 680 681 sfc1_cif_in_ep: endpoint { 682 remote-endpoint = <&xbar_sfc1_in_ep>; 683 }; 684 }; 685 686 sfc1_out_port: port@1 { 687 reg = <1>; 688 689 sfc1_cif_out_ep: endpoint { 690 remote-endpoint = <&xbar_sfc1_out_ep>; 691 }; 692 }; 693 }; 694 }; 695 696 sfc@702d2200 { 697 status = "okay"; 698 699 ports { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 port@0 { 704 reg = <0>; 705 706 sfc2_cif_in_ep: endpoint { 707 remote-endpoint = <&xbar_sfc2_in_ep>; 708 }; 709 }; 710 711 sfc2_out_port: port@1 { 712 reg = <1>; 713 714 sfc2_cif_out_ep: endpoint { 715 remote-endpoint = <&xbar_sfc2_out_ep>; 716 }; 717 }; 718 }; 719 }; 720 721 sfc@702d2400 { 722 status = "okay"; 723 724 ports { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 728 port@0 { 729 reg = <0>; 730 731 sfc3_cif_in_ep: endpoint { 732 remote-endpoint = <&xbar_sfc3_in_ep>; 733 }; 734 }; 735 736 sfc3_out_port: port@1 { 737 reg = <1>; 738 739 sfc3_cif_out_ep: endpoint { 740 remote-endpoint = <&xbar_sfc3_out_ep>; 741 }; 742 }; 743 }; 744 }; 745 746 sfc@702d2600 { 747 status = "okay"; 748 749 ports { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 port@0 { 754 reg = <0>; 755 756 sfc4_cif_in_ep: endpoint { 757 remote-endpoint = <&xbar_sfc4_in_ep>; 758 }; 759 }; 760 761 sfc4_out_port: port@1 { 762 reg = <1>; 763 764 sfc4_cif_out_ep: endpoint { 765 remote-endpoint = <&xbar_sfc4_out_ep>; 766 }; 767 }; 768 }; 769 }; 770 771 amx@702d3000 { 772 status = "okay"; 773 774 ports { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 port@0 { 779 reg = <0>; 780 781 amx1_in1_ep: endpoint { 782 remote-endpoint = <&xbar_amx1_in1_ep>; 783 }; 784 }; 785 786 port@1 { 787 reg = <1>; 788 789 amx1_in2_ep: endpoint { 790 remote-endpoint = <&xbar_amx1_in2_ep>; 791 }; 792 }; 793 794 port@2 { 795 reg = <2>; 796 797 amx1_in3_ep: endpoint { 798 remote-endpoint = <&xbar_amx1_in3_ep>; 799 }; 800 }; 801 802 port@3 { 803 reg = <3>; 804 805 amx1_in4_ep: endpoint { 806 remote-endpoint = <&xbar_amx1_in4_ep>; 807 }; 808 }; 809 810 amx1_out_port: port@4 { 811 reg = <4>; 812 813 amx1_out_ep: endpoint { 814 remote-endpoint = <&xbar_amx1_out_ep>; 815 }; 816 }; 817 }; 818 }; 819 820 amx@702d3100 { 821 status = "okay"; 822 823 ports { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 827 port@0 { 828 reg = <0>; 829 830 amx2_in1_ep: endpoint { 831 remote-endpoint = <&xbar_amx2_in1_ep>; 832 }; 833 }; 834 835 port@1 { 836 reg = <1>; 837 838 amx2_in2_ep: endpoint { 839 remote-endpoint = <&xbar_amx2_in2_ep>; 840 }; 841 }; 842 843 amx2_in3_port: port@2 { 844 reg = <2>; 845 846 amx2_in3_ep: endpoint { 847 remote-endpoint = <&xbar_amx2_in3_ep>; 848 }; 849 }; 850 851 amx2_in4_port: port@3 { 852 reg = <3>; 853 854 amx2_in4_ep: endpoint { 855 remote-endpoint = <&xbar_amx2_in4_ep>; 856 }; 857 }; 858 859 amx2_out_port: port@4 { 860 reg = <4>; 861 862 amx2_out_ep: endpoint { 863 remote-endpoint = <&xbar_amx2_out_ep>; 864 }; 865 }; 866 }; 867 }; 868 869 adx@702d3800 { 870 status = "okay"; 871 872 ports { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 876 port@0 { 877 reg = <0>; 878 879 adx1_in_ep: endpoint { 880 remote-endpoint = <&xbar_adx1_in_ep>; 881 }; 882 }; 883 884 adx1_out1_port: port@1 { 885 reg = <1>; 886 887 adx1_out1_ep: endpoint { 888 remote-endpoint = <&xbar_adx1_out1_ep>; 889 }; 890 }; 891 892 adx1_out2_port: port@2 { 893 reg = <2>; 894 895 adx1_out2_ep: endpoint { 896 remote-endpoint = <&xbar_adx1_out2_ep>; 897 }; 898 }; 899 900 adx1_out3_port: port@3 { 901 reg = <3>; 902 903 adx1_out3_ep: endpoint { 904 remote-endpoint = <&xbar_adx1_out3_ep>; 905 }; 906 }; 907 908 adx1_out4_port: port@4 { 909 reg = <4>; 910 911 adx1_out4_ep: endpoint { 912 remote-endpoint = <&xbar_adx1_out4_ep>; 913 }; 914 }; 915 }; 916 }; 917 918 adx@702d3900 { 919 status = "okay"; 920 921 ports { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 925 port@0 { 926 reg = <0>; 927 928 adx2_in_ep: endpoint { 929 remote-endpoint = <&xbar_adx2_in_ep>; 930 }; 931 }; 932 933 adx2_out1_port: port@1 { 934 reg = <1>; 935 936 adx2_out1_ep: endpoint { 937 remote-endpoint = <&xbar_adx2_out1_ep>; 938 }; 939 }; 940 941 adx2_out2_port: port@2 { 942 reg = <2>; 943 944 adx2_out2_ep: endpoint { 945 remote-endpoint = <&xbar_adx2_out2_ep>; 946 }; 947 }; 948 949 adx2_out3_port: port@3 { 950 reg = <3>; 951 952 adx2_out3_ep: endpoint { 953 remote-endpoint = <&xbar_adx2_out3_ep>; 954 }; 955 }; 956 957 adx2_out4_port: port@4 { 958 reg = <4>; 959 960 adx2_out4_ep: endpoint { 961 remote-endpoint = <&xbar_adx2_out4_ep>; 962 }; 963 }; 964 }; 965 }; 966 967 dmic@702d4000 { 968 status = "okay"; 969 970 ports { 971 #address-cells = <1>; 972 #size-cells = <0>; 973 974 port@0 { 975 reg = <0>; 976 977 dmic1_cif_ep: endpoint { 978 remote-endpoint = <&xbar_dmic1_ep>; 979 }; 980 }; 981 982 dmic1_port: port@1 { 983 reg = <1>; 984 985 dmic1_dap_ep: endpoint { 986 /* Placeholder for external Codec */ 987 }; 988 }; 989 }; 990 }; 991 992 dmic@702d4100 { 993 status = "okay"; 994 995 ports { 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 port@0 { 1000 reg = <0>; 1001 1002 dmic2_cif_ep: endpoint { 1003 remote-endpoint = <&xbar_dmic2_ep>; 1004 }; 1005 }; 1006 1007 dmic2_port: port@1 { 1008 reg = <1>; 1009 1010 dmic2_dap_ep: endpoint { 1011 /* Placeholder for external Codec */ 1012 }; 1013 }; 1014 }; 1015 }; 1016 1017 processing-engine@702d8000 { 1018 status = "okay"; 1019 1020 ports { 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 1024 port@0 { 1025 reg = <0x0>; 1026 1027 ope1_cif_in_ep: endpoint { 1028 remote-endpoint = <&xbar_ope1_in_ep>; 1029 }; 1030 }; 1031 1032 ope1_out_port: port@1 { 1033 reg = <0x1>; 1034 1035 ope1_cif_out_ep: endpoint { 1036 remote-endpoint = <&xbar_ope1_out_ep>; 1037 }; 1038 }; 1039 }; 1040 }; 1041 1042 processing-engine@702d8400 { 1043 status = "okay"; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 port@0 { 1050 reg = <0x0>; 1051 1052 ope2_cif_in_ep: endpoint { 1053 remote-endpoint = <&xbar_ope2_in_ep>; 1054 }; 1055 }; 1056 1057 ope2_out_port: port@1 { 1058 reg = <0x1>; 1059 1060 ope2_cif_out_ep: endpoint { 1061 remote-endpoint = <&xbar_ope2_out_ep>; 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 mvc@702da000 { 1068 status = "okay"; 1069 1070 ports { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 port@0 { 1075 reg = <0>; 1076 1077 mvc1_cif_in_ep: endpoint { 1078 remote-endpoint = <&xbar_mvc1_in_ep>; 1079 }; 1080 }; 1081 1082 mvc1_out_port: port@1 { 1083 reg = <1>; 1084 1085 mvc1_cif_out_ep: endpoint { 1086 remote-endpoint = <&xbar_mvc1_out_ep>; 1087 }; 1088 }; 1089 }; 1090 }; 1091 1092 mvc@702da200 { 1093 status = "okay"; 1094 1095 ports { 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 1099 port@0 { 1100 reg = <0>; 1101 1102 mvc2_cif_in_ep: endpoint { 1103 remote-endpoint = <&xbar_mvc2_in_ep>; 1104 }; 1105 }; 1106 1107 mvc2_out_port: port@1 { 1108 reg = <1>; 1109 1110 mvc2_cif_out_ep: endpoint { 1111 remote-endpoint = <&xbar_mvc2_out_ep>; 1112 }; 1113 }; 1114 }; 1115 }; 1116 1117 amixer@702dbb00 { 1118 status = "okay"; 1119 1120 ports { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 port@0 { 1125 reg = <0x0>; 1126 1127 mixer_in1_ep: endpoint { 1128 remote-endpoint = <&xbar_mixer_in1_ep>; 1129 }; 1130 }; 1131 1132 port@1 { 1133 reg = <0x1>; 1134 1135 mixer_in2_ep: endpoint { 1136 remote-endpoint = <&xbar_mixer_in2_ep>; 1137 }; 1138 }; 1139 1140 port@2 { 1141 reg = <0x2>; 1142 1143 mixer_in3_ep: endpoint { 1144 remote-endpoint = <&xbar_mixer_in3_ep>; 1145 }; 1146 }; 1147 1148 port@3 { 1149 reg = <0x3>; 1150 1151 mixer_in4_ep: endpoint { 1152 remote-endpoint = <&xbar_mixer_in4_ep>; 1153 }; 1154 }; 1155 1156 port@4 { 1157 reg = <0x4>; 1158 1159 mixer_in5_ep: endpoint { 1160 remote-endpoint = <&xbar_mixer_in5_ep>; 1161 }; 1162 }; 1163 1164 port@5 { 1165 reg = <0x5>; 1166 1167 mixer_in6_ep: endpoint { 1168 remote-endpoint = <&xbar_mixer_in6_ep>; 1169 }; 1170 }; 1171 1172 port@6 { 1173 reg = <0x6>; 1174 1175 mixer_in7_ep: endpoint { 1176 remote-endpoint = <&xbar_mixer_in7_ep>; 1177 }; 1178 }; 1179 1180 port@7 { 1181 reg = <0x7>; 1182 1183 mixer_in8_ep: endpoint { 1184 remote-endpoint = <&xbar_mixer_in8_ep>; 1185 }; 1186 }; 1187 1188 port@8 { 1189 reg = <0x8>; 1190 1191 mixer_in9_ep: endpoint { 1192 remote-endpoint = <&xbar_mixer_in9_ep>; 1193 }; 1194 }; 1195 1196 port@9 { 1197 reg = <0x9>; 1198 1199 mixer_in10_ep: endpoint { 1200 remote-endpoint = <&xbar_mixer_in10_ep>; 1201 }; 1202 }; 1203 1204 mixer_out1_port: port@a { 1205 reg = <0xa>; 1206 1207 mixer_out1_ep: endpoint { 1208 remote-endpoint = <&xbar_mixer_out1_ep>; 1209 }; 1210 }; 1211 1212 mixer_out2_port: port@b { 1213 reg = <0xb>; 1214 1215 mixer_out2_ep: endpoint { 1216 remote-endpoint = <&xbar_mixer_out2_ep>; 1217 }; 1218 }; 1219 1220 mixer_out3_port: port@c { 1221 reg = <0xc>; 1222 1223 mixer_out3_ep: endpoint { 1224 remote-endpoint = <&xbar_mixer_out3_ep>; 1225 }; 1226 }; 1227 1228 mixer_out4_port: port@d { 1229 reg = <0xd>; 1230 1231 mixer_out4_ep: endpoint { 1232 remote-endpoint = <&xbar_mixer_out4_ep>; 1233 }; 1234 }; 1235 1236 mixer_out5_port: port@e { 1237 reg = <0xe>; 1238 1239 mixer_out5_ep: endpoint { 1240 remote-endpoint = <&xbar_mixer_out5_ep>; 1241 }; 1242 }; 1243 }; 1244 }; 1245 1246 ports { 1247 xbar_i2s3_port: port@c { 1248 reg = <0xc>; 1249 1250 xbar_i2s3_ep: endpoint { 1251 remote-endpoint = <&i2s3_cif_ep>; 1252 }; 1253 }; 1254 1255 xbar_i2s4_port: port@d { 1256 reg = <0xd>; 1257 1258 xbar_i2s4_ep: endpoint { 1259 remote-endpoint = <&i2s4_cif_ep>; 1260 }; 1261 }; 1262 1263 xbar_dmic1_port: port@f { 1264 reg = <0xf>; 1265 1266 xbar_dmic1_ep: endpoint { 1267 remote-endpoint = <&dmic1_cif_ep>; 1268 }; 1269 }; 1270 1271 xbar_dmic2_port: port@10 { 1272 reg = <0x10>; 1273 1274 xbar_dmic2_ep: endpoint { 1275 remote-endpoint = <&dmic2_cif_ep>; 1276 }; 1277 }; 1278 1279 xbar_sfc1_in_port: port@12 { 1280 reg = <0x12>; 1281 1282 xbar_sfc1_in_ep: endpoint { 1283 remote-endpoint = <&sfc1_cif_in_ep>; 1284 }; 1285 }; 1286 1287 port@13 { 1288 reg = <0x13>; 1289 1290 xbar_sfc1_out_ep: endpoint { 1291 remote-endpoint = <&sfc1_cif_out_ep>; 1292 }; 1293 }; 1294 1295 xbar_sfc2_in_port: port@14 { 1296 reg = <0x14>; 1297 1298 xbar_sfc2_in_ep: endpoint { 1299 remote-endpoint = <&sfc2_cif_in_ep>; 1300 }; 1301 }; 1302 1303 port@15 { 1304 reg = <0x15>; 1305 1306 xbar_sfc2_out_ep: endpoint { 1307 remote-endpoint = <&sfc2_cif_out_ep>; 1308 }; 1309 }; 1310 1311 xbar_sfc3_in_port: port@16 { 1312 reg = <0x16>; 1313 1314 xbar_sfc3_in_ep: endpoint { 1315 remote-endpoint = <&sfc3_cif_in_ep>; 1316 }; 1317 }; 1318 1319 port@17 { 1320 reg = <0x17>; 1321 1322 xbar_sfc3_out_ep: endpoint { 1323 remote-endpoint = <&sfc3_cif_out_ep>; 1324 }; 1325 }; 1326 1327 xbar_sfc4_in_port: port@18 { 1328 reg = <0x18>; 1329 1330 xbar_sfc4_in_ep: endpoint { 1331 remote-endpoint = <&sfc4_cif_in_ep>; 1332 }; 1333 }; 1334 1335 port@19 { 1336 reg = <0x19>; 1337 1338 xbar_sfc4_out_ep: endpoint { 1339 remote-endpoint = <&sfc4_cif_out_ep>; 1340 }; 1341 }; 1342 1343 xbar_mvc1_in_port: port@1a { 1344 reg = <0x1a>; 1345 1346 xbar_mvc1_in_ep: endpoint { 1347 remote-endpoint = <&mvc1_cif_in_ep>; 1348 }; 1349 }; 1350 1351 port@1b { 1352 reg = <0x1b>; 1353 1354 xbar_mvc1_out_ep: endpoint { 1355 remote-endpoint = <&mvc1_cif_out_ep>; 1356 }; 1357 }; 1358 1359 xbar_mvc2_in_port: port@1c { 1360 reg = <0x1c>; 1361 1362 xbar_mvc2_in_ep: endpoint { 1363 remote-endpoint = <&mvc2_cif_in_ep>; 1364 }; 1365 }; 1366 1367 port@1d { 1368 reg = <0x1d>; 1369 1370 xbar_mvc2_out_ep: endpoint { 1371 remote-endpoint = <&mvc2_cif_out_ep>; 1372 }; 1373 }; 1374 1375 xbar_amx1_in1_port: port@1e { 1376 reg = <0x1e>; 1377 1378 xbar_amx1_in1_ep: endpoint { 1379 remote-endpoint = <&amx1_in1_ep>; 1380 }; 1381 }; 1382 1383 xbar_amx1_in2_port: port@1f { 1384 reg = <0x1f>; 1385 1386 xbar_amx1_in2_ep: endpoint { 1387 remote-endpoint = <&amx1_in2_ep>; 1388 }; 1389 }; 1390 1391 xbar_amx1_in3_port: port@20 { 1392 reg = <0x20>; 1393 1394 xbar_amx1_in3_ep: endpoint { 1395 remote-endpoint = <&amx1_in3_ep>; 1396 }; 1397 }; 1398 1399 xbar_amx1_in4_port: port@21 { 1400 reg = <0x21>; 1401 1402 xbar_amx1_in4_ep: endpoint { 1403 remote-endpoint = <&amx1_in4_ep>; 1404 }; 1405 }; 1406 1407 port@22 { 1408 reg = <0x22>; 1409 1410 xbar_amx1_out_ep: endpoint { 1411 remote-endpoint = <&amx1_out_ep>; 1412 }; 1413 }; 1414 1415 xbar_amx2_in1_port: port@23 { 1416 reg = <0x23>; 1417 1418 xbar_amx2_in1_ep: endpoint { 1419 remote-endpoint = <&amx2_in1_ep>; 1420 }; 1421 }; 1422 1423 xbar_amx2_in2_port: port@24 { 1424 reg = <0x24>; 1425 1426 xbar_amx2_in2_ep: endpoint { 1427 remote-endpoint = <&amx2_in2_ep>; 1428 }; 1429 }; 1430 1431 xbar_amx2_in3_port: port@25 { 1432 reg = <0x25>; 1433 1434 xbar_amx2_in3_ep: endpoint { 1435 remote-endpoint = <&amx2_in3_ep>; 1436 }; 1437 }; 1438 1439 xbar_amx2_in4_port: port@26 { 1440 reg = <0x26>; 1441 1442 xbar_amx2_in4_ep: endpoint { 1443 remote-endpoint = <&amx2_in4_ep>; 1444 }; 1445 }; 1446 1447 port@27 { 1448 reg = <0x27>; 1449 1450 xbar_amx2_out_ep: endpoint { 1451 remote-endpoint = <&amx2_out_ep>; 1452 }; 1453 }; 1454 1455 xbar_adx1_in_port: port@28 { 1456 reg = <0x28>; 1457 1458 xbar_adx1_in_ep: endpoint { 1459 remote-endpoint = <&adx1_in_ep>; 1460 }; 1461 }; 1462 1463 port@29 { 1464 reg = <0x29>; 1465 1466 xbar_adx1_out1_ep: endpoint { 1467 remote-endpoint = <&adx1_out1_ep>; 1468 }; 1469 }; 1470 1471 port@2a { 1472 reg = <0x2a>; 1473 1474 xbar_adx1_out2_ep: endpoint { 1475 remote-endpoint = <&adx1_out2_ep>; 1476 }; 1477 }; 1478 1479 port@2b { 1480 reg = <0x2b>; 1481 1482 xbar_adx1_out3_ep: endpoint { 1483 remote-endpoint = <&adx1_out3_ep>; 1484 }; 1485 }; 1486 1487 port@2c { 1488 reg = <0x2c>; 1489 1490 xbar_adx1_out4_ep: endpoint { 1491 remote-endpoint = <&adx1_out4_ep>; 1492 }; 1493 }; 1494 1495 xbar_adx2_in_port: port@2d { 1496 reg = <0x2d>; 1497 1498 xbar_adx2_in_ep: endpoint { 1499 remote-endpoint = <&adx2_in_ep>; 1500 }; 1501 }; 1502 1503 port@2e { 1504 reg = <0x2e>; 1505 1506 xbar_adx2_out1_ep: endpoint { 1507 remote-endpoint = <&adx2_out1_ep>; 1508 }; 1509 }; 1510 1511 port@2f { 1512 reg = <0x2f>; 1513 1514 xbar_adx2_out2_ep: endpoint { 1515 remote-endpoint = <&adx2_out2_ep>; 1516 }; 1517 }; 1518 1519 port@30 { 1520 reg = <0x30>; 1521 1522 xbar_adx2_out3_ep: endpoint { 1523 remote-endpoint = <&adx2_out3_ep>; 1524 }; 1525 }; 1526 1527 port@31 { 1528 reg = <0x31>; 1529 1530 xbar_adx2_out4_ep: endpoint { 1531 remote-endpoint = <&adx2_out4_ep>; 1532 }; 1533 }; 1534 1535 xbar_mixer_in1_port: port@32 { 1536 reg = <0x32>; 1537 1538 xbar_mixer_in1_ep: endpoint { 1539 remote-endpoint = <&mixer_in1_ep>; 1540 }; 1541 }; 1542 1543 xbar_mixer_in2_port: port@33 { 1544 reg = <0x33>; 1545 1546 xbar_mixer_in2_ep: endpoint { 1547 remote-endpoint = <&mixer_in2_ep>; 1548 }; 1549 }; 1550 1551 xbar_mixer_in3_port: port@34 { 1552 reg = <0x34>; 1553 1554 xbar_mixer_in3_ep: endpoint { 1555 remote-endpoint = <&mixer_in3_ep>; 1556 }; 1557 }; 1558 1559 xbar_mixer_in4_port: port@35 { 1560 reg = <0x35>; 1561 1562 xbar_mixer_in4_ep: endpoint { 1563 remote-endpoint = <&mixer_in4_ep>; 1564 }; 1565 }; 1566 1567 xbar_mixer_in5_port: port@36 { 1568 reg = <0x36>; 1569 1570 xbar_mixer_in5_ep: endpoint { 1571 remote-endpoint = <&mixer_in5_ep>; 1572 }; 1573 }; 1574 1575 xbar_mixer_in6_port: port@37 { 1576 reg = <0x37>; 1577 1578 xbar_mixer_in6_ep: endpoint { 1579 remote-endpoint = <&mixer_in6_ep>; 1580 }; 1581 }; 1582 1583 xbar_mixer_in7_port: port@38 { 1584 reg = <0x38>; 1585 1586 xbar_mixer_in7_ep: endpoint { 1587 remote-endpoint = <&mixer_in7_ep>; 1588 }; 1589 }; 1590 1591 xbar_mixer_in8_port: port@39 { 1592 reg = <0x39>; 1593 1594 xbar_mixer_in8_ep: endpoint { 1595 remote-endpoint = <&mixer_in8_ep>; 1596 }; 1597 }; 1598 1599 xbar_mixer_in9_port: port@3a { 1600 reg = <0x3a>; 1601 1602 xbar_mixer_in9_ep: endpoint { 1603 remote-endpoint = <&mixer_in9_ep>; 1604 }; 1605 }; 1606 1607 xbar_mixer_in10_port: port@3b { 1608 reg = <0x3b>; 1609 1610 xbar_mixer_in10_ep: endpoint { 1611 remote-endpoint = <&mixer_in10_ep>; 1612 }; 1613 }; 1614 1615 port@3c { 1616 reg = <0x3c>; 1617 1618 xbar_mixer_out1_ep: endpoint { 1619 remote-endpoint = <&mixer_out1_ep>; 1620 }; 1621 }; 1622 1623 port@3d { 1624 reg = <0x3d>; 1625 1626 xbar_mixer_out2_ep: endpoint { 1627 remote-endpoint = <&mixer_out2_ep>; 1628 }; 1629 }; 1630 1631 port@3e { 1632 reg = <0x3e>; 1633 1634 xbar_mixer_out3_ep: endpoint { 1635 remote-endpoint = <&mixer_out3_ep>; 1636 }; 1637 }; 1638 1639 port@3f { 1640 reg = <0x3f>; 1641 1642 xbar_mixer_out4_ep: endpoint { 1643 remote-endpoint = <&mixer_out4_ep>; 1644 }; 1645 }; 1646 1647 port@40 { 1648 reg = <0x40>; 1649 1650 xbar_mixer_out5_ep: endpoint { 1651 remote-endpoint = <&mixer_out5_ep>; 1652 }; 1653 }; 1654 1655 xbar_ope1_in_port: port@41 { 1656 reg = <0x41>; 1657 1658 xbar_ope1_in_ep: endpoint { 1659 remote-endpoint = <&ope1_cif_in_ep>; 1660 }; 1661 }; 1662 1663 port@42 { 1664 reg = <0x42>; 1665 1666 xbar_ope1_out_ep: endpoint { 1667 remote-endpoint = <&ope1_cif_out_ep>; 1668 }; 1669 }; 1670 1671 xbar_ope2_in_port: port@43 { 1672 reg = <0x43>; 1673 1674 xbar_ope2_in_ep: endpoint { 1675 remote-endpoint = <&ope2_cif_in_ep>; 1676 }; 1677 }; 1678 1679 port@44 { 1680 reg = <0x44>; 1681 1682 xbar_ope2_out_ep: endpoint { 1683 remote-endpoint = <&ope2_cif_out_ep>; 1684 }; 1685 }; 1686 }; 1687 }; 1688 1689 dma-controller@702e2000 { 1690 status = "okay"; 1691 }; 1692 1693 interrupt-controller@702f9000 { 1694 status = "okay"; 1695 }; 1696 }; 1697 1698 spi@70410000 { 1699 status = "okay"; 1700 1701 flash@0 { 1702 compatible = "jedec,spi-nor"; 1703 reg = <0>; 1704 spi-max-frequency = <104000000>; 1705 spi-tx-bus-width = <2>; 1706 spi-rx-bus-width = <2>; 1707 }; 1708 }; 1709 1710 clk32k_in: clock-32k { 1711 compatible = "fixed-clock"; 1712 clock-frequency = <32768>; 1713 #clock-cells = <0>; 1714 }; 1715 1716 cpus { 1717 cpu@0 { 1718 enable-method = "psci"; 1719 }; 1720 1721 cpu@1 { 1722 enable-method = "psci"; 1723 }; 1724 1725 cpu@2 { 1726 enable-method = "psci"; 1727 }; 1728 1729 cpu@3 { 1730 enable-method = "psci"; 1731 }; 1732 1733 idle-states { 1734 cpu-sleep { 1735 status = "okay"; 1736 }; 1737 }; 1738 }; 1739 1740 gpio-keys { 1741 compatible = "gpio-keys"; 1742 1743 key-force-recovery { 1744 label = "Force Recovery"; 1745 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1746 linux,input-type = <EV_KEY>; 1747 linux,code = <BTN_1>; 1748 debounce-interval = <30>; 1749 }; 1750 1751 key-power { 1752 label = "Power"; 1753 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1754 linux,input-type = <EV_KEY>; 1755 linux,code = <KEY_POWER>; 1756 debounce-interval = <30>; 1757 wakeup-event-action = <EV_ACT_ASSERTED>; 1758 wakeup-source; 1759 }; 1760 }; 1761 1762 psci { 1763 compatible = "arm,psci-1.0"; 1764 method = "smc"; 1765 }; 1766 1767 fan: pwm-fan { 1768 compatible = "pwm-fan"; 1769 pwms = <&pwm 3 45334>; 1770 1771 cooling-levels = <0 64 128 255>; 1772 #cooling-cells = <2>; 1773 }; 1774 1775 vdd_5v0_sys: regulator-vdd-5v0-sys { 1776 compatible = "regulator-fixed"; 1777 1778 regulator-name = "VDD_5V0_SYS"; 1779 regulator-min-microvolt = <5000000>; 1780 regulator-max-microvolt = <5000000>; 1781 regulator-always-on; 1782 regulator-boot-on; 1783 }; 1784 1785 vdd_3v3_sys: regulator-vdd-3v3-sys { 1786 compatible = "regulator-fixed"; 1787 1788 regulator-name = "VDD_3V3_SYS"; 1789 regulator-min-microvolt = <3300000>; 1790 regulator-max-microvolt = <3300000>; 1791 regulator-enable-ramp-delay = <240>; 1792 regulator-always-on; 1793 regulator-boot-on; 1794 1795 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1796 enable-active-high; 1797 1798 vin-supply = <&vdd_5v0_sys>; 1799 }; 1800 1801 vdd_3v3_sd: regulator-vdd-3v3-sd { 1802 compatible = "regulator-fixed"; 1803 1804 regulator-name = "VDD_3V3_SD"; 1805 regulator-min-microvolt = <3300000>; 1806 regulator-max-microvolt = <3300000>; 1807 1808 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1809 enable-active-high; 1810 1811 vin-supply = <&vdd_3v3_sys>; 1812 }; 1813 1814 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1815 compatible = "regulator-fixed"; 1816 1817 regulator-name = "VDD_HDMI_5V0"; 1818 regulator-min-microvolt = <5000000>; 1819 regulator-max-microvolt = <5000000>; 1820 1821 vin-supply = <&vdd_5v0_sys>; 1822 }; 1823 1824 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1825 compatible = "regulator-fixed"; 1826 1827 regulator-name = "VDD_HUB_3V3"; 1828 regulator-min-microvolt = <3300000>; 1829 regulator-max-microvolt = <3300000>; 1830 1831 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1832 enable-active-high; 1833 1834 vin-supply = <&vdd_5v0_sys>; 1835 }; 1836 1837 vdd_cpu: regulator-vdd-cpu { 1838 compatible = "regulator-fixed"; 1839 1840 regulator-name = "VDD_CPU"; 1841 regulator-min-microvolt = <5000000>; 1842 regulator-max-microvolt = <5000000>; 1843 regulator-always-on; 1844 regulator-boot-on; 1845 1846 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1847 enable-active-high; 1848 1849 vin-supply = <&vdd_5v0_sys>; 1850 }; 1851 1852 vdd_gpu: regulator-vdd-gpu { 1853 compatible = "pwm-regulator"; 1854 pwms = <&pwm 1 8000>; 1855 1856 regulator-name = "VDD_GPU"; 1857 regulator-min-microvolt = <710000>; 1858 regulator-max-microvolt = <1320000>; 1859 regulator-ramp-delay = <80>; 1860 regulator-enable-ramp-delay = <2000>; 1861 regulator-settling-time-us = <160>; 1862 1863 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1864 vin-supply = <&vdd_5v0_sys>; 1865 }; 1866 1867 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1868 compatible = "regulator-fixed"; 1869 1870 regulator-name = "AVDD_IO_EDP_1V05"; 1871 regulator-min-microvolt = <1050000>; 1872 regulator-max-microvolt = <1050000>; 1873 1874 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1875 enable-active-high; 1876 1877 vin-supply = <&avdd_1v05_pll>; 1878 }; 1879 1880 vdd_5v0_usb: regulator-vdd-5v-usb { 1881 compatible = "regulator-fixed"; 1882 1883 regulator-name = "VDD_5V_USB"; 1884 regulator-min-microvolt = <50000000>; 1885 regulator-max-microvolt = <50000000>; 1886 1887 vin-supply = <&vdd_5v0_sys>; 1888 }; 1889 1890 sound { 1891 compatible = "nvidia,tegra210-audio-graph-card"; 1892 status = "okay"; 1893 1894 dais = /* FE */ 1895 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1896 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1897 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1898 <&admaif10_port>, 1899 /* Router */ 1900 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1901 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1902 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1903 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1904 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1905 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1906 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1907 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1908 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1909 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1910 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1911 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1912 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1913 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1914 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1915 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, 1916 /* HW accelerators */ 1917 <&sfc1_out_port>, <&sfc2_out_port>, 1918 <&sfc3_out_port>, <&sfc4_out_port>, 1919 <&mvc1_out_port>, <&mvc2_out_port>, 1920 <&amx1_out_port>, <&amx2_out_port>, 1921 <&adx1_out1_port>, <&adx1_out2_port>, 1922 <&adx1_out3_port>, <&adx1_out4_port>, 1923 <&adx2_out1_port>, <&adx2_out2_port>, 1924 <&adx2_out3_port>, <&adx2_out4_port>, 1925 <&mixer_out1_port>, <&mixer_out2_port>, 1926 <&mixer_out3_port>, <&mixer_out4_port>, 1927 <&mixer_out5_port>, 1928 <&ope1_out_port>, <&ope2_out_port>, 1929 /* I/O DAP Ports */ 1930 <&i2s3_port>, <&i2s4_port>, 1931 <&dmic1_port>, <&dmic2_port>; 1932 1933 label = "NVIDIA Jetson Nano APE"; 1934 }; 1935 1936 thermal-zones { 1937 cpu-thermal { 1938 trips { 1939 cpu_trip_critical: critical { 1940 temperature = <96500>; 1941 hysteresis = <0>; 1942 type = "critical"; 1943 }; 1944 1945 cpu_trip_hot: hot { 1946 temperature = <70000>; 1947 hysteresis = <2000>; 1948 type = "hot"; 1949 }; 1950 1951 cpu_trip_active: active { 1952 temperature = <50000>; 1953 hysteresis = <2000>; 1954 type = "active"; 1955 }; 1956 1957 cpu_trip_passive: passive { 1958 temperature = <30000>; 1959 hysteresis = <2000>; 1960 type = "passive"; 1961 }; 1962 }; 1963 1964 cooling-maps { 1965 cpu-critical { 1966 cooling-device = <&fan 3 3>; 1967 trip = <&cpu_trip_critical>; 1968 }; 1969 1970 cpu-hot { 1971 cooling-device = <&fan 2 2>; 1972 trip = <&cpu_trip_hot>; 1973 }; 1974 1975 cpu-active { 1976 cooling-device = <&fan 1 1>; 1977 trip = <&cpu_trip_active>; 1978 }; 1979 1980 cpu-passive { 1981 cooling-device = <&fan 0 0>; 1982 trip = <&cpu_trip_passive>; 1983 }; 1984 }; 1985 }; 1986 }; 1987}; 1988