1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Radxa Limited 4 * Copyright (C) 2024 Collabora Ltd. 5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 14#include <dt-bindings/spmi/spmi.h> 15#include <dt-bindings/usb/pd.h> 16 17/ { 18 model = "Radxa NIO 12L"; 19 chassis-type = "embedded"; 20 compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; 21 22 aliases { 23 i2c0 = &i2c2; 24 i2c1 = &i2c3; 25 i2c2 = &i2c4; 26 i2c3 = &i2c0; 27 i2c4 = &i2c1; 28 ethernet0 = ð 29 serial0 = &uart0; 30 serial1 = &uart1; 31 spi0 = &spi1; 32 spi1 = &spi2; 33 }; 34 35 chosen { 36 stdout-path = "serial0:921600n8"; 37 }; 38 39 firmware { 40 optee { 41 compatible = "linaro,optee-tz"; 42 method = "smc"; 43 }; 44 }; 45 46 memory@40000000 { 47 device_type = "memory"; 48 reg = <0 0x40000000 0x1 0x0>; 49 }; 50 51 backlight: backlight { 52 compatible = "pwm-backlight"; 53 brightness-levels = <0 1023>; 54 default-brightness-level = <576>; 55 enable-gpios = <&pio 107 GPIO_ACTIVE_HIGH>; 56 num-interpolated-steps = <1023>; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&dsi0_backlight_pins>; 59 pwms = <&disp_pwm0 0 500000>; 60 status = "disabled"; 61 }; 62 63 wifi_vreg: regulator-wifi-3v3-en { 64 compatible = "regulator-fixed"; 65 regulator-name = "wifi_3v3_en"; 66 regulator-always-on; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 enable-active-high; 70 gpio = <&pio 67 GPIO_ACTIVE_HIGH>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&wifi_vreg_pins>; 73 vin-supply = <&vsys>; 74 }; 75 76 /* system wide switching 5.0V power rail */ 77 vsys: regulator-vsys { 78 compatible = "regulator-fixed"; 79 regulator-name = "vsys"; 80 regulator-always-on; 81 regulator-boot-on; 82 regulator-min-microvolt = <5000000>; 83 regulator-max-microvolt = <5000000>; 84 vin-supply = <&vcc5v0_vsys>; 85 }; 86 87 vsys_buck: regulator-vsys-buck { 88 compatible = "regulator-fixed"; 89 regulator-name = "vsys_buck"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <5000000>; 93 regulator-max-microvolt = <5000000>; 94 vin-supply = <&vcc5v0_vsys>; 95 }; 96 97 /* Rail from power-only "TYPE C DC" port */ 98 vcc5v0_vsys: regulator-vcc5v0-sys { 99 compatible = "regulator-fixed"; 100 regulator-name = "vcc5v0_sys"; 101 regulator-always-on; 102 regulator-boot-on; 103 }; 104 105 reserved-memory { 106 #address-cells = <2>; 107 #size-cells = <2>; 108 ranges; 109 110 /* 111 * 12 MiB reserved for OP-TEE (BL32) 112 * +-----------------------+ 0x43e0_0000 113 * | SHMEM 2MiB | 114 * +-----------------------+ 0x43c0_0000 115 * | | TA_RAM 8MiB | 116 * + TZDRAM +--------------+ 0x4340_0000 117 * | | TEE_RAM 2MiB | 118 * +-----------------------+ 0x4320_0000 119 */ 120 optee_reserved: optee@43200000 { 121 reg = <0 0x43200000 0 0xc00000>; 122 no-map; 123 }; 124 125 scp_mem: memory@50000000 { 126 compatible = "shared-dma-pool"; 127 reg = <0 0x50000000 0 0x2900000>; 128 no-map; 129 }; 130 131 vpu_mem: memory@53000000 { 132 compatible = "shared-dma-pool"; 133 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 134 }; 135 136 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 137 bl31_secmon_mem: memory@54600000 { 138 reg = <0 0x54600000 0x0 0x200000>; 139 no-map; 140 }; 141 142 afe_mem: memory@60000000 { 143 compatible = "shared-dma-pool"; 144 reg = <0 0x60000000 0 0x1100000>; 145 no-map; 146 }; 147 148 apu_mem: memory@62000000 { 149 compatible = "shared-dma-pool"; 150 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 151 }; 152 }; 153}; 154 155&cpu0 { 156 cpu-supply = <&mt6359_vcore_buck_reg>; 157}; 158 159&cpu1 { 160 cpu-supply = <&mt6359_vcore_buck_reg>; 161}; 162 163&cpu2 { 164 cpu-supply = <&mt6359_vcore_buck_reg>; 165}; 166 167&cpu3 { 168 cpu-supply = <&mt6359_vcore_buck_reg>; 169}; 170 171&cpu4 { 172 cpu-supply = <&mt6315_6_vbuck1>; 173}; 174 175&cpu5 { 176 cpu-supply = <&mt6315_6_vbuck1>; 177}; 178 179&cpu6 { 180 cpu-supply = <&mt6315_6_vbuck1>; 181}; 182 183&cpu7 { 184 cpu-supply = <&mt6315_6_vbuck1>; 185}; 186 187&dither0_out { 188 remote-endpoint = <&dsi0_in>; 189}; 190 191&dsi0 { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 195 ports { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 port@0 { 200 reg = <0>; 201 dsi0_in: endpoint { 202 remote-endpoint = <&dither0_out>; 203 }; 204 }; 205 206 port@1 { 207 reg = <1>; 208 dsi0_out: endpoint { }; 209 }; 210 }; 211}; 212 213ð { 214 phy-mode = "rgmii-rxid"; 215 phy-handle = <&rgmii_phy>; 216 pinctrl-names = "default", "sleep"; 217 pinctrl-0 = <ð_default_pins>; 218 pinctrl-1 = <ð_sleep_pins>; 219 mediatek,tx-delay-ps = <2030>; 220 mediatek,mac-wol; 221 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; 222 snps,reset-delays-us = <0 20000 100000>; 223 status = "okay"; 224 225 mdio { 226 rgmii_phy: ethernet-phy@1 { 227 compatible = "ethernet-phy-id001c.c916"; 228 reg = <0x1>; 229 }; 230 }; 231}; 232 233&gpu { 234 mali-supply = <&mt6315_7_vbuck1>; 235 status = "okay"; 236}; 237 238&i2c2 { 239 clock-frequency = <400000>; 240 pinctrl-0 = <&i2c2_pins>; 241 pinctrl-names = "default"; 242 status = "okay"; 243 244 typec-mux@48 { 245 compatible = "ite,it5205"; 246 reg = <0x48>; 247 248 mode-switch; 249 orientation-switch; 250 251 vcc-supply = <&mt6359_vibr_ldo_reg>; 252 253 port { 254 it5205_sbu_mux: endpoint { 255 remote-endpoint = <&typec_con_mux>; 256 }; 257 }; 258 }; 259}; 260 261&i2c4 { 262 clock-frequency = <400000>; 263 pinctrl-0 = <&i2c4_pins>; 264 pinctrl-names = "default"; 265 status = "okay"; 266 267 /* I2C4 exposed at 39-pins MIPI-LCD connector */ 268}; 269 270&i2c6 { 271 clock-frequency = <400000>; 272 pinctrl-0 = <&i2c6_pins>; 273 pinctrl-names = "default"; 274 status = "okay"; 275 276 mt6360: pmic@34 { 277 compatible = "mediatek,mt6360"; 278 reg = <0x34>; 279 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; 280 interrupt-names = "IRQB"; 281 interrupt-controller; 282 #interrupt-cells = <1>; 283 pinctrl-0 = <&mt6360_pins>; 284 285 charger { 286 compatible = "mediatek,mt6360-chg"; 287 richtek,vinovp-microvolt = <14500000>; 288 289 otg_vbus_regulator: usb-otg-vbus-regulator { 290 regulator-name = "usb-otg-vbus"; 291 regulator-min-microvolt = <4425000>; 292 regulator-max-microvolt = <5825000>; 293 }; 294 }; 295 296 regulator { 297 compatible = "mediatek,mt6360-regulator"; 298 LDO_VIN1-supply = <&vsys_buck>; 299 LDO_VIN3-supply = <&mt6360_buck2>; 300 301 mt6360_buck1: buck1 { 302 regulator-name = "emi_vdd2"; 303 regulator-min-microvolt = <300000>; 304 regulator-max-microvolt = <1300000>; 305 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 306 MT6360_OPMODE_LP 307 MT6360_OPMODE_ULP>; 308 regulator-always-on; 309 }; 310 311 mt6360_buck2: buck2 { 312 regulator-name = "emi_vddq"; 313 regulator-min-microvolt = <300000>; 314 regulator-max-microvolt = <1300000>; 315 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 316 MT6360_OPMODE_LP 317 MT6360_OPMODE_ULP>; 318 regulator-always-on; 319 }; 320 321 mt6360_ldo1: ldo1 { 322 regulator-name = "ext_lcd_3v3"; 323 regulator-min-microvolt = <3300000>; 324 regulator-max-microvolt = <3300000>; 325 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 326 MT6360_OPMODE_LP>; 327 regulator-always-on; 328 }; 329 330 mt6360_ldo2: ldo2 { 331 regulator-name = "panel1_p1v8"; 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 335 MT6360_OPMODE_LP>; 336 }; 337 338 mt6360_ldo3: ldo3 { 339 regulator-name = "vmc_pmu"; 340 regulator-min-microvolt = <1200000>; 341 regulator-max-microvolt = <3600000>; 342 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 343 MT6360_OPMODE_LP>; 344 }; 345 346 mt6360_ldo5: ldo5 { 347 regulator-name = "vmch_pmu"; 348 regulator-min-microvolt = <3300000>; 349 regulator-max-microvolt = <3300000>; 350 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 351 MT6360_OPMODE_LP>; 352 regulator-always-on; 353 }; 354 355 mt6360_ldo6: ldo6 { 356 regulator-name = "mt6360_ldo6"; /* Test point */ 357 regulator-min-microvolt = <500000>; 358 regulator-max-microvolt = <2100000>; 359 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 360 MT6360_OPMODE_LP>; 361 }; 362 363 mt6360_ldo7: ldo7 { 364 regulator-name = "emi_vmddr_en"; 365 regulator-min-microvolt = <500000>; 366 regulator-max-microvolt = <2100000>; 367 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 368 MT6360_OPMODE_LP>; 369 regulator-always-on; 370 }; 371 }; 372 373 typec { 374 compatible = "mediatek,mt6360-tcpc"; 375 interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>; 376 interrupt-names = "PD_IRQB"; 377 378 connector { 379 compatible = "usb-c-connector"; 380 label = "USB-C"; 381 data-role = "dual"; 382 op-sink-microwatt = <10000000>; 383 power-role = "dual"; 384 try-power-role = "sink"; 385 386 source-pdos = <PDO_FIXED(5000, 1000, 387 PDO_FIXED_DUAL_ROLE | 388 PDO_FIXED_DATA_SWAP)>; 389 sink-pdos = <PDO_FIXED(5000, 3000, 390 PDO_FIXED_DUAL_ROLE | 391 PDO_FIXED_DATA_SWAP)>; 392 393 ports { 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 port@0 { 398 reg = <0>; 399 typec_con_hs: endpoint { 400 remote-endpoint = <&mtu3_hs0_role_sw>; 401 }; 402 }; 403 404 port@2 { 405 reg = <2>; 406 typec_con_mux: endpoint { 407 remote-endpoint = <&it5205_sbu_mux>; 408 }; 409 }; 410 }; 411 }; 412 }; 413 }; 414}; 415 416&mfg0 { 417 domain-supply = <&mt6315_7_vbuck1>; 418}; 419 420&mfg1 { 421 domain-supply = <&mt6359_vsram_others_ldo_reg>; 422}; 423 424/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ 425&mmc0 { 426 pinctrl-names = "default", "state_uhs"; 427 pinctrl-0 = <&mmc0_default_pins>; 428 pinctrl-1 = <&mmc0_uhs_pins>; 429 bus-width = <8>; 430 max-frequency = <200000000>; 431 hs400-ds-delay = <0x14c11>; 432 cap-mmc-highspeed; 433 cap-mmc-hw-reset; 434 mmc-hs200-1_8v; 435 mmc-hs400-1_8v; 436 no-sdio; 437 no-sd; 438 non-removable; 439 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 440 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 441 status = "okay"; 442}; 443 444/* MMC1 Controller: MicroSD card slot */ 445&mmc1 { 446 pinctrl-names = "default", "state_uhs"; 447 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>; 448 pinctrl-1 = <&mmc1_default_pins>; 449 bus-width = <4>; 450 max-frequency = <200000000>; 451 cap-sd-highspeed; 452 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; 453 no-mmc; 454 no-sdio; 455 sd-uhs-sdr50; 456 sd-uhs-sdr104; 457 vmmc-supply = <&mt6360_ldo5>; 458 vqmmc-supply = <&mt6360_ldo3>; 459 status = "okay"; 460}; 461 462&mt6359_vaud18_ldo_reg { 463 regulator-always-on; 464}; 465 466&mt6359_vbbck_ldo_reg { 467 regulator-always-on; 468}; 469 470/* For USB Hub */ 471&mt6359_vcamio_ldo_reg { 472 regulator-always-on; 473}; 474 475&mt6359_vcn33_2_bt_ldo_reg { 476 regulator-min-microvolt = <3300000>; 477 regulator-max-microvolt = <3300000>; 478}; 479 480&mt6359_vcore_buck_reg { 481 regulator-always-on; 482}; 483 484&mt6359_vgpu11_buck_reg { 485 regulator-always-on; 486}; 487 488&mt6359_vproc1_buck_reg { 489 regulator-always-on; 490}; 491 492&mt6359_vproc2_buck_reg { 493 regulator-always-on; 494}; 495 496&mt6359_vpu_buck_reg { 497 regulator-always-on; 498}; 499 500&mt6359_vrf12_ldo_reg { 501 regulator-always-on; 502}; 503 504&mt6359_vsram_md_ldo_reg { 505 regulator-always-on; 506}; 507 508/* for GPU SRAM */ 509&mt6359_vsram_others_ldo_reg { 510 regulator-min-microvolt = <750000>; 511 regulator-max-microvolt = <750000>; 512}; 513 514&pio { 515 mediatek,rsel-resistance-in-si-unit; 516 517 dsi0_backlight_pins: dsi0-backlight-pins { 518 pins-backlight-en { 519 pinmux = <PINMUX_GPIO107__FUNC_GPIO107>; 520 output-high; 521 }; 522 }; 523 524 eth_default_pins: eth-default-pins { 525 pins-cc { 526 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 527 <PINMUX_GPIO86__FUNC_GBE_RXC>, 528 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 529 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 530 drive-strength = <8>; 531 }; 532 533 pins-mdio { 534 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 535 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 536 input-enable; 537 }; 538 539 pins-power { 540 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 541 <PINMUX_GPIO92__FUNC_GPIO92>; 542 output-high; 543 }; 544 545 pins-rst { 546 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>; 547 }; 548 549 pins-rxd { 550 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 551 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 552 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 553 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 554 }; 555 556 pins-txd { 557 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 558 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 559 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 560 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 561 drive-strength = <8>; 562 }; 563 }; 564 565 eth_sleep_pins: eth-sleep-pins { 566 pins-cc { 567 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 568 <PINMUX_GPIO86__FUNC_GPIO86>, 569 <PINMUX_GPIO87__FUNC_GPIO87>, 570 <PINMUX_GPIO88__FUNC_GPIO88>; 571 }; 572 573 pins-mdio { 574 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 575 <PINMUX_GPIO90__FUNC_GPIO90>; 576 bias-disable; 577 input-disable; 578 }; 579 580 pins-rxd { 581 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 582 <PINMUX_GPIO82__FUNC_GPIO82>, 583 <PINMUX_GPIO83__FUNC_GPIO83>, 584 <PINMUX_GPIO84__FUNC_GPIO84>; 585 }; 586 587 pins-txd { 588 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 589 <PINMUX_GPIO78__FUNC_GPIO78>, 590 <PINMUX_GPIO79__FUNC_GPIO79>, 591 <PINMUX_GPIO80__FUNC_GPIO80>; 592 }; 593 }; 594 595 i2c2_pins: i2c2-pins { 596 pins-bus { 597 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 598 <PINMUX_GPIO13__FUNC_SCL2>; 599 bias-pull-up = <1000>; 600 drive-strength = <6>; 601 drive-strength-microamp = <1000>; 602 }; 603 }; 604 605 i2c4_pins: i2c4-pins { 606 pins-bus { 607 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 608 <PINMUX_GPIO17__FUNC_SCL4>; 609 bias-pull-up = <1000>; 610 drive-strength-microamp = <1000>; 611 }; 612 }; 613 614 i2c6_pins: i2c6-pins { 615 pins { 616 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 617 <PINMUX_GPIO26__FUNC_SCL6>; 618 bias-disable; 619 }; 620 }; 621 622 mmc0_default_pins: mmc0-default-pins { 623 pins-clk { 624 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 625 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 626 drive-strength = <6>; 627 }; 628 629 pins-cmd-dat { 630 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 631 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 632 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 633 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 634 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 635 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 636 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 637 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 638 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 639 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 640 drive-strength = <6>; 641 input-enable; 642 }; 643 644 pins-rst { 645 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 646 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 647 drive-strength = <6>; 648 }; 649 }; 650 651 mmc0_uhs_pins: mmc0-uhs-pins { 652 pins-clk { 653 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 654 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 655 drive-strength = <8>; 656 }; 657 658 pins-cmd-dat { 659 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 660 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 661 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 662 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 663 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 664 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 665 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 666 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 667 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 668 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 669 drive-strength = <8>; 670 input-enable; 671 }; 672 673 pins-ds { 674 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 675 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 676 drive-strength = <8>; 677 }; 678 679 pins-rst { 680 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 681 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 682 drive-strength = <8>; 683 }; 684 }; 685 686 mmc1_default_pins: mmc1-default-pins { 687 pins-clk { 688 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 689 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 690 drive-strength = <8>; 691 }; 692 693 pins-cmd-dat { 694 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 695 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 696 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 697 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 698 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 699 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 700 drive-strength = <8>; 701 input-enable; 702 }; 703 }; 704 705 mmc1_pins_detect: mmc1-detect-pins { 706 pins-insert { 707 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 708 bias-pull-up; 709 }; 710 }; 711 712 mt6360_pins: mt6360-pins { 713 pins-irq { 714 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>, 715 <PINMUX_GPIO101__FUNC_GPIO101>; 716 input-enable; 717 bias-pull-up; 718 }; 719 }; 720 721 panel_default_pins: panel-pins { 722 pins-rst { 723 pinmux = <PINMUX_GPIO108__FUNC_GPIO108>; 724 bias-pull-up; 725 }; 726 }; 727 728 pcie0_default_pins: pcie0-default-pins { 729 pins-bus { 730 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 731 <PINMUX_GPIO20__FUNC_PERSTN>, 732 <PINMUX_GPIO21__FUNC_CLKREQN>; 733 bias-pull-up; 734 }; 735 }; 736 737 pcie1_default_pins: pcie1-default-pins { 738 pins-bus { 739 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>, 740 <PINMUX_GPIO1__FUNC_CLKREQN_1>, 741 <PINMUX_GPIO2__FUNC_WAKEN_1>; 742 bias-disable; 743 }; 744 }; 745 746 pwm0_default_pins: pwm0-pins { 747 pins-disp-pwm { 748 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; 749 }; 750 }; 751 752 spi1_pins: spi1-default-pins { 753 pins-bus { 754 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 755 <PINMUX_GPIO137__FUNC_SPIM1_CLK>, 756 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 757 <PINMUX_GPIO139__FUNC_SPIM1_MI>; 758 bias-disable; 759 }; 760 }; 761 762 spi2_pins: spi2-default-pins { 763 pins-bus { 764 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, 765 <PINMUX_GPIO141__FUNC_SPIM2_CLK>, 766 <PINMUX_GPIO142__FUNC_SPIM2_MO>, 767 <PINMUX_GPIO143__FUNC_SPIM2_MI>; 768 bias-disable; 769 }; 770 }; 771 772 touch_pins: touch-pins { 773 pins-touch-int { 774 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; 775 input-enable; 776 bias-disable; 777 }; 778 779 pins-touch-rst { 780 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; 781 output-high; 782 }; 783 }; 784 785 uart0_pins: uart0-pins { 786 pins-bus { 787 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 788 <PINMUX_GPIO99__FUNC_URXD0>; 789 }; 790 }; 791 792 uart1_pins: uart1-pins { 793 pins-bus { 794 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>, 795 <PINMUX_GPIO103__FUNC_URXD1>; 796 }; 797 }; 798 799 usb3_port0_pins: usb3p0-default-pins { 800 pins-vbus { 801 pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; 802 input-enable; 803 }; 804 }; 805 806 usb2_port0_pins: usb2p0-default-pins { 807 pins-iddig { 808 pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>; 809 input-enable; 810 bias-pull-up; 811 }; 812 813 pins-vbus { 814 pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>; 815 output-low; 816 }; 817 }; 818 819 wifi_vreg_pins: wifi-vreg-pins { 820 pins-wifi-pmu-en { 821 pinmux = <PINMUX_GPIO65__FUNC_GPIO65>; 822 output-high; 823 }; 824 825 pins-wifi-vreg-en { 826 pinmux = <PINMUX_GPIO67__FUNC_GPIO67>; 827 }; 828 }; 829}; 830 831&pcie0 { 832 pinctrl-names = "default"; 833 pinctrl-0 = <&pcie0_default_pins>; 834 status = "okay"; 835}; 836 837&pcie1 { 838 pinctrl-names = "default"; 839 pinctrl-0 = <&pcie1_default_pins>; 840 status = "okay"; 841}; 842 843&pciephy { 844 status = "okay"; 845}; 846 847&pmic { 848 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 849}; 850 851&scp { 852 memory-region = <&scp_mem>; 853 status = "okay"; 854}; 855 856&spi1 { 857 /* Exposed at 40 pin connector */ 858 pinctrl-0 = <&spi1_pins>; 859 pinctrl-names = "default"; 860 mediatek,pad-select = <0>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 status = "okay"; 864}; 865 866&spi2 { 867 /* Exposed at 40 pin connector */ 868 pinctrl-0 = <&spi2_pins>; 869 pinctrl-names = "default"; 870 mediatek,pad-select = <0>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 status = "okay"; 874}; 875 876&spmi { 877 #address-cells = <2>; 878 #size-cells = <0>; 879 880 mt6315_6: pmic@6 { 881 compatible = "mediatek,mt6315-regulator"; 882 reg = <0x6 SPMI_USID>; 883 884 regulators { 885 mt6315_6_vbuck1: vbuck1 { 886 regulator-name = "Vbcpu"; 887 regulator-min-microvolt = <300000>; 888 regulator-max-microvolt = <1193750>; 889 regulator-enable-ramp-delay = <256>; 890 regulator-allowed-modes = <0 1 2>; 891 regulator-always-on; 892 }; 893 }; 894 }; 895 896 mt6315_7: pmic@7 { 897 compatible = "mediatek,mt6315-regulator"; 898 reg = <0x7 SPMI_USID>; 899 900 regulators { 901 mt6315_7_vbuck1: vbuck1 { 902 regulator-name = "Vgpu"; 903 regulator-min-microvolt = <300000>; 904 regulator-max-microvolt = <1193750>; 905 regulator-enable-ramp-delay = <256>; 906 regulator-allowed-modes = <0 1 2>; 907 }; 908 }; 909 }; 910}; 911 912&u3phy0 { 913 status = "okay"; 914}; 915 916&u3phy1 { 917 status = "okay"; 918}; 919 920&u3phy2 { 921 status = "okay"; 922}; 923 924&uart0 { 925 /* Exposed at 40 pin connector */ 926 pinctrl-0 = <&uart0_pins>; 927 pinctrl-names = "default"; 928 status = "okay"; 929}; 930 931&uart1 { 932 /* Exposed at 40 pin connector */ 933 pinctrl-0 = <&uart1_pins>; 934 pinctrl-names = "default"; 935 status = "okay"; 936}; 937 938&ssusb0 { 939 pinctrl-names = "default"; 940 pinctrl-0 = <&usb3_port0_pins>; 941 role-switch-default-mode = "host"; 942 usb-role-switch; 943 vusb33-supply = <&mt6359_vusb_ldo_reg>; 944 status = "okay"; 945 946 port { 947 mtu3_hs0_role_sw: endpoint { 948 remote-endpoint = <&typec_con_hs>; 949 }; 950 }; 951}; 952 953&ssusb2 { 954 pinctrl-names = "default"; 955 pinctrl-0 = <&usb2_port0_pins>; 956 vusb33-supply = <&mt6359_vusb_ldo_reg>; 957 status = "okay"; 958}; 959 960&xhci0 { 961 vbus-supply = <&otg_vbus_regulator>; 962 status = "okay"; 963}; 964 965&xhci1 { 966 phys = <&u2port1 PHY_TYPE_USB2>; 967 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 968 usb2-lpm-disable; 969 vusb33-supply = <&mt6359_vusb_ldo_reg>; 970 vbus-supply = <&vsys>; 971 mediatek,u3p-dis-msk = <1>; 972 status = "okay"; 973}; 974 975&xhci2 { 976 vbus-supply = <&vsys>; 977 status = "okay"; 978}; 979