1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include <dt-bindings/gpio/gpio.h> 7#include "mt8188.dtsi" 8#include "mt6359.dtsi" 9 10/ { 11 aliases { 12 dsi0 = &disp_dsi0; 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 mmc0 = &mmc0; 21 serial0 = &uart0; 22 }; 23 24 backlight_lcd0: backlight-lcd0 { 25 compatible = "pwm-backlight"; 26 brightness-levels = <0 1023>; 27 default-brightness-level = <576>; 28 enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; 29 num-interpolated-steps = <1023>; 30 power-supply = <&ppvar_sys>; 31 pwms = <&disp_pwm0 0 500000>; 32 }; 33 34 chosen { 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 dmic-codec { 39 compatible = "dmic-codec"; 40 num-channels = <2>; 41 wakeup-delay-ms = <100>; 42 }; 43 44 memory@40000000 { 45 device_type = "memory"; 46 /* The size will be filled in by the bootloader */ 47 reg = <0 0x40000000 0 0>; 48 }; 49 50 /* system wide LDO 1.8V power rail */ 51 pp1800_ldo_z1: regulator-pp1800-ldo-z1 { 52 compatible = "regulator-fixed"; 53 regulator-name = "pp1800_ldo_z1"; 54 /* controlled by PP3300_Z1 */ 55 regulator-always-on; 56 regulator-boot-on; 57 regulator-min-microvolt = <1800000>; 58 regulator-max-microvolt = <1800000>; 59 vin-supply = <&pp3300_z1>; 60 }; 61 62 /* separately switched 3.3V power rail */ 63 pp3300_s3: regulator-pp3300-s3 { 64 compatible = "regulator-fixed"; 65 regulator-name = "pp3300_s3"; 66 /* controlled by PMIC */ 67 regulator-always-on; 68 regulator-boot-on; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&pp3300_z1>; 72 }; 73 74 /* system wide 3.3V power rail */ 75 pp3300_z1: regulator-pp3300-z1 { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp3300_z1"; 78 /* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */ 79 regulator-always-on; 80 regulator-boot-on; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 vin-supply = <&ppvar_sys>; 84 }; 85 86 pp3300_wlan: regulator-pp3300-wlan { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp3300_wlan"; 89 regulator-always-on; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 enable-active-high; 93 gpio = <&pio 12 GPIO_ACTIVE_HIGH>; 94 pinctrl-0 = <&wlan_en>; 95 pinctrl-names = "default"; 96 vin-supply = <&pp3300_z1>; 97 }; 98 99 /* system wide 4.2V power rail */ 100 pp4200_s5: regulator-pp4200-s5 { 101 compatible = "regulator-fixed"; 102 regulator-name = "pp4200_s5"; 103 /* controlled by EC */ 104 regulator-always-on; 105 regulator-boot-on; 106 regulator-min-microvolt = <4200000>; 107 regulator-max-microvolt = <4200000>; 108 vin-supply = <&ppvar_sys>; 109 }; 110 111 /* system wide 5.0V power rail */ 112 pp5000_z1: regulator-pp5000-z1 { 113 compatible = "regulator-fixed"; 114 regulator-name = "pp5000_z1"; 115 /* controlled by EC */ 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <5000000>; 119 regulator-max-microvolt = <5000000>; 120 vin-supply = <&ppvar_sys>; 121 }; 122 123 pp5000_usb_vbus: regulator-pp5000-usb-vbus { 124 compatible = "regulator-fixed"; 125 regulator-name = "pp5000_usb_vbus"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 enable-active-high; 129 gpio = <&pio 150 GPIO_ACTIVE_HIGH>; 130 vin-supply = <&pp5000_z1>; 131 }; 132 133 /* system wide semi-regulated power rail from battery or USB */ 134 ppvar_sys: regulator-ppvar-sys { 135 compatible = "regulator-fixed"; 136 regulator-name = "ppvar_sys"; 137 regulator-always-on; 138 regulator-boot-on; 139 }; 140 141 ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd { 142 compatible = "regulator-fixed"; 143 regulator-name = "ppvar_mipi_disp_avdd"; 144 enable-active-high; 145 gpio = <&pio 3 GPIO_ACTIVE_HIGH>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&mipi_disp_avdd_en>; 148 vin-supply = <&pp5000_z1>; 149 }; 150 151 ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee { 152 compatible = "regulator-fixed"; 153 regulator-name = "ppvar_mipi_disp_avee"; 154 regulator-enable-ramp-delay = <10000>; 155 enable-active-high; 156 gpio = <&pio 4 GPIO_ACTIVE_HIGH>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&mipi_disp_avee_en>; 159 vin-supply = <&pp5000_z1>; 160 }; 161 162 reserved_memory: reserved-memory { 163 #address-cells = <2>; 164 #size-cells = <2>; 165 ranges; 166 167 apu_mem: memory@55000000 { 168 compatible = "shared-dma-pool"; 169 reg = <0 0x55000000 0 0x1400000>; 170 }; 171 172 adsp_mem: memory@60000000 { 173 compatible = "shared-dma-pool"; 174 reg = <0 0x60000000 0 0xf00000>; 175 no-map; 176 }; 177 178 afe_dma_mem: memory@60f00000 { 179 compatible = "shared-dma-pool"; 180 reg = <0 0x60f00000 0 0x100000>; 181 no-map; 182 }; 183 184 adsp_dma_mem: memory@61000000 { 185 compatible = "shared-dma-pool"; 186 reg = <0 0x61000000 0 0x100000>; 187 no-map; 188 }; 189 }; 190}; 191 192&adsp { 193 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&adsp_uart_pins>; 196 status = "okay"; 197}; 198 199&afe { 200 memory-region = <&afe_dma_mem>; 201 mediatek,etdm-out1-cowork-source = <0>; /* in1 */ 202 mediatek,etdm-in2-cowork-source = <3>; /* out2 */ 203 status = "okay"; 204}; 205 206&auxadc { 207 status = "okay"; 208}; 209 210&cam_vcore { 211 domain-supply = <&mt6359_vproc1_buck_reg>; 212}; 213 214/* 215 * Geralt is the reference design and doesn't have target TDP. 216 * Ciri is (currently) the only device following Geralt, and its 217 * TDP target is 90 degrees. 218 **/ 219&cpu_little0_alert0 { 220 temperature = <90000>; 221 hysteresis = <2000>; 222 type = "passive"; 223}; 224 225&cpu_little1_alert0 { 226 temperature = <90000>; 227 hysteresis = <2000>; 228 type = "passive"; 229}; 230 231&cpu_little2_alert0 { 232 temperature = <90000>; 233 hysteresis = <2000>; 234 type = "passive"; 235}; 236 237&cpu_little3_alert0 { 238 temperature = <90000>; 239 hysteresis = <2000>; 240 type = "passive"; 241}; 242 243&cpu_big0_alert0 { 244 temperature = <90000>; 245 hysteresis = <2000>; 246 type = "passive"; 247}; 248 249&cpu_big1_alert0 { 250 temperature = <90000>; 251 hysteresis = <2000>; 252 type = "passive"; 253}; 254 255&disp_dsi0 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 status = "okay"; 259 260 dsi_panel: panel@0 { 261 /* Compatible string for different panels can be found in each device dts */ 262 reg = <0>; 263 enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&mipi_dsi_pins>; 266 267 backlight = <&backlight_lcd0>; 268 avdd-supply = <&ppvar_mipi_disp_avdd>; 269 avee-supply = <&ppvar_mipi_disp_avee>; 270 pp1800-supply = <&mt6359_vm18_ldo_reg>; 271 rotation = <270>; 272 273 status = "okay"; 274 275 port { 276 dsi_panel_in: endpoint { 277 remote-endpoint = <&dsi0_out>; 278 }; 279 }; 280 }; 281 282 ports { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 286 port@0 { 287 reg = <0>; 288 dsi0_in: endpoint { 289 remote-endpoint = <&dither0_out>; 290 }; 291 }; 292 293 port@1 { 294 reg = <1>; 295 dsi0_out: endpoint { 296 remote-endpoint = <&dsi_panel_in>; 297 }; 298 }; 299 }; 300}; 301 302&disp_pwm0 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&disp_pwm0_pins>; 305 status = "okay"; 306}; 307 308&disp_pwm1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&disp_pwm1_pins>; 311}; 312 313&dither0_in { 314 remote-endpoint = <&postmask0_out>; 315}; 316 317&dither0_out { 318 remote-endpoint = <&dsi0_in>; 319}; 320 321ðdr0 { 322 ports { 323 #address-cells = <1>; 324 #size-cells = <0>; 325 326 port@0 { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0>; 330 331 ethdr0_in: endpoint@1 { 332 reg = <1>; 333 remote-endpoint = <&vdosys1_ep_ext>; 334 }; 335 }; 336 337 port@1 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <1>; 341 342 ethdr0_out: endpoint@1 { 343 reg = <1>; 344 remote-endpoint = <&merge5_in>; 345 }; 346 }; 347 }; 348}; 349 350&gamma0_out { 351 remote-endpoint = <&postmask0_in>; 352}; 353 354&dp_intf1 { 355 status = "okay"; 356 357 ports { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 port@0 { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0>; 365 366 dp_intf1_in: endpoint@1 { 367 reg = <1>; 368 remote-endpoint = <&merge5_out>; 369 }; 370 }; 371 372 port@1 { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 reg = <1>; 376 377 dp_intf1_out: endpoint@1 { 378 reg = <1>; 379 remote-endpoint = <&dptx_in>; 380 }; 381 }; 382 }; 383}; 384 385&dp_tx { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&dp_tx_hpd>; 388 #sound-dai-cells = <0>; 389 status = "okay"; 390 391 ports { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 port@0 { 396 reg = <0>; 397 dptx_in: endpoint { 398 remote-endpoint = <&dp_intf1_out>; 399 }; 400 }; 401 402 port@1 { 403 reg = <1>; 404 dptx_out: endpoint { 405 data-lanes = <0 1 2 3>; 406 }; 407 }; 408 }; 409}; 410 411&gpu { 412 mali-supply = <&mt6359_vproc2_buck_reg>; 413 status = "okay"; 414}; 415 416&i2c0 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c0_pins>; 419 clock-frequency = <400000>; 420 status = "okay"; 421}; 422 423&i2c1 { 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c1_pins>; 426 clock-frequency = <400000>; 427 status = "okay"; 428 429 tpm@50 { 430 compatible = "google,cr50"; 431 reg = <0x50>; 432 interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&gsc_int>; 435 }; 436}; 437 438&i2c2 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&i2c2_pins>; 441 clock-frequency = <400000>; 442 status = "okay"; 443}; 444 445&i2c3 { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&i2c3_pins>; 448 clock-frequency = <400000>; 449 status = "okay"; 450}; 451 452&i2c4 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&i2c4_pins>; 455 clock-frequency = <400000>; 456 status = "okay"; 457}; 458 459&i2c5 { 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c5_pins>; 462 clock-frequency = <400000>; 463 status = "okay"; 464}; 465 466&i2c6 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&i2c6_pins>; 469 clock-frequency = <400000>; 470 status = "okay"; 471}; 472 473&merge5 { 474 ports { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 478 port@0 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <0>; 482 483 merge5_in: endpoint@1 { 484 reg = <1>; 485 remote-endpoint = <ðdr0_out>; 486 }; 487 }; 488 489 port@1 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <1>; 493 494 merge5_out: endpoint@1 { 495 reg = <1>; 496 remote-endpoint = <&dp_intf1_in>; 497 }; 498 }; 499 }; 500}; 501 502&mfg0 { 503 domain-supply = <&mt6359_vproc2_buck_reg>; 504}; 505 506&mfg1 { 507 domain-supply = <&mt6359_vsram_others_ldo_reg>; 508}; 509 510&mipi_tx_config0 { 511 status = "okay"; 512}; 513 514&mmc0 { 515 bus-width = <8>; 516 cap-mmc-highspeed; 517 cap-mmc-hw-reset; 518 hs400-ds-delay = <0x1481b>; 519 max-frequency = <200000000>; 520 mmc-hs200-1_8v; 521 mmc-hs400-1_8v; 522 mmc-hs400-enhanced-strobe; 523 no-sd; 524 no-sdio; 525 non-removable; 526 pinctrl-names = "default", "state_uhs"; 527 pinctrl-0 = <&mmc0_pins_default>; 528 pinctrl-1 = <&mmc0_pins_uhs>; 529 supports-cqe; 530 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 531 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 532 status = "okay"; 533}; 534 535&mt6359codec { 536 mediatek,dmic-mode = <1>; /* one-wire */ 537 mediatek,mic-type-0 = <2>; /* DMIC */ 538 mediatek,mic-type-2 = <2>; /* DMIC */ 539}; 540 541&mt6359_vcore_buck_reg { 542 regulator-always-on; 543}; 544 545&mt6359_vgpu11_buck_reg { 546 regulator-always-on; 547}; 548 549&mt6359_vgpu11_sshub_buck_reg { 550 regulator-min-microvolt = <550000>; 551 regulator-max-microvolt = <550000>; 552 regulator-always-on; 553}; 554 555&mt6359_vio28_ldo_reg { 556 /delete-property/ regulator-always-on; 557}; 558 559&mt6359_vm18_ldo_reg { 560 /delete-property/ regulator-always-on; 561}; 562 563&mt6359_vmodem_buck_reg { 564 regulator-min-microvolt = <775000>; 565 regulator-max-microvolt = <775000>; 566}; 567 568&mt6359_vpa_buck_reg { 569 regulator-max-microvolt = <3100000>; 570}; 571 572&mt6359_vproc2_buck_reg { 573 /* 574 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to 575 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements. 576 */ 577 regulator-name = "ppvar_dvdd_vgpu"; 578 regulator-min-microvolt = <550000>; 579 regulator-max-microvolt = <800000>; 580 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 581 regulator-coupled-max-spread = <6250>; 582}; 583 584&mt6359_vpu_buck_reg { 585 regulator-always-on; 586}; 587 588&mt6359_vrf12_ldo_reg { 589 regulator-always-on; 590}; 591 592&mt6359_vsram_md_ldo_reg { 593 regulator-min-microvolt = <800000>; 594 regulator-max-microvolt = <800000>; 595}; 596 597&mt6359_vsram_others_ldo_reg { 598 regulator-name = "pp0850_dvdd_sram_gpu"; 599 regulator-min-microvolt = <750000>; 600 regulator-max-microvolt = <800000>; 601 regulator-coupled-with = <&mt6359_vproc2_buck_reg>; 602 regulator-coupled-max-spread = <6250>; 603}; 604 605&mt6359_vufs_ldo_reg { 606 regulator-always-on; 607}; 608 609&nor_flash { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&nor_pins>; 612 status = "okay"; 613 614 flash@0 { 615 compatible = "jedec,spi-nor"; 616 reg = <0>; 617 spi-max-frequency = <52000000>; 618 }; 619}; 620 621&ovl0_in { 622 remote-endpoint = <&vdosys0_ep_main>; 623}; 624 625&pcie { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pcie_pins>; 628 status = "okay"; 629}; 630 631&pciephy { 632 status = "okay"; 633}; 634 635&pio { 636 gpio-line-names = 637 "gsc_int", 638 "AP_DISP_BKLTEN", 639 "", 640 "EN_PPVAR_MIPI_DISP", 641 "EN_PPVAR_MIPI_DISP_150MA", 642 "TCHSCR_RST_1V8_L", 643 "TCHSRC_REPORT_DISABLE", 644 "", 645 "", 646 "", 647 "", 648 "I2S_SPKR_DATAOUT", 649 "EN_PP3300_WLAN_X", 650 "WIFI_KILL_1V8_L", 651 "BT_KILL_1V8_L", 652 "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 653 "", 654 "EDP_HPD_1V8", 655 "WCAM_PWDN_L", 656 "WCAM_RST_L", 657 "UCAM_PWDM_L", 658 "UCAM_RST_L", 659 "WCAM_24M_CLK", 660 "UCAM_24M_CLK", 661 "MT6319_INT", 662 "DISP_RST_1V8_L", 663 "DSIO_DSI_TE", 664 "EN_PP3300_EDP_DISP_X", 665 "TP", 666 "MIPI_BL_PWM_1V8", 667 "EDP_BL_PWM_1V8", 668 "UART_AP_TX_GSC_RX", 669 "UART_GSC_TX_AP_RX", 670 "UART_SSPM_TX_DBGCON_RX", 671 "UART_DBGCON_TX_SSPM_RX", 672 "UART_ADSP_TX_DBGCON_RX", 673 "UART_DBGCON_TX_ADSP_RX", 674 "JTAG_AP_TMS", 675 "JTAG_AP_TCK", 676 "JTAG_AP_TDI", 677 "JTAG_AP_TDO", 678 "JTAG_AP_TRST", 679 "AP_KPCOL0", 680 "TP", 681 "BEEP_ON_OD", 682 "TP", 683 "EC_AP_HPD_OD", 684 "PCIE_WAKE_1V8_ODL", 685 "PCIE_RST_1V8_L", 686 "PCIE_CLKREQ_1V8_ODL", 687 "", 688 "", 689 "", 690 "", 691 "", 692 "AP_I2C_AUD_SCL_1V8", 693 "AP_I2C_AUD_SDA_1V8", 694 "AP_I2C_TPM_SCL_1V8", 695 "AP_I2C_TPM_SDA_1V8", 696 "AP_I2C_TCHSCR_SCL_1V8", 697 "AP_I2C_TCHSCR_SDA_1V8", 698 "AP_I2C_PMIC_SAR_SCL_1V8", 699 "AP_I2C_PMIC_SAR_SDA_1V8", 700 "AP_I2C_EC_HID_KB_SCL_1V8", 701 "AP_I2C_EC_HID_KB_SDA_1V8", 702 "AP_I2C_UCAM_SCL_1V8", 703 "AP_I2C_UCAM_SDA_1V8", 704 "AP_I2C_WCAM_SCL_1V8", 705 "AP_I2C_WCAM_SDA_1V8", 706 "SPI_AP_CS_EC_L", 707 "SPI_AP_CLK_EC", 708 "SPI_AP_DO_EC_DI", 709 "SPI_AP_DI_EC_DO", 710 "TP", 711 "TP", 712 "SPI_AP_CS_TCHSCR_L", 713 "SPI_AP_CLK_TCHSCR", 714 "SPI_AP_DO_TCHSCR_DI", 715 "SPI_AP_DI_TCHSCR_DO", 716 "TP", 717 "TP", 718 "TP", 719 "TP", 720 "", 721 "", 722 "", 723 "TP", 724 "", 725 "SAR_INT_ODL", 726 "", 727 "", 728 "", 729 "PWRAP_SPI_CS_L", 730 "PWRAP_SPI_CK", 731 "PWRAP_SPI_MOSI", 732 "PWRAP_SPI_MISO", 733 "SRCLKENA0", 734 "SRCLKENA1", 735 "SCP_VREQ_VAO", 736 "AP_RTC_CLK32K", 737 "AP_PMIC_WDTRST_L", 738 "AUD_CLK_MOSI", 739 "AUD_SYNC_MOSI", 740 "AUD_DAT_MOSI0", 741 "AUD_DAT_MOSI1", 742 "AUD_DAT_MISO0", 743 "AUD_DAT_MISO1", 744 "SD_CD_ODL", 745 "HP_INT_ODL", 746 "SPKR_INT_ODL", 747 "I2S_HP_DATAIN", 748 "EN_SPKR", 749 "I2S_SPKR_MCLK", 750 "I2S_SPKR_BCLK", 751 "I2S_HP_MCLK", 752 "I2S_HP_BCLK", 753 "I2S_HP_LRCK", 754 "I2S_HP_DATAOUT", 755 "RST_SPKR_L", 756 "I2S_SPKR_LRCK", 757 "I2S_SPKR_DATAIN", 758 "", 759 "", 760 "", 761 "", 762 "SPI_AP_CLK_ROM", 763 "SPI_AP_CS_ROM_L", 764 "SPI_AP_DO_ROM_DI", 765 "SPI_AP_DI_ROM_DO", 766 "TP", 767 "TP", 768 "", 769 "", 770 "", 771 "", 772 "", 773 "", 774 "", 775 "", 776 "EN_PP2800A_UCAM_X", 777 "EN_PP1200_UCAM_X", 778 "EN_PP2800A_WCAM_X", 779 "EN_PP1100_WCAM_X", 780 "TCHSCR_INT_1V8_L", 781 "EN_PP3300_MIPI_TCHSCR_X", 782 "MT7921_PMU_EN_1V8", 783 "EN_PP3300_EDP_TCHSCR_X", 784 "AP_EC_WARM_RST_REQ", 785 "EC_AP_HID_INT_ODL", 786 "EC_AP_INT_ODL", 787 "AP_XHCI_INIT_DONE", 788 "EMMC_DAT7", 789 "EMMC_DAT6", 790 "EMMC_DAT5", 791 "EMMC_DAT4", 792 "EMMC_RST_L", 793 "EMMC_CMD", 794 "EMMC_CLK", 795 "EMMC_DAT3", 796 "EMMC_DAT2", 797 "EMMC_DAT1", 798 "EMMC_DAT0", 799 "EMMC_DSL", 800 "SD_CMD", 801 "SD_CLK", 802 "SD_DAT0", 803 "SD_DAT1", 804 "SD_DAT2", 805 "SD_DAT3", 806 "", 807 "", 808 "USB3_HUB_RST_L", 809 "EC_AP_RSVD0_ODL", 810 "", 811 "", 812 "SPMI_SCL", 813 "SPMI_SDA"; 814 815 adsp_uart_pins: adsp-uart-pins { 816 pins-bus { 817 pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, 818 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>; 819 }; 820 }; 821 822 aud_etdm_hp_on: aud-etdm-hp-on-pins { 823 pins-bus { 824 pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>, 825 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>, 826 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>, 827 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>; 828 }; 829 }; 830 831 aud_etdm_hp_off: aud-etdm-hp-off-pins { 832 pins-bus { 833 pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>, 834 <PINMUX_GPIO115__FUNC_B_GPIO115>, 835 <PINMUX_GPIO116__FUNC_B_GPIO116>, 836 <PINMUX_GPIO117__FUNC_B_GPIO117>; 837 bias-pull-down; 838 input-enable; 839 }; 840 }; 841 842 aud_etdm_spk_on: aud-etdm-spk-on-pins { 843 pins-bus { 844 pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>, 845 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>, 846 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>, 847 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>; 848 drive-strength = <8>; 849 }; 850 }; 851 852 aud_etdm_spk_off: aud-etdm-spk-off-pins { 853 pins-bus { 854 pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>, 855 <PINMUX_GPIO113__FUNC_B_GPIO113>, 856 <PINMUX_GPIO119__FUNC_B_GPIO119>, 857 <PINMUX_GPIO120__FUNC_B_GPIO120>; 858 bias-pull-down; 859 input-enable; 860 }; 861 }; 862 863 aud_mtkaif_on: aud-mtkaif-on-pins { 864 pins-bus { 865 pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>, 866 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>, 867 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>, 868 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>, 869 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>, 870 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>; 871 }; 872 }; 873 874 aud_mtkaif_off: aud-mtkaif-off-pins { 875 pins-bus { 876 pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>, 877 <PINMUX_GPIO102__FUNC_B_GPIO102>, 878 <PINMUX_GPIO103__FUNC_B_GPIO103>, 879 <PINMUX_GPIO104__FUNC_B_GPIO104>, 880 <PINMUX_GPIO105__FUNC_B_GPIO105>, 881 <PINMUX_GPIO106__FUNC_B_GPIO106>; 882 bias-pull-down; 883 input-enable; 884 }; 885 }; 886 887 cros_ec_int: cros-ec-int-pins { 888 pins-ec-ap-int-odl { 889 pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>; 890 input-enable; 891 }; 892 }; 893 894 disp_pwm0_pins: disp-pwm0-pins { 895 pins-disp-pwm0 { 896 pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>; 897 output-high; 898 }; 899 }; 900 901 disp_pwm1_pins: disp-pwm1-pins { 902 pins-disp-pwm1 { 903 pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>; 904 output-high; 905 }; 906 }; 907 908 dp_tx_hpd: dp-tx-hpd-pins { 909 pins-dp-tx-hpd { 910 pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>; 911 }; 912 }; 913 914 gsc_int: gsc-int-pins { 915 pins-gsc-ap-int-odl { 916 pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>; 917 input-enable; 918 }; 919 }; 920 921 i2c0_pins: i2c0-pins { 922 pins-bus { 923 pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, 924 <PINMUX_GPIO55__FUNC_B1_SCL0>; 925 }; 926 }; 927 928 i2c1_pins: i2c1-pins { 929 pins-bus { 930 pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, 931 <PINMUX_GPIO57__FUNC_B1_SCL1>; 932 }; 933 }; 934 935 i2c2_pins: i2c2-pins { 936 pins-bus { 937 pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, 938 <PINMUX_GPIO59__FUNC_B1_SCL2>; 939 bias-disable; 940 drive-strength = <12>; 941 }; 942 }; 943 944 i2c3_pins: i2c3-pins { 945 pins-bus { 946 pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, 947 <PINMUX_GPIO61__FUNC_B1_SCL3>; 948 }; 949 }; 950 951 i2c4_pins: i2c4-pins { 952 pins-bus { 953 pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, 954 <PINMUX_GPIO63__FUNC_B1_SCL4>; 955 }; 956 }; 957 958 i2c5_pins: i2c5-pins { 959 pins-bus { 960 pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, 961 <PINMUX_GPIO65__FUNC_B1_SCL5>; 962 }; 963 }; 964 965 i2c6_pins: i2c6-pins { 966 pins-bus { 967 pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, 968 <PINMUX_GPIO67__FUNC_B1_SCL6>; 969 }; 970 }; 971 972 mipi_disp_avdd_en: mipi-disp-avdd-en-pins { 973 pins-en-ppvar-mipi-disp { 974 pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>; 975 output-low; 976 }; 977 }; 978 979 mipi_disp_avee_en: mipi-disp-avee-en-pins { 980 pins-en-ppvar-mipi-disp-150ma { 981 pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>; 982 output-low; 983 }; 984 }; 985 986 mipi_dsi_pins: mipi-dsi-pins { 987 pins-bus { 988 pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>, 989 <PINMUX_GPIO25__FUNC_B_GPIO25>; 990 output-low; 991 }; 992 }; 993 994 mmc0_pins_default: mmc0-default-pins { 995 pins-bus { 996 pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 997 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 998 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 999 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 1000 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 1001 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 1002 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 1003 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 1004 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 1005 input-enable; 1006 drive-strength = <6>; 1007 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1008 }; 1009 1010 pins-clk { 1011 pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 1012 drive-strength = <6>; 1013 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1014 }; 1015 1016 pins-rst { 1017 pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 1018 drive-strength = <6>; 1019 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1020 }; 1021 }; 1022 1023 mmc0_pins_uhs: mmc0-uhs-pins { 1024 pins-bus { 1025 pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, 1026 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, 1027 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, 1028 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, 1029 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, 1030 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, 1031 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, 1032 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, 1033 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; 1034 input-enable; 1035 drive-strength = <8>; 1036 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1037 }; 1038 1039 pins-clk { 1040 pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; 1041 drive-strength = <8>; 1042 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1043 }; 1044 1045 pins-ds { 1046 pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; 1047 drive-strength = <8>; 1048 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1049 }; 1050 1051 pins-rst { 1052 pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; 1053 drive-strength = <8>; 1054 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1055 }; 1056 }; 1057 1058 nor_pins: nor-default-pins { 1059 pins-clk { 1060 pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>, 1061 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>, 1062 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>; 1063 bias-pull-down; 1064 }; 1065 1066 pins-cs { 1067 pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>; 1068 bias-pull-up; 1069 }; 1070 }; 1071 1072 pcie_pins: pcie-default-pins { 1073 pins-bus { 1074 pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, 1075 <PINMUX_GPIO48__FUNC_O_PERSTN>, 1076 <PINMUX_GPIO49__FUNC_B1_CLKREQN>; 1077 }; 1078 }; 1079 1080 spi0_pins: spi0-pins { 1081 pins-bus { 1082 pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, 1083 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, 1084 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, 1085 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; 1086 bias-disable; 1087 }; 1088 }; 1089 1090 spi1_pins_default: spi1-default-pins { 1091 pins-bus { 1092 pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, 1093 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, 1094 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, 1095 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; 1096 bias-disable; 1097 }; 1098 }; 1099 1100 spi1_pins_sleep: spi1-sleep-pins { 1101 pins-bus { 1102 pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>, 1103 <PINMUX_GPIO76__FUNC_B_GPIO76>, 1104 <PINMUX_GPIO77__FUNC_B_GPIO77>, 1105 <PINMUX_GPIO78__FUNC_B_GPIO78>; 1106 bias-pull-down; 1107 input-enable; 1108 }; 1109 }; 1110 1111 spi2_pins: spi2-pins { 1112 pins-bus { 1113 pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, 1114 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, 1115 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, 1116 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; 1117 bias-disable; 1118 }; 1119 }; 1120 1121 uart0_pins: uart0-pins { 1122 pins-bus { 1123 pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, 1124 <PINMUX_GPIO32__FUNC_I1_URXD0>; 1125 bias-pull-up; 1126 }; 1127 }; 1128 1129 wlan_en: wlan-en-pins { 1130 pins-en-pp3300-wlan { 1131 pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; 1132 output-low; 1133 }; 1134 }; 1135}; 1136 1137&pmic { 1138 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1139}; 1140 1141&postmask0_in { 1142 remote-endpoint = <&gamma0_out>; 1143}; 1144 1145&postmask0_out { 1146 remote-endpoint = <&dither0_in>; 1147}; 1148 1149&sound { 1150 pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", 1151 "aud_etdm_spk_on", "aud_etdm_spk_off", 1152 "aud_mtkaif_on", "aud_mtkaif_off"; 1153 pinctrl-0 = <&aud_etdm_hp_on>; 1154 pinctrl-1 = <&aud_etdm_hp_off>; 1155 pinctrl-2 = <&aud_etdm_spk_on>; 1156 pinctrl-3 = <&aud_etdm_spk_off>; 1157 pinctrl-4 = <&aud_mtkaif_on>; 1158 pinctrl-5 = <&aud_mtkaif_off>; 1159 mediatek,adsp = <&adsp>; 1160 /* The audio-routing is defined in each board dts */ 1161 1162 status = "okay"; 1163}; 1164 1165&spi0 { 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&spi0_pins>; 1168 status = "okay"; 1169 1170 cros_ec: ec@0 { 1171 compatible = "google,cros-ec-spi"; 1172 reg = <0>; 1173 interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&cros_ec_int>; 1176 spi-max-frequency = <3000000>; 1177 1178 i2c_tunnel: i2c-tunnel { 1179 compatible = "google,cros-ec-i2c-tunnel"; 1180 google,remote-bus = <1>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 }; 1184 1185 cbas { 1186 compatible = "google,cros-cbas"; 1187 }; 1188 }; 1189}; 1190 1191&spi1 { 1192 pinctrl-names = "default", "sleep"; 1193 pinctrl-0 = <&spi1_pins_default>; 1194 pinctrl-1 = <&spi1_pins_sleep>; 1195 status = "okay"; 1196}; 1197 1198&spi2 { 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&spi2_pins>; 1201 status = "okay"; 1202}; 1203 1204&uart0 { 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&uart0_pins>; 1207 status = "okay"; 1208}; 1209 1210&u3phy0 { 1211 status = "okay"; 1212}; 1213 1214&u3phy1 { 1215 status = "okay"; 1216}; 1217 1218&u3phy2 { 1219 status = "okay"; 1220}; 1221 1222/* USB detachable base */ 1223&ssusb0 { 1224 dr_mode = "host"; 1225 vusb33-supply = <&pp3300_s3>; 1226 status = "okay"; 1227}; 1228 1229&xhci0 { 1230 /* controlled by EC */ 1231 vbus-supply = <&pp3300_z1>; 1232 status = "okay"; 1233}; 1234 1235/* USB3 hub */ 1236&ssusb1 { 1237 dr_mode = "host"; 1238 vusb33-supply = <&pp3300_s3>; 1239 status = "okay"; 1240}; 1241 1242&xhci1 { 1243 vusb33-supply = <&pp3300_s3>; 1244 vbus-supply = <&pp5000_usb_vbus>; 1245 status = "okay"; 1246}; 1247 1248/* USB BT */ 1249&ssusb2 { 1250 dr_mode = "host"; 1251 vusb33-supply = <&pp3300_s3>; 1252 status = "okay"; 1253}; 1254 1255&vdosys0 { 1256 port { 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 1260 vdosys0_ep_main: endpoint@0 { 1261 reg = <0>; 1262 remote-endpoint = <&ovl0_in>; 1263 }; 1264 }; 1265}; 1266 1267&vdosys1 { 1268 port { 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 1272 vdosys1_ep_ext: endpoint@1 { 1273 reg = <1>; 1274 remote-endpoint = <ðdr0_in>; 1275 }; 1276 }; 1277}; 1278 1279&xhci2 { 1280 /* no power supply since MT7921's power is controlled by PCIe */ 1281 /* MT7921's USB BT has issues with USB2 LPM */ 1282 usb2-lpm-disable; 1283 status = "okay"; 1284}; 1285 1286#include <arm/cros-ec-keyboard.dtsi> 1287 1288&keyboard_controller { 1289 function-row-physmap = < 1290 MATRIX_KEY(0x00, 0x02, 0) /* T1 */ 1291 MATRIX_KEY(0x03, 0x02, 0) /* T2 */ 1292 MATRIX_KEY(0x02, 0x02, 0) /* T3 */ 1293 MATRIX_KEY(0x01, 0x02, 0) /* T4 */ 1294 MATRIX_KEY(0x03, 0x04, 0) /* T5 */ 1295 MATRIX_KEY(0x02, 0x04, 0) /* T6 */ 1296 MATRIX_KEY(0x01, 0x04, 0) /* T7 */ 1297 MATRIX_KEY(0x02, 0x09, 0) /* T8 */ 1298 MATRIX_KEY(0x01, 0x09, 0) /* T9 */ 1299 MATRIX_KEY(0x00, 0x04, 0) /* T10 */ 1300 >; 1301 1302 linux,keymap = < 1303 MATRIX_KEY(0x00, 0x02, KEY_BACK) 1304 MATRIX_KEY(0x03, 0x02, KEY_REFRESH) 1305 MATRIX_KEY(0x02, 0x02, KEY_ZOOM) 1306 MATRIX_KEY(0x01, 0x02, KEY_SCALE) 1307 MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) 1308 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) 1309 MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) 1310 MATRIX_KEY(0x02, 0x09, KEY_MUTE) 1311 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) 1312 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) 1313 CROS_STD_MAIN_KEYMAP 1314 >; 1315}; 1316