1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <®_vsys>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 gpio = <&pio 178 0>; 51 enable-active-high; 52 vin-supply = <&pp1800_alw>; 53 }; 54 55 pp1800_alw: regulator5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "pp1800_alw"; 58 regulator-always-on; 59 regulator-boot-on; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 vin-supply = <®_vsys>; 63 }; 64 65 pp3300_alw: regulator6 { 66 compatible = "regulator-fixed"; 67 regulator-name = "pp3300_alw"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <®_vsys>; 73 }; 74 75 /* system wide semi-regulated power rail from charger */ 76 reg_vsys: regulator-vsys { 77 compatible = "regulator-fixed"; 78 regulator-name = "vsys"; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 reserved_memory: reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 scp_mem_reserved: memory@50000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0 0x50000000 0 0x2900000>; 91 no-map; 92 }; 93 }; 94 95 sound: mt8183-sound { 96 mediatek,platform = <&afe>; 97 pinctrl-names = "default", 98 "aud_tdm_out_on", 99 "aud_tdm_out_off"; 100 pinctrl-0 = <&aud_pins_default>; 101 pinctrl-1 = <&aud_pins_tdm_out_on>; 102 pinctrl-2 = <&aud_pins_tdm_out_off>; 103 status = "okay"; 104 }; 105 106 btsco: bt-sco { 107 compatible = "linux,bt-sco"; 108 #sound-dai-cells = <0>; 109 }; 110 111 wifi_pwrseq: wifi-pwrseq { 112 compatible = "mmc-pwrseq-simple"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&wifi_pins_pwrseq>; 115 116 /* Toggle WIFI_ENABLE to reset the chip. */ 117 reset-gpios = <&pio 119 1>; 118 }; 119 120 wifi_wakeup: wifi-wakeup { 121 compatible = "gpio-keys"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&wifi_pins_wakeup>; 124 125 wifi_wakeup_event: event-wowlan { 126 label = "Wake on WiFi"; 127 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 128 linux,code = <KEY_WAKEUP>; 129 wakeup-source; 130 }; 131 }; 132 133 tboard_thermistor1: thermal-sensor1 { 134 compatible = "generic-adc-thermal"; 135 #thermal-sensor-cells = <0>; 136 io-channels = <&auxadc 0>; 137 io-channel-names = "sensor-channel"; 138 temperature-lookup-table = < (-5000) 1553 139 0 1488 140 5000 1412 141 10000 1326 142 15000 1232 143 20000 1132 144 25000 1029 145 30000 925 146 35000 823 147 40000 726 148 45000 635 149 50000 552 150 55000 478 151 60000 411 152 65000 353 153 70000 303 154 75000 260 155 80000 222 156 85000 190 157 90000 163 158 95000 140 159 100000 121 160 105000 104 161 110000 90 162 115000 78 163 120000 67 164 125000 59>; 165 }; 166 167 tboard_thermistor2: thermal-sensor2 { 168 compatible = "generic-adc-thermal"; 169 #thermal-sensor-cells = <0>; 170 io-channels = <&auxadc 1>; 171 io-channel-names = "sensor-channel"; 172 temperature-lookup-table = < (-5000) 1553 173 0 1488 174 5000 1412 175 10000 1326 176 15000 1232 177 20000 1132 178 25000 1029 179 30000 925 180 35000 823 181 40000 726 182 45000 635 183 50000 552 184 55000 478 185 60000 411 186 65000 353 187 70000 303 188 75000 260 189 80000 222 190 85000 190 191 90000 163 192 95000 140 193 100000 121 194 105000 104 195 110000 90 196 115000 78 197 120000 67 198 125000 59>; 199 }; 200}; 201 202&auxadc { 203 status = "okay"; 204}; 205 206&cci { 207 proc-supply = <&mt6358_vproc12_reg>; 208}; 209 210&cpu0 { 211 proc-supply = <&mt6358_vproc12_reg>; 212}; 213 214&cpu1 { 215 proc-supply = <&mt6358_vproc12_reg>; 216}; 217 218&cpu2 { 219 proc-supply = <&mt6358_vproc12_reg>; 220}; 221 222&cpu3 { 223 proc-supply = <&mt6358_vproc12_reg>; 224}; 225 226&cpu4 { 227 proc-supply = <&mt6358_vproc11_reg>; 228}; 229 230&cpu5 { 231 proc-supply = <&mt6358_vproc11_reg>; 232}; 233 234&cpu6 { 235 proc-supply = <&mt6358_vproc11_reg>; 236}; 237 238&cpu7 { 239 proc-supply = <&mt6358_vproc11_reg>; 240}; 241 242&dsi0 { 243 status = "okay"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 panel: panel@0 { 247 /* compatible will be set in board dts */ 248 reg = <0>; 249 enable-gpios = <&pio 45 0>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&panel_pins_default>; 252 avdd-supply = <&ppvarn_lcd>; 253 avee-supply = <&ppvarp_lcd>; 254 pp1800-supply = <&pp1800_lcd>; 255 backlight = <&backlight_lcd0>; 256 rotation = <270>; 257 port { 258 panel_in: endpoint { 259 remote-endpoint = <&dsi_out>; 260 }; 261 }; 262 }; 263}; 264 265&dsi_out { 266 remote-endpoint = <&panel_in>; 267}; 268 269&gic { 270 mediatek,broken-save-restore-fw; 271}; 272 273&gpu { 274 mali-supply = <&mt6358_vgpu_reg>; 275}; 276 277&i2c0 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&i2c0_pins>; 280 status = "okay"; 281 clock-frequency = <400000>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284}; 285 286&i2c1 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c1_pins>; 289 status = "okay"; 290 clock-frequency = <100000>; 291}; 292 293&i2c3 { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c3_pins>; 296 status = "okay"; 297 clock-frequency = <100000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300}; 301 302&i2c5 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c5_pins>; 305 status = "okay"; 306 clock-frequency = <100000>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309}; 310 311&i2c6 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&i2c6_pins>; 314 status = "okay"; 315 clock-frequency = <100000>; 316}; 317 318&mipi_tx0 { 319 status = "okay"; 320}; 321 322&mmc0 { 323 status = "okay"; 324 pinctrl-names = "default", "state_uhs"; 325 pinctrl-0 = <&mmc0_pins_default>; 326 pinctrl-1 = <&mmc0_pins_uhs>; 327 bus-width = <8>; 328 max-frequency = <200000000>; 329 cap-mmc-highspeed; 330 mmc-hs200-1_8v; 331 mmc-hs400-1_8v; 332 cap-mmc-hw-reset; 333 no-sdio; 334 no-sd; 335 hs400-ds-delay = <0x12814>; 336 vmmc-supply = <&mt6358_vemc_reg>; 337 vqmmc-supply = <&mt6358_vio18_reg>; 338 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 339 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 340 non-removable; 341}; 342 343&mmc1 { 344 status = "okay"; 345 pinctrl-names = "default", "state_uhs"; 346 pinctrl-0 = <&mmc1_pins_default>; 347 pinctrl-1 = <&mmc1_pins_uhs>; 348 vmmc-supply = <&pp3300_alw>; 349 vqmmc-supply = <&pp1800_alw>; 350 mmc-pwrseq = <&wifi_pwrseq>; 351 bus-width = <4>; 352 max-frequency = <200000000>; 353 cap-sd-highspeed; 354 sd-uhs-sdr50; 355 sd-uhs-sdr104; 356 keep-power-in-suspend; 357 wakeup-source; 358 cap-sdio-irq; 359 non-removable; 360 no-mmc; 361 no-sd; 362 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 363 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 qca_wifi: qca-wifi@1 { 368 compatible = "qcom,ath10k"; 369 reg = <1>; 370 }; 371}; 372 373&mt6358_vdram2_reg { 374 regulator-always-on; 375}; 376 377&mt6358codec { 378 Avdd-supply = <&mt6358_vaud28_reg>; 379}; 380 381&mt6358regulator { 382 vsys-ldo1-supply = <®_vsys>; 383 vsys-ldo2-supply = <®_vsys>; 384 vsys-ldo3-supply = <®_vsys>; 385 vsys-vcore-supply = <®_vsys>; 386 vsys-vdram1-supply = <®_vsys>; 387 vsys-vgpu-supply = <®_vsys>; 388 vsys-vmodem-supply = <®_vsys>; 389 vsys-vpa-supply = <®_vsys>; 390 vsys-vproc11-supply = <®_vsys>; 391 vsys-vproc12-supply = <®_vsys>; 392 vsys-vs1-supply = <®_vsys>; 393 vsys-vs2-supply = <®_vsys>; 394 vs1-ldo1-supply = <&mt6358_vs1_reg>; 395 vs2-ldo1-supply = <&mt6358_vdram1_reg>; 396 vs2-ldo2-supply = <&mt6358_vs2_reg>; 397 vs2-ldo3-supply = <&mt6358_vs2_reg>; 398 vs2-ldo4-supply = <&mt6358_vs2_reg>; 399}; 400 401&mt6358_vgpu_reg { 402 regulator-max-microvolt = <900000>; 403 404 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 405 regulator-coupled-max-spread = <100000>; 406}; 407 408&mt6358_vsim1_reg { 409 regulator-min-microvolt = <2700000>; 410 regulator-max-microvolt = <2700000>; 411}; 412 413&mt6358_vsim2_reg { 414 regulator-min-microvolt = <2700000>; 415 regulator-max-microvolt = <2700000>; 416}; 417 418&mt6358_vsram_gpu_reg { 419 regulator-min-microvolt = <850000>; 420 regulator-max-microvolt = <1000000>; 421 422 regulator-coupled-with = <&mt6358_vgpu_reg>; 423 regulator-coupled-max-spread = <100000>; 424}; 425 426&pio { 427 aud_pins_default: audiopins { 428 pins-bus { 429 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 430 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 431 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 432 <PINMUX_GPIO102__FUNC_I2S2_DI>, 433 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 434 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 435 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 436 <PINMUX_GPIO91__FUNC_I2S5_DO>, 437 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 438 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 439 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 440 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 441 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 442 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 443 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 444 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 445 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 446 }; 447 }; 448 449 aud_pins_tdm_out_on: audiotdmouton { 450 pins-bus { 451 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 452 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 453 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 454 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 455 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 456 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 457 drive-strength = <6>; 458 }; 459 }; 460 461 aud_pins_tdm_out_off: audiotdmoutoff { 462 pins-bus { 463 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 464 <PINMUX_GPIO170__FUNC_GPIO170>, 465 <PINMUX_GPIO171__FUNC_GPIO171>, 466 <PINMUX_GPIO172__FUNC_GPIO172>, 467 <PINMUX_GPIO173__FUNC_GPIO173>, 468 <PINMUX_GPIO10__FUNC_GPIO10>; 469 input-enable; 470 bias-pull-down; 471 drive-strength = <2>; 472 }; 473 }; 474 475 bt_pins: bt-pins { 476 pins-bt-en { 477 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 478 output-low; 479 }; 480 }; 481 482 ec_ap_int_odl: ec-ap-int-odl { 483 pins1 { 484 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 485 input-enable; 486 bias-pull-up; 487 }; 488 }; 489 490 h1_int_od_l: h1-int-od-l { 491 pins1 { 492 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 493 input-enable; 494 }; 495 }; 496 497 i2c0_pins: i2c0 { 498 pins-bus { 499 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 500 <PINMUX_GPIO83__FUNC_SCL0>; 501 mediatek,pull-up-adv = <3>; 502 }; 503 }; 504 505 i2c1_pins: i2c1 { 506 pins-bus { 507 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 508 <PINMUX_GPIO84__FUNC_SCL1>; 509 mediatek,pull-up-adv = <3>; 510 }; 511 }; 512 513 i2c2_pins: i2c2 { 514 pins-bus { 515 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 516 <PINMUX_GPIO104__FUNC_SDA2>; 517 bias-disable; 518 }; 519 }; 520 521 i2c3_pins: i2c3 { 522 pins-bus { 523 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 524 <PINMUX_GPIO51__FUNC_SDA3>; 525 mediatek,pull-up-adv = <3>; 526 }; 527 }; 528 529 i2c4_pins: i2c4 { 530 pins-bus { 531 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 532 <PINMUX_GPIO106__FUNC_SDA4>; 533 bias-disable; 534 }; 535 }; 536 537 i2c5_pins: i2c5 { 538 pins-bus { 539 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 540 <PINMUX_GPIO49__FUNC_SDA5>; 541 mediatek,pull-up-adv = <3>; 542 }; 543 }; 544 545 i2c6_pins: i2c6 { 546 pins-bus { 547 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 548 <PINMUX_GPIO12__FUNC_SDA6>; 549 bias-disable; 550 }; 551 }; 552 553 mmc0_pins_default: mmc0-pins-default { 554 pins-cmd-dat { 555 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 556 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 557 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 558 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 559 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 560 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 561 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 562 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 563 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 564 input-enable; 565 drive-strength = <MTK_DRIVE_14mA>; 566 mediatek,pull-up-adv = <01>; 567 }; 568 569 pins-clk { 570 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 571 drive-strength = <MTK_DRIVE_14mA>; 572 mediatek,pull-down-adv = <10>; 573 }; 574 575 pins-rst { 576 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 577 drive-strength = <MTK_DRIVE_14mA>; 578 mediatek,pull-down-adv = <01>; 579 }; 580 }; 581 582 mmc0_pins_uhs: mmc0-pins-uhs { 583 pins-cmd-dat { 584 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 585 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 586 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 587 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 588 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 589 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 590 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 591 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 592 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 593 input-enable; 594 drive-strength = <MTK_DRIVE_14mA>; 595 mediatek,pull-up-adv = <01>; 596 }; 597 598 pins-clk { 599 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 600 drive-strength = <MTK_DRIVE_14mA>; 601 mediatek,pull-down-adv = <10>; 602 }; 603 604 pins-ds { 605 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 606 drive-strength = <MTK_DRIVE_14mA>; 607 mediatek,pull-down-adv = <10>; 608 }; 609 610 pins-rst { 611 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 612 drive-strength = <MTK_DRIVE_14mA>; 613 mediatek,pull-up-adv = <01>; 614 }; 615 }; 616 617 mmc1_pins_default: mmc1-pins-default { 618 pins-cmd-dat { 619 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 620 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 621 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 622 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 623 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 624 input-enable; 625 mediatek,pull-up-adv = <10>; 626 }; 627 628 pins-clk { 629 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 630 input-enable; 631 mediatek,pull-down-adv = <10>; 632 }; 633 }; 634 635 mmc1_pins_uhs: mmc1-pins-uhs { 636 pins-cmd-dat { 637 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 638 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 639 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 640 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 641 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 642 drive-strength = <6>; 643 input-enable; 644 mediatek,pull-up-adv = <10>; 645 }; 646 647 pins-clk { 648 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 649 drive-strength = <8>; 650 mediatek,pull-down-adv = <10>; 651 input-enable; 652 }; 653 }; 654 655 panel_pins_default: panel-pins-default { 656 panel-reset { 657 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 658 output-low; 659 bias-pull-up; 660 }; 661 }; 662 663 pwm0_pin_default: pwm0-pin-default { 664 pins1 { 665 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 666 output-high; 667 bias-pull-up; 668 }; 669 pins2 { 670 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 671 }; 672 }; 673 674 scp_pins: scp { 675 pins-scp-uart { 676 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 677 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 678 }; 679 }; 680 681 spi0_pins: spi0 { 682 pins-spi { 683 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 684 <PINMUX_GPIO86__FUNC_GPIO86>, 685 <PINMUX_GPIO87__FUNC_SPI0_MO>, 686 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 687 bias-disable; 688 }; 689 }; 690 691 spi1_pins: spi1 { 692 pins-spi { 693 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 694 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 695 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 696 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 697 bias-disable; 698 }; 699 }; 700 701 spi2_pins: spi2 { 702 pins-spi { 703 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 704 <PINMUX_GPIO1__FUNC_SPI2_MO>, 705 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 706 bias-disable; 707 }; 708 pins-spi-mi { 709 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 710 mediatek,pull-down-adv = <00>; 711 }; 712 }; 713 714 spi3_pins: spi3 { 715 pins-spi { 716 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 717 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 718 <PINMUX_GPIO23__FUNC_SPI3_MO>, 719 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 720 bias-disable; 721 }; 722 }; 723 724 spi4_pins: spi4 { 725 pins-spi { 726 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 727 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 728 <PINMUX_GPIO19__FUNC_SPI4_MO>, 729 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 730 bias-disable; 731 }; 732 }; 733 734 spi5_pins: spi5 { 735 pins-spi { 736 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 737 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 738 <PINMUX_GPIO15__FUNC_SPI5_MO>, 739 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 740 bias-disable; 741 }; 742 }; 743 744 uart0_pins_default: uart0-pins-default { 745 pins-rx { 746 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 747 input-enable; 748 bias-pull-up; 749 }; 750 pins-tx { 751 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 752 }; 753 }; 754 755 uart1_pins_default: uart1-pins-default { 756 pins-rx { 757 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 758 input-enable; 759 bias-pull-up; 760 }; 761 pins-tx { 762 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 763 }; 764 pins-rts { 765 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 766 }; 767 pins-cts { 768 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 769 input-enable; 770 }; 771 }; 772 773 uart1_pins_sleep: uart1-pins-sleep { 774 pins-rx { 775 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 776 input-enable; 777 bias-pull-up; 778 }; 779 pins-tx { 780 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 781 }; 782 pins-rts { 783 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 784 }; 785 pins-cts { 786 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 787 input-enable; 788 }; 789 }; 790 791 wifi_pins_pwrseq: wifi-pins-pwrseq { 792 pins-wifi-enable { 793 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 794 output-low; 795 }; 796 }; 797 798 wifi_pins_wakeup: wifi-pins-wakeup { 799 pins-wifi-wakeup { 800 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 801 input-enable; 802 }; 803 }; 804}; 805 806&pmic { 807 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>; 808}; 809 810&pwm0 { 811 status = "okay"; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&pwm0_pin_default>; 814}; 815 816&scp { 817 status = "okay"; 818 819 firmware-name = "mediatek/mt8183/scp.img"; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&scp_pins>; 822 823 cros-ec-rpmsg { 824 compatible = "google,cros-ec-rpmsg"; 825 mediatek,rpmsg-name = "cros-ec-rpmsg"; 826 }; 827}; 828 829&mfg_async { 830 domain-supply = <&mt6358_vsram_gpu_reg>; 831}; 832 833&mfg { 834 domain-supply = <&mt6358_vgpu_reg>; 835}; 836 837&spi0 { 838 pinctrl-names = "default"; 839 pinctrl-0 = <&spi0_pins>; 840 mediatek,pad-select = <0>; 841 status = "okay"; 842 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 843 844 tpm@0 { 845 compatible = "google,cr50"; 846 reg = <0>; 847 spi-max-frequency = <1000000>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&h1_int_od_l>; 850 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>; 851 }; 852}; 853 854&spi1 { 855 pinctrl-names = "default"; 856 pinctrl-0 = <&spi1_pins>; 857 mediatek,pad-select = <0>; 858 status = "okay"; 859 860 w25q64dw: flash@0 { 861 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 862 reg = <0>; 863 spi-max-frequency = <25000000>; 864 }; 865}; 866 867&spi2 { 868 pinctrl-names = "default"; 869 pinctrl-0 = <&spi2_pins>; 870 mediatek,pad-select = <0>; 871 status = "okay"; 872 873 cros_ec: cros-ec@0 { 874 compatible = "google,cros-ec-spi"; 875 reg = <0>; 876 spi-max-frequency = <3000000>; 877 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&ec_ap_int_odl>; 880 wakeup-source; 881 882 i2c_tunnel: i2c-tunnel { 883 compatible = "google,cros-ec-i2c-tunnel"; 884 google,remote-bus = <1>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 }; 888 889 usbc_extcon: extcon0 { 890 compatible = "google,extcon-usbc-cros-ec"; 891 google,usb-port-id = <0>; 892 }; 893 894 typec { 895 compatible = "google,cros-ec-typec"; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 usb_c0: connector@0 { 900 compatible = "usb-c-connector"; 901 reg = <0>; 902 power-role = "dual"; 903 data-role = "host"; 904 try-power-role = "sink"; 905 }; 906 }; 907 }; 908}; 909 910&spi3 { 911 pinctrl-names = "default"; 912 pinctrl-0 = <&spi3_pins>; 913 mediatek,pad-select = <0>; 914 status = "disabled"; 915}; 916 917&spi4 { 918 pinctrl-names = "default"; 919 pinctrl-0 = <&spi4_pins>; 920 mediatek,pad-select = <0>; 921 status = "disabled"; 922}; 923 924&spi5 { 925 pinctrl-names = "default"; 926 pinctrl-0 = <&spi5_pins>; 927 mediatek,pad-select = <0>; 928 status = "disabled"; 929}; 930 931&ssusb { 932 dr_mode = "host"; 933 wakeup-source; 934 vusb33-supply = <&mt6358_vusb_reg>; 935 status = "okay"; 936}; 937 938&thermal_zones { 939 tboard1-thermal { 940 polling-delay = <1000>; /* milliseconds */ 941 polling-delay-passive = <0>; /* milliseconds */ 942 thermal-sensors = <&tboard_thermistor1>; 943 }; 944 945 tboard2-thermal { 946 polling-delay = <1000>; /* milliseconds */ 947 polling-delay-passive = <0>; /* milliseconds */ 948 thermal-sensors = <&tboard_thermistor2>; 949 }; 950}; 951 952&u3phy { 953 status = "okay"; 954}; 955 956&uart0 { 957 pinctrl-names = "default"; 958 pinctrl-0 = <&uart0_pins_default>; 959 status = "okay"; 960}; 961 962&uart1 { 963 pinctrl-names = "default", "sleep"; 964 pinctrl-0 = <&uart1_pins_default>; 965 pinctrl-1 = <&uart1_pins_sleep>; 966 status = "okay"; 967 /delete-property/ interrupts; 968 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 969 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 970 971 bluetooth: bluetooth { 972 pinctrl-names = "default"; 973 pinctrl-0 = <&bt_pins>; 974 status = "okay"; 975 compatible = "qcom,qca6174-bt"; 976 enable-gpios = <&pio 120 0>; 977 clocks = <&clk32k>; 978 firmware-name = "nvm_00440302_i2s.bin"; 979 }; 980}; 981 982&usb_host { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 vusb33-supply = <&mt6358_vusb_reg>; 986 status = "okay"; 987 988 hub@1 { 989 compatible = "usb5e3,610"; 990 reg = <1>; 991 }; 992}; 993 994#include <arm/cros-ec-sbs.dtsi> 995