xref: /linux/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts (revision 4f9786035f9e519db41375818e1d0b5f20da2f10)
1a6120833SBaruch Siach// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2a6120833SBaruch Siach/*
3a6120833SBaruch Siach * Copyright (C) 2018 SolidRun ltd.
4a6120833SBaruch Siach * Based on Marvell MACCHIATOBin board
5a6120833SBaruch Siach *
6a6120833SBaruch Siach * Device Tree file for SolidRun's ClearFog GT 8K
7a6120833SBaruch Siach */
8a6120833SBaruch Siach
9a6120833SBaruch Siach#include "armada-8040.dtsi"
10a6120833SBaruch Siach
11a6120833SBaruch Siach#include <dt-bindings/input/input.h>
12a6120833SBaruch Siach#include <dt-bindings/gpio/gpio.h>
13a6120833SBaruch Siach
14a6120833SBaruch Siach/ {
15a6120833SBaruch Siach	model = "SolidRun ClearFog GT 8K";
16a6120833SBaruch Siach	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17a6120833SBaruch Siach			"marvell,armada-ap806-quad", "marvell,armada-ap806";
18a6120833SBaruch Siach
19a6120833SBaruch Siach	chosen {
20a6120833SBaruch Siach		stdout-path = "serial0:115200n8";
21a6120833SBaruch Siach	};
22a6120833SBaruch Siach
239e62ec0eSRob Herring	memory@0 {
24a6120833SBaruch Siach		device_type = "memory";
25a6120833SBaruch Siach		reg = <0x0 0x0 0x0 0x80000000>;
26a6120833SBaruch Siach	};
27a6120833SBaruch Siach
28a6120833SBaruch Siach	aliases {
29a6120833SBaruch Siach		ethernet0 = &cp1_eth1;
30a6120833SBaruch Siach		ethernet1 = &cp0_eth0;
31a6120833SBaruch Siach		ethernet2 = &cp1_eth2;
32a6120833SBaruch Siach	};
33a6120833SBaruch Siach
349c7d1f4bSRussell King	fan: pwm {
352d36399cSRussell King		compatible = "pwm-fan";
369c7d1f4bSRussell King		/* 20% steps */
379c7d1f4bSRussell King		cooling-levels = <0 51 102 153 204 255>;
389c7d1f4bSRussell King		#cooling-cells = <2>;
392d36399cSRussell King		pinctrl-names = "default";
402d36399cSRussell King		pinctrl-0 = <&cp0_fan_pwm_pins>;
412d36399cSRussell King		pwms = <&cp0_gpio2 16 40000>;
422d36399cSRussell King	};
432d36399cSRussell King
44a6120833SBaruch Siach	v_3_3: regulator-3-3v {
45a6120833SBaruch Siach		compatible = "regulator-fixed";
46a6120833SBaruch Siach		regulator-name = "v_3_3";
47a6120833SBaruch Siach		regulator-min-microvolt = <3300000>;
48a6120833SBaruch Siach		regulator-max-microvolt = <3300000>;
49a6120833SBaruch Siach		regulator-always-on;
50a6120833SBaruch Siach		status = "okay";
51a6120833SBaruch Siach	};
52a6120833SBaruch Siach
53a6120833SBaruch Siach	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
54a6120833SBaruch Siach		compatible = "regulator-fixed";
55b597a6f5SBaruch Siach		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
56a6120833SBaruch Siach		pinctrl-names = "default";
57a6120833SBaruch Siach		pinctrl-0 = <&cp0_xhci_vbus_pins>;
58a6120833SBaruch Siach		regulator-name = "v_5v0_usb3_hst_vbus";
59a6120833SBaruch Siach		regulator-min-microvolt = <5000000>;
60a6120833SBaruch Siach		regulator-max-microvolt = <5000000>;
61a6120833SBaruch Siach		status = "okay";
62a6120833SBaruch Siach	};
63a6120833SBaruch Siach
64a6120833SBaruch Siach	sfp_cp0_eth0: sfp-cp0-eth0 {
65a6120833SBaruch Siach		compatible = "sff,sfp";
66a6120833SBaruch Siach		i2c-bus = <&cp0_i2c1>;
674ce223e5SIoana Ciornei		mod-def0-gpios = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
684ce223e5SIoana Ciornei		tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
69a6120833SBaruch Siach		pinctrl-names = "default";
70a6120833SBaruch Siach		pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
71188ea2fcSBaruch Siach		maximum-power-milliwatt = <2000>;
72a6120833SBaruch Siach	};
73a6120833SBaruch Siach
74a6120833SBaruch Siach	leds {
75a6120833SBaruch Siach		compatible = "gpio-leds";
76a6120833SBaruch Siach		pinctrl-0 = <&cp0_led0_pins
77a6120833SBaruch Siach			     &cp0_led1_pins>;
78a6120833SBaruch Siach		pinctrl-names = "default";
79a6120833SBaruch Siach		/* No designated function for these LEDs at the moment */
80a6120833SBaruch Siach		led0 {
81a6120833SBaruch Siach			label = "clearfog-gt-8k:green:led0";
82a6120833SBaruch Siach			gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
83a6120833SBaruch Siach			default-state = "on";
84a6120833SBaruch Siach		};
85a6120833SBaruch Siach		led1 {
86a6120833SBaruch Siach			label = "clearfog-gt-8k:green:led1";
87a6120833SBaruch Siach			gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
88a6120833SBaruch Siach			default-state = "on";
89a6120833SBaruch Siach		};
90a6120833SBaruch Siach	};
91a6120833SBaruch Siach
92a6120833SBaruch Siach	keys {
93a6120833SBaruch Siach		compatible = "gpio-keys";
94a6120833SBaruch Siach		pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
95a6120833SBaruch Siach		pinctrl-names = "default";
96a6120833SBaruch Siach
97ebb8ba54SKrzysztof Kozlowski		button-0 {
98a6120833SBaruch Siach			/* The rear button */
99a6120833SBaruch Siach			label = "Rear Button";
100a6120833SBaruch Siach			gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
101a6120833SBaruch Siach			linux,can-disable;
102a6120833SBaruch Siach			linux,code = <BTN_0>;
103a6120833SBaruch Siach		};
104a6120833SBaruch Siach
105ebb8ba54SKrzysztof Kozlowski		button-1 {
106a6120833SBaruch Siach			/* The wps button */
107a6120833SBaruch Siach			label = "WPS Button";
108a6120833SBaruch Siach			gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
109a6120833SBaruch Siach			linux,can-disable;
110a6120833SBaruch Siach			linux,code = <KEY_WPS_BUTTON>;
111a6120833SBaruch Siach		};
112a6120833SBaruch Siach	};
113a6120833SBaruch Siach};
114a6120833SBaruch Siach
1159c7d1f4bSRussell King&ap_thermal_ic {
1169c7d1f4bSRussell King	polling-delay = <1000>; /* milliseconds */
1179c7d1f4bSRussell King	trips {
1189c7d1f4bSRussell King		ap_active: trip-active {
1199c7d1f4bSRussell King			temperature = <40000>; /* millicelsius */
1209c7d1f4bSRussell King			hysteresis = <4000>; /* millicelsius */
1219c7d1f4bSRussell King			type = "active";
1229c7d1f4bSRussell King		};
1239c7d1f4bSRussell King	};
1249c7d1f4bSRussell King	cooling-maps {
1259c7d1f4bSRussell King		map0 {
1269c7d1f4bSRussell King			trip = <&ap_active>;
1279c7d1f4bSRussell King			cooling-device = <&fan THERMAL_NO_LIMIT 4>;
1289c7d1f4bSRussell King		};
1299c7d1f4bSRussell King		map1 {
1309c7d1f4bSRussell King			trip = <&ap_crit>;
1319c7d1f4bSRussell King			cooling-device = <&fan 4 5>;
1329c7d1f4bSRussell King		};
1339c7d1f4bSRussell King	};
1349c7d1f4bSRussell King};
1359c7d1f4bSRussell King
1369c7d1f4bSRussell King&cp0_thermal_ic {
1379c7d1f4bSRussell King	polling-delay = <1000>; /* milliseconds */
1389c7d1f4bSRussell King	trips {
1399c7d1f4bSRussell King		cp0_active0: trip-active0 {
1409c7d1f4bSRussell King			temperature = <40000>; /* millicelsius */
1419c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1429c7d1f4bSRussell King			type = "active";
1439c7d1f4bSRussell King		};
1449c7d1f4bSRussell King		cp0_active1: trip-active1 {
1459c7d1f4bSRussell King			temperature = <45000>; /* millicelsius */
1469c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1479c7d1f4bSRussell King			type = "active";
1489c7d1f4bSRussell King		};
1499c7d1f4bSRussell King		cp0_active2: trip-active2 {
1509c7d1f4bSRussell King			temperature = <50000>; /* millicelsius */
1519c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1529c7d1f4bSRussell King			type = "active";
1539c7d1f4bSRussell King		};
1549c7d1f4bSRussell King		cp0_active3: trip-active3 {
1559c7d1f4bSRussell King			temperature = <60000>; /* millicelsius */
1569c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1579c7d1f4bSRussell King			type = "active";
1589c7d1f4bSRussell King		};
1599c7d1f4bSRussell King	};
1609c7d1f4bSRussell King	cooling-maps {
1619c7d1f4bSRussell King		map0 {
1629c7d1f4bSRussell King			trip = <&cp0_active0>;
1639c7d1f4bSRussell King			cooling-device = <&fan 0 1>;
1649c7d1f4bSRussell King		};
1659c7d1f4bSRussell King		map1 {
1669c7d1f4bSRussell King			trip = <&cp0_active1>;
1679c7d1f4bSRussell King			cooling-device = <&fan 1 2>;
1689c7d1f4bSRussell King		};
1699c7d1f4bSRussell King		map2 {
1709c7d1f4bSRussell King			trip = <&cp0_active2>;
1719c7d1f4bSRussell King			cooling-device = <&fan 2 3>;
1729c7d1f4bSRussell King		};
1739c7d1f4bSRussell King		map3 {
1749c7d1f4bSRussell King			trip = <&cp0_active3>;
1759c7d1f4bSRussell King			cooling-device = <&fan 3 4>;
1769c7d1f4bSRussell King		};
1779c7d1f4bSRussell King		map4 {
1789c7d1f4bSRussell King			trip = <&cp0_crit>;
1799c7d1f4bSRussell King			cooling-device = <&fan 4 5>;
1809c7d1f4bSRussell King		};
1819c7d1f4bSRussell King	};
1829c7d1f4bSRussell King};
1839c7d1f4bSRussell King
1849c7d1f4bSRussell King&cp1_thermal_ic {
1859c7d1f4bSRussell King	polling-delay = <1000>; /* milliseconds */
1869c7d1f4bSRussell King	trips {
1879c7d1f4bSRussell King		cp1_active0: trip-active0 {
1889c7d1f4bSRussell King			temperature = <40000>; /* millicelsius */
1899c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1909c7d1f4bSRussell King			type = "active";
1919c7d1f4bSRussell King		};
1929c7d1f4bSRussell King		cp1_active1: trip-active1 {
1939c7d1f4bSRussell King			temperature = <45000>; /* millicelsius */
1949c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
1959c7d1f4bSRussell King			type = "active";
1969c7d1f4bSRussell King		};
1979c7d1f4bSRussell King		cp1_active2: trip-active2 {
1989c7d1f4bSRussell King			temperature = <50000>; /* millicelsius */
1999c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
2009c7d1f4bSRussell King			type = "active";
2019c7d1f4bSRussell King		};
2029c7d1f4bSRussell King		cp1_active3: trip-active3 {
2039c7d1f4bSRussell King			temperature = <60000>; /* millicelsius */
2049c7d1f4bSRussell King			hysteresis = <2500>; /* millicelsius */
2059c7d1f4bSRussell King			type = "active";
2069c7d1f4bSRussell King		};
2079c7d1f4bSRussell King	};
2089c7d1f4bSRussell King	cooling-maps {
2099c7d1f4bSRussell King		map0 {
2109c7d1f4bSRussell King			trip = <&cp1_active0>;
2119c7d1f4bSRussell King			cooling-device = <&fan 0 1>;
2129c7d1f4bSRussell King		};
2139c7d1f4bSRussell King		map1 {
2149c7d1f4bSRussell King			trip = <&cp1_active1>;
2159c7d1f4bSRussell King			cooling-device = <&fan 1 2>;
2169c7d1f4bSRussell King		};
2179c7d1f4bSRussell King		map2 {
2189c7d1f4bSRussell King			trip = <&cp1_active2>;
2199c7d1f4bSRussell King			cooling-device = <&fan 2 3>;
2209c7d1f4bSRussell King		};
2219c7d1f4bSRussell King		map3 {
2229c7d1f4bSRussell King			trip = <&cp1_active3>;
2239c7d1f4bSRussell King			cooling-device = <&fan 3 4>;
2249c7d1f4bSRussell King		};
2259c7d1f4bSRussell King		map4 {
2269c7d1f4bSRussell King			trip = <&cp1_crit>;
2279c7d1f4bSRussell King			cooling-device = <&fan 4 5>;
2289c7d1f4bSRussell King		};
2299c7d1f4bSRussell King	};
2309c7d1f4bSRussell King};
2319c7d1f4bSRussell King
232a6120833SBaruch Siach&uart0 {
233a6120833SBaruch Siach	status = "okay";
234a6120833SBaruch Siach	pinctrl-0 = <&uart0_pins>;
235a6120833SBaruch Siach	pinctrl-names = "default";
236a6120833SBaruch Siach};
237a6120833SBaruch Siach
238a6120833SBaruch Siach&ap_sdhci0 {
239a6120833SBaruch Siach	bus-width = <8>;
240a6120833SBaruch Siach	no-1-8-v;
241a6120833SBaruch Siach	no-sd;
242a6120833SBaruch Siach	no-sdio;
243a6120833SBaruch Siach	non-removable;
244a6120833SBaruch Siach	status = "okay";
245a6120833SBaruch Siach	vqmmc-supply = <&v_3_3>;
246a6120833SBaruch Siach};
247a6120833SBaruch Siach
248a6120833SBaruch Siach&cp0_i2c0 {
249a6120833SBaruch Siach	clock-frequency = <100000>;
250a6120833SBaruch Siach	pinctrl-names = "default";
251a6120833SBaruch Siach	pinctrl-0 = <&cp0_i2c0_pins>;
252a6120833SBaruch Siach	status = "okay";
253a6120833SBaruch Siach};
254a6120833SBaruch Siach
255a6120833SBaruch Siach&cp0_i2c1 {
256a6120833SBaruch Siach	clock-frequency = <100000>;
257a6120833SBaruch Siach	pinctrl-names = "default";
258a6120833SBaruch Siach	pinctrl-0 = <&cp0_i2c1_pins>;
259a6120833SBaruch Siach	status = "okay";
260a6120833SBaruch Siach};
261a6120833SBaruch Siach
262a6120833SBaruch Siach&cp0_pinctrl {
263a6120833SBaruch Siach	/*
264a6120833SBaruch Siach	 * MPP Bus:
265a6120833SBaruch Siach	 * [0-31] = 0xff: Keep default CP0_shared_pins:
266a6120833SBaruch Siach	 * [11] CLKOUT_MPP_11 (out)
267a6120833SBaruch Siach	 * [23] LINK_RD_IN_CP2CP (in)
268a6120833SBaruch Siach	 * [25] CLKOUT_MPP_25 (out)
269a6120833SBaruch Siach	 * [29] AVS_FB_IN_CP2CP (in)
270a6120833SBaruch Siach	 * [32, 33, 34] pci0/1/2 reset
271a6120833SBaruch Siach	 * [35-38] CP0 I2C1 and I2C0
272a6120833SBaruch Siach	 * [39] GPIO reset button
273a6120833SBaruch Siach	 * [40,41] LED0 and LED1
274a6120833SBaruch Siach	 * [43] 1512 phy reset
275a6120833SBaruch Siach	 * [47] USB VBUS EN (active low)
276a6120833SBaruch Siach	 * [48] FAN PWM
277a6120833SBaruch Siach	 * [49] SFP+ present signal
278a6120833SBaruch Siach	 * [50] TPM interrupt
279a6120833SBaruch Siach	 * [51] WLAN0 disable
280a6120833SBaruch Siach	 * [52] WLAN1 disable
281a6120833SBaruch Siach	 * [53] LTE disable
282a6120833SBaruch Siach	 * [54] NFC reset
283a6120833SBaruch Siach	 * [55] Micro SD card detect
284a6120833SBaruch Siach	 * [56-61] Micro SD
285a6120833SBaruch Siach	 */
286a6120833SBaruch Siach
287a6120833SBaruch Siach	cp0_pci0_reset_pins: pci0-reset-pins {
288a6120833SBaruch Siach		marvell,pins = "mpp32";
289a6120833SBaruch Siach		marvell,function = "gpio";
290a6120833SBaruch Siach	};
291a6120833SBaruch Siach
292a6120833SBaruch Siach	cp0_pci1_reset_pins: pci1-reset-pins {
293a6120833SBaruch Siach		marvell,pins = "mpp33";
294a6120833SBaruch Siach		marvell,function = "gpio";
295a6120833SBaruch Siach	};
296a6120833SBaruch Siach
297a6120833SBaruch Siach	cp0_pci2_reset_pins: pci2-reset-pins {
298a6120833SBaruch Siach		marvell,pins = "mpp34";
299a6120833SBaruch Siach		marvell,function = "gpio";
300a6120833SBaruch Siach	};
301a6120833SBaruch Siach
302a6120833SBaruch Siach	cp0_i2c1_pins: i2c1-pins {
303a6120833SBaruch Siach		marvell,pins = "mpp35", "mpp36";
304a6120833SBaruch Siach		marvell,function = "i2c1";
305a6120833SBaruch Siach	};
306a6120833SBaruch Siach
307a6120833SBaruch Siach	cp0_i2c0_pins: i2c0-pins {
308a6120833SBaruch Siach		marvell,pins = "mpp37", "mpp38";
309a6120833SBaruch Siach		marvell,function = "i2c0";
310a6120833SBaruch Siach	};
311a6120833SBaruch Siach
312a6120833SBaruch Siach	cp0_gpio_reset_pins: gpio-reset-pins {
313a6120833SBaruch Siach		marvell,pins = "mpp39";
314a6120833SBaruch Siach		marvell,function = "gpio";
315a6120833SBaruch Siach	};
316a6120833SBaruch Siach
317a6120833SBaruch Siach	cp0_led0_pins: led0-pins {
318a6120833SBaruch Siach		marvell,pins = "mpp40";
319a6120833SBaruch Siach		marvell,function = "gpio";
320a6120833SBaruch Siach	};
321a6120833SBaruch Siach
322a6120833SBaruch Siach	cp0_led1_pins: led1-pins {
323a6120833SBaruch Siach		marvell,pins = "mpp41";
324a6120833SBaruch Siach		marvell,function = "gpio";
325a6120833SBaruch Siach	};
326a6120833SBaruch Siach
327a6120833SBaruch Siach	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
328a6120833SBaruch Siach		marvell,pins = "mpp43";
329a6120833SBaruch Siach		marvell,function = "gpio";
330a6120833SBaruch Siach	};
331a6120833SBaruch Siach
332a6120833SBaruch Siach	cp0_xhci_vbus_pins: xhci0-vbus-pins {
333a6120833SBaruch Siach		marvell,pins = "mpp47";
334a6120833SBaruch Siach		marvell,function = "gpio";
335a6120833SBaruch Siach	};
336a6120833SBaruch Siach
337a6120833SBaruch Siach	cp0_fan_pwm_pins: fan-pwm-pins {
338a6120833SBaruch Siach		marvell,pins = "mpp48";
339a6120833SBaruch Siach		marvell,function = "gpio";
340a6120833SBaruch Siach	};
341a6120833SBaruch Siach
342a6120833SBaruch Siach	cp0_sfp_present_pins: sfp-present-pins {
343a6120833SBaruch Siach		marvell,pins = "mpp49";
344a6120833SBaruch Siach		marvell,function = "gpio";
345a6120833SBaruch Siach	};
346a6120833SBaruch Siach
347a6120833SBaruch Siach	cp0_tpm_irq_pins: tpm-irq-pins {
348a6120833SBaruch Siach		marvell,pins = "mpp50";
349a6120833SBaruch Siach		marvell,function = "gpio";
350a6120833SBaruch Siach	};
351a6120833SBaruch Siach
352e97bb6d4SThomas Schreiber	cp0_wlan_disable_pins: wlan-disable-pins {
353e97bb6d4SThomas Schreiber		marvell,pins = "mpp51";
354e97bb6d4SThomas Schreiber		marvell,function = "gpio";
355e97bb6d4SThomas Schreiber	};
356e97bb6d4SThomas Schreiber
357a6120833SBaruch Siach	cp0_sdhci_pins: sdhci-pins {
358a6120833SBaruch Siach		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
359a6120833SBaruch Siach			       "mpp60", "mpp61";
360a6120833SBaruch Siach		marvell,function = "sdio";
361a6120833SBaruch Siach	};
362a6120833SBaruch Siach};
363a6120833SBaruch Siach
36491f84690SBaruch Siach&cp0_pcie0 {
36591f84690SBaruch Siach	pinctrl-names = "default";
366e97bb6d4SThomas Schreiber	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
36791f84690SBaruch Siach	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
368ce55522cSMiquel Raynal	phys = <&cp0_comphy0 0>;
369ce55522cSMiquel Raynal	phy-names = "cp0-pcie0-x1-phy";
37091f84690SBaruch Siach	status = "okay";
37191f84690SBaruch Siach};
37291f84690SBaruch Siach
373a6120833SBaruch Siach&cp0_gpio2 {
374*9e7531c4SKrzysztof Kozlowski	sata-reset-hog {
375a6120833SBaruch Siach		gpio-hog;
376a6120833SBaruch Siach		gpios = <1 GPIO_ACTIVE_HIGH>;
377a6120833SBaruch Siach		output-high;
378a6120833SBaruch Siach	};
379235df2d8SBaruch Siach
380*9e7531c4SKrzysztof Kozlowski	lte-reset-hog {
381235df2d8SBaruch Siach		gpio-hog;
382235df2d8SBaruch Siach		gpios = <2 GPIO_ACTIVE_LOW>;
383235df2d8SBaruch Siach		output-low;
384235df2d8SBaruch Siach	};
385235df2d8SBaruch Siach
386*9e7531c4SKrzysztof Kozlowski	wlan_disable-hog {
387e97bb6d4SThomas Schreiber		gpio-hog;
388e97bb6d4SThomas Schreiber		gpios = <19 GPIO_ACTIVE_LOW>;
389e97bb6d4SThomas Schreiber		output-low;
390e97bb6d4SThomas Schreiber	};
391e97bb6d4SThomas Schreiber
392*9e7531c4SKrzysztof Kozlowski	lte-disable-hog {
393235df2d8SBaruch Siach		gpio-hog;
394235df2d8SBaruch Siach		gpios = <21 GPIO_ACTIVE_LOW>;
395235df2d8SBaruch Siach		output-low;
396235df2d8SBaruch Siach	};
397a6120833SBaruch Siach};
398a6120833SBaruch Siach
399a6120833SBaruch Siach&cp0_ethernet {
400a6120833SBaruch Siach	status = "okay";
401a6120833SBaruch Siach};
402a6120833SBaruch Siach
403a6120833SBaruch Siach/* SFP */
404a6120833SBaruch Siach&cp0_eth0 {
405a6120833SBaruch Siach	status = "okay";
406847c3323SRussell King	phy-mode = "10gbase-r";
407a6120833SBaruch Siach	managed = "in-band-status";
408a6120833SBaruch Siach	phys = <&cp0_comphy2 0>;
409a6120833SBaruch Siach	sfp = <&sfp_cp0_eth0>;
410a6120833SBaruch Siach};
411a6120833SBaruch Siach
412a6120833SBaruch Siach&cp0_sdhci0 {
413a6120833SBaruch Siach	broken-cd;
414a6120833SBaruch Siach	bus-width = <4>;
415a6120833SBaruch Siach	pinctrl-names = "default";
416a6120833SBaruch Siach	pinctrl-0 = <&cp0_sdhci_pins>;
417a6120833SBaruch Siach	status = "okay";
418a6120833SBaruch Siach	vqmmc-supply = <&v_3_3>;
419a6120833SBaruch Siach};
420a6120833SBaruch Siach
421dfc1259aSBaruch Siach&cp0_usb3_1 {
422dfc1259aSBaruch Siach	status = "okay";
423dfc1259aSBaruch Siach};
424dfc1259aSBaruch Siach
425a6120833SBaruch Siach&cp1_pinctrl {
426a6120833SBaruch Siach	/*
427a6120833SBaruch Siach	 * MPP Bus:
428a6120833SBaruch Siach	 * [0-5] TDM
429a6120833SBaruch Siach	 * [6]   VHV Enable
430a6120833SBaruch Siach	 * [7]   CP1 SPI0 CSn1 (FXS)
431a6120833SBaruch Siach	 * [8]   CP1 SPI0 CSn0 (TPM)
432a6120833SBaruch Siach	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
433a6120833SBaruch Siach	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
434a6120833SBaruch Siach	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
435a6120833SBaruch Siach	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
436a6120833SBaruch Siach	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
437a6120833SBaruch Siach	 * [24]  Topaz switch reset
438a6120833SBaruch Siach	 * [26]  Buzzer
439a6120833SBaruch Siach	 * [27]  CP1 SMI MDIO
440a6120833SBaruch Siach	 * [28]  CP1 SMI MDC
441a6120833SBaruch Siach	 * [29]  CP0 10G SFP TX Disable
442a6120833SBaruch Siach	 * [30]  WPS button
443a6120833SBaruch Siach	 * [31]  Front panel button
444a6120833SBaruch Siach	 */
445a6120833SBaruch Siach
446a6120833SBaruch Siach	cp1_spi1_pins: spi1-pins {
447a6120833SBaruch Siach		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
448a6120833SBaruch Siach		marvell,function = "spi1";
449a6120833SBaruch Siach	};
450a6120833SBaruch Siach
451a6120833SBaruch Siach	cp1_switch_reset_pins: switch-reset-pins {
452a6120833SBaruch Siach		marvell,pins = "mpp24";
453a6120833SBaruch Siach		marvell,function = "gpio";
454a6120833SBaruch Siach	};
455a6120833SBaruch Siach
456a6120833SBaruch Siach	cp1_ge_mdio_pins: ge-mdio-pins {
457a6120833SBaruch Siach		marvell,pins = "mpp27", "mpp28";
458a6120833SBaruch Siach		marvell,function = "ge";
459a6120833SBaruch Siach	};
460a6120833SBaruch Siach
461a6120833SBaruch Siach	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
462a6120833SBaruch Siach		marvell,pins = "mpp29";
463a6120833SBaruch Siach		marvell,function = "gpio";
464a6120833SBaruch Siach	};
465a6120833SBaruch Siach
466a6120833SBaruch Siach	cp1_wps_button_pins: wps-button-pins {
467a6120833SBaruch Siach		marvell,pins = "mpp30";
468a6120833SBaruch Siach		marvell,function = "gpio";
469a6120833SBaruch Siach	};
470a6120833SBaruch Siach};
471a6120833SBaruch Siach
472a6120833SBaruch Siach&cp1_sata0 {
473a6120833SBaruch Siach	pinctrl-0 = <&cp0_pci1_reset_pins>;
474a6120833SBaruch Siach	status = "okay";
475d04abe99SMiquel Raynal
476d04abe99SMiquel Raynal	sata-port@1 {
477d04abe99SMiquel Raynal		phys = <&cp1_comphy0 1>;
47830023876SFrank Wunderlich		status = "okay";
479d04abe99SMiquel Raynal	};
480a6120833SBaruch Siach};
481a6120833SBaruch Siach
482a6120833SBaruch Siach&cp1_mdio {
483a6120833SBaruch Siach	pinctrl-names = "default";
484a6120833SBaruch Siach	pinctrl-0 = <&cp1_ge_mdio_pins>;
485a6120833SBaruch Siach	status = "okay";
486a6120833SBaruch Siach
487a6120833SBaruch Siach	ge_phy: ethernet-phy@0 {
488a6120833SBaruch Siach		/* LED0 - GB link
489a6120833SBaruch Siach		 * LED1 - on: link, blink: activity
490a6120833SBaruch Siach		 */
491a6120833SBaruch Siach		marvell,reg-init = <3 16 0 0x1017>;
492a6120833SBaruch Siach		reg = <0>;
493babc5544SBaruch Siach		pinctrl-names = "default";
494babc5544SBaruch Siach		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
495bdd22a41SBaruch Siach		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
496babc5544SBaruch Siach		reset-assert-us = <10000>;
49746f94c78SRussell King		reset-deassert-us = <10000>;
498a6120833SBaruch Siach	};
499a6120833SBaruch Siach
500fedb923aSLinus Walleij	switch0: ethernet-switch@4 {
501a6120833SBaruch Siach		compatible = "marvell,mv88e6085";
502a6120833SBaruch Siach		reg = <4>;
503a6120833SBaruch Siach		pinctrl-names = "default";
504a6120833SBaruch Siach		pinctrl-0 = <&cp1_switch_reset_pins>;
505a6120833SBaruch Siach		reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
506a6120833SBaruch Siach
507fedb923aSLinus Walleij		ethernet-ports {
508a6120833SBaruch Siach			#address-cells = <1>;
509a6120833SBaruch Siach			#size-cells = <0>;
510a6120833SBaruch Siach
511fedb923aSLinus Walleij			ethernet-port@1 {
512a6120833SBaruch Siach				reg = <1>;
513a6120833SBaruch Siach				label = "lan2";
514a6120833SBaruch Siach				phy-handle = <&switch0phy0>;
515a6120833SBaruch Siach			};
516a6120833SBaruch Siach
517fedb923aSLinus Walleij			ethernet-port@2 {
518a6120833SBaruch Siach				reg = <2>;
519a6120833SBaruch Siach				label = "lan1";
520a6120833SBaruch Siach				phy-handle = <&switch0phy1>;
521a6120833SBaruch Siach			};
522a6120833SBaruch Siach
523fedb923aSLinus Walleij			ethernet-port@3 {
524a6120833SBaruch Siach				reg = <3>;
525a6120833SBaruch Siach				label = "lan4";
526a6120833SBaruch Siach				phy-handle = <&switch0phy2>;
527a6120833SBaruch Siach			};
528a6120833SBaruch Siach
529fedb923aSLinus Walleij			ethernet-port@4 {
530a6120833SBaruch Siach				reg = <4>;
531a6120833SBaruch Siach				label = "lan3";
532a6120833SBaruch Siach				phy-handle = <&switch0phy3>;
533a6120833SBaruch Siach			};
534a6120833SBaruch Siach
535fedb923aSLinus Walleij			ethernet-port@5 {
536a6120833SBaruch Siach				reg = <5>;
537a6120833SBaruch Siach				label = "cpu";
538a6120833SBaruch Siach				ethernet = <&cp1_eth2>;
53962bba54dSBaruch Siach				phy-mode = "2500base-x";
54062bba54dSBaruch Siach				managed = "in-band-status";
541a6120833SBaruch Siach			};
542a6120833SBaruch Siach		};
543a6120833SBaruch Siach
544a6120833SBaruch Siach		mdio {
545a6120833SBaruch Siach			#address-cells = <1>;
546a6120833SBaruch Siach			#size-cells = <0>;
547a6120833SBaruch Siach
548fedb923aSLinus Walleij			switch0phy0: ethernet-phy@11 {
549a6120833SBaruch Siach				reg = <0x11>;
550a6120833SBaruch Siach			};
551a6120833SBaruch Siach
552fedb923aSLinus Walleij			switch0phy1: ethernet-phy@12 {
553a6120833SBaruch Siach				reg = <0x12>;
554a6120833SBaruch Siach			};
555a6120833SBaruch Siach
556fedb923aSLinus Walleij			switch0phy2: ethernet-phy@13 {
557a6120833SBaruch Siach				reg = <0x13>;
558a6120833SBaruch Siach			};
559a6120833SBaruch Siach
560fedb923aSLinus Walleij			switch0phy3: ethernet-phy@14 {
561a6120833SBaruch Siach				reg = <0x14>;
562a6120833SBaruch Siach			};
563a6120833SBaruch Siach		};
564a6120833SBaruch Siach	};
565a6120833SBaruch Siach};
566a6120833SBaruch Siach
567a6120833SBaruch Siach&cp1_ethernet {
568a6120833SBaruch Siach	status = "okay";
569a6120833SBaruch Siach};
570a6120833SBaruch Siach
571a6120833SBaruch Siach/* 1G copper */
572a6120833SBaruch Siach&cp1_eth1 {
573a6120833SBaruch Siach	status = "okay";
574a6120833SBaruch Siach	phy-mode = "sgmii";
575a6120833SBaruch Siach	phy = <&ge_phy>;
576a6120833SBaruch Siach	phys = <&cp1_comphy3 1>;
577a6120833SBaruch Siach};
578a6120833SBaruch Siach
579a6120833SBaruch Siach/* Switch uplink */
580a6120833SBaruch Siach&cp1_eth2 {
581a6120833SBaruch Siach	status = "okay";
582a6120833SBaruch Siach	phy-mode = "2500base-x";
583a6120833SBaruch Siach	phys = <&cp1_comphy5 2>;
5847c6719a1SRussell King	managed = "in-band-status";
585a6120833SBaruch Siach};
586a6120833SBaruch Siach
587a6120833SBaruch Siach&cp1_spi1 {
588a6120833SBaruch Siach	pinctrl-names = "default";
589a6120833SBaruch Siach	pinctrl-0 = <&cp1_spi1_pins>;
590a6120833SBaruch Siach	status = "okay";
591a6120833SBaruch Siach
5922f00bb4aSKrzysztof Kozlowski	flash@0 {
593a6120833SBaruch Siach		compatible = "st,w25q32";
594a6120833SBaruch Siach		spi-max-frequency = <50000000>;
595a6120833SBaruch Siach		reg = <0>;
596a6120833SBaruch Siach	};
597a6120833SBaruch Siach};
598a6120833SBaruch Siach
59996018a6fSMiquel Raynal&cp1_comphy2 {
60096018a6fSMiquel Raynal	cp1_usbh0_con: connector {
60196018a6fSMiquel Raynal		compatible = "usb-a-connector";
60296018a6fSMiquel Raynal		phy-supply = <&v_5v0_usb3_hst_vbus>;
60396018a6fSMiquel Raynal	};
60496018a6fSMiquel Raynal};
60596018a6fSMiquel Raynal
606a6120833SBaruch Siach&cp1_usb3_0 {
60701d0debaSMiquel Raynal	phys = <&cp1_comphy2 0>;
60801d0debaSMiquel Raynal	phy-names = "cp1-usb3h0-comphy";
609a6120833SBaruch Siach	status = "okay";
610a6120833SBaruch Siach};
611