xref: /linux/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts (revision e78f70bad29c5ae1e1076698b690b15794e9b81e) 
1// SPDX-License-Identifier:     GPL-2.0
2/*
3 * Copyright (C) 2025, Altera Corporation
4 */
5#include "socfpga_agilex5.dtsi"
6
7/ {
8	model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
9	compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";
10
11	aliases {
12		serial0 = &uart0;
13	};
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	leds {
20		compatible = "gpio-leds";
21		led0 {
22			label = "hps_led0";
23			gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
24		};
25
26		led1 {
27			label = "hps_led1";
28			gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
29		};
30	};
31
32	memory@80000000 {
33		device_type = "memory";
34		/* We expect the bootloader to fill in the reg */
35		reg = <0x0 0x80000000 0x0 0x0>;
36	};
37};
38
39&gpio0 {
40	status = "okay";
41};
42
43&gpio1 {
44	status = "okay";
45};
46
47&i2c0 {
48	status = "okay";
49};
50
51&i3c0 {
52	status = "okay";
53};
54
55&i3c1 {
56	status = "okay";
57};
58
59&nand {
60	status = "okay";
61
62	nand@0 {
63		#address-cells = <1>;
64		#size-cells = <1>;
65		reg = <0>;
66		nand-bus-width = <8>;
67
68		partition@0 {
69			label = "u-boot";
70			reg = <0 0x200000>;
71		};
72		partition@200000 {
73			label = "root";
74			reg = <0x200000 0xffe00000>;
75		};
76	};
77};
78
79&osc1 {
80	clock-frequency = <25000000>;
81};
82
83&uart0 {
84	status = "okay";
85};
86
87&watchdog0 {
88	status = "okay";
89};
90