1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx95.dtsi" 11 12#define FALLING_EDGE 1 13#define RISING_EDGE 2 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 16#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 18#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 20 21/ { 22 model = "NXP i.MX95 19X19 board"; 23 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 24 25 aliases { 26 ethernet0 = &enetc_port0; 27 gpio0 = &gpio1; 28 gpio1 = &gpio2; 29 gpio2 = &gpio3; 30 gpio3 = &gpio4; 31 gpio4 = &gpio5; 32 i2c0 = &lpi2c1; 33 i2c1 = &lpi2c2; 34 i2c2 = &lpi2c3; 35 i2c3 = &lpi2c4; 36 i2c4 = &lpi2c5; 37 i2c5 = &lpi2c6; 38 i2c6 = &lpi2c7; 39 i2c7 = &lpi2c8; 40 mmc0 = &usdhc1; 41 mmc1 = &usdhc2; 42 serial0 = &lpuart1; 43 }; 44 45 bt_sco_codec: audio-codec-bt-sco { 46 #sound-dai-cells = <1>; 47 compatible = "linux,bt-sco"; 48 }; 49 50 chosen { 51 stdout-path = &lpuart1; 52 }; 53 54 memory@80000000 { 55 device_type = "memory"; 56 reg = <0x0 0x80000000 0 0x80000000>; 57 }; 58 59 fan0: pwm-fan { 60 compatible = "pwm-fan"; 61 #cooling-cells = <2>; 62 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 63 cooling-levels = <64 128 192 255>; 64 }; 65 66 reserved-memory { 67 #address-cells = <2>; 68 #size-cells = <2>; 69 ranges; 70 71 linux_cma: linux,cma { 72 compatible = "shared-dma-pool"; 73 alloc-ranges = <0 0x80000000 0 0x7f000000>; 74 size = <0 0x3c000000>; 75 linux,cma-default; 76 reusable; 77 }; 78 }; 79 80 flexcan1_phy: can-phy0 { 81 compatible = "nxp,tjr1443"; 82 #phy-cells = <0>; 83 max-bitrate = <1000000>; 84 enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>; 85 standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>; 86 }; 87 88 flexcan2_phy: can-phy1 { 89 compatible = "nxp,tjr1443"; 90 #phy-cells = <0>; 91 max-bitrate = <1000000>; 92 enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>; 93 standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>; 94 }; 95 96 reg_vref_1v8: regulator-1p8v { 97 compatible = "regulator-fixed"; 98 regulator-max-microvolt = <1800000>; 99 regulator-min-microvolt = <1800000>; 100 regulator-name = "+V1.8_SW"; 101 }; 102 103 reg_3p3v: regulator-3p3v { 104 compatible = "regulator-fixed"; 105 regulator-max-microvolt = <3300000>; 106 regulator-min-microvolt = <3300000>; 107 regulator-name = "+V3.3_SW"; 108 }; 109 110 reg_audio_pwr: regulator-audio-pwr { 111 compatible = "regulator-fixed"; 112 regulator-name = "audio-pwr"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 regulator-always-on; 118 }; 119 120 reg_audio_slot: regulator-audio-slot { 121 compatible = "regulator-fixed"; 122 regulator-name = "audio-wm8962"; 123 regulator-min-microvolt = <3300000>; 124 regulator-max-microvolt = <3300000>; 125 gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 regulator-always-on; 128 status = "disabled"; 129 }; 130 131 reg_m2_pwr: regulator-m2-pwr { 132 compatible = "regulator-fixed"; 133 regulator-name = "M.2-power"; 134 regulator-min-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>; 136 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 137 enable-active-high; 138 }; 139 140 reg_pcie0: regulator-pcie { 141 compatible = "regulator-fixed"; 142 regulator-name = "PCIE_WLAN_EN"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 vin-supply = <®_m2_pwr>; 146 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 147 enable-active-high; 148 }; 149 150 reg_slot_pwr: regulator-slot-pwr { 151 compatible = "regulator-fixed"; 152 regulator-name = "PCIe slot-power"; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 156 enable-active-high; 157 }; 158 159 reg_usdhc2_vmmc: regulator-usdhc2 { 160 compatible = "regulator-fixed"; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 163 regulator-name = "VDD_SD2_3V3"; 164 regulator-min-microvolt = <3300000>; 165 regulator-max-microvolt = <3300000>; 166 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 167 enable-active-high; 168 off-on-delay-us = <12000>; 169 }; 170 171 reg_usb_vbus: regulator-vbus { 172 compatible = "regulator-fixed"; 173 regulator-name = "USB_VBUS"; 174 regulator-min-microvolt = <5000000>; 175 regulator-max-microvolt = <5000000>; 176 gpio = <&i2c7_pcal6524 3 GPIO_ACTIVE_HIGH>; 177 enable-active-high; 178 }; 179 180 sound-bt-sco { 181 compatible = "simple-audio-card"; 182 simple-audio-card,name = "bt-sco-audio"; 183 simple-audio-card,format = "dsp_a"; 184 simple-audio-card,bitclock-inversion; 185 simple-audio-card,frame-master = <&btcpu>; 186 simple-audio-card,bitclock-master = <&btcpu>; 187 188 btcpu: simple-audio-card,cpu { 189 sound-dai = <&sai1>; 190 dai-tdm-slot-num = <2>; 191 dai-tdm-slot-width = <16>; 192 }; 193 194 simple-audio-card,codec { 195 sound-dai = <&bt_sco_codec 1>; 196 }; 197 }; 198 199 sound-micfil { 200 compatible = "fsl,imx-audio-card"; 201 model = "micfil-audio"; 202 203 pri-dai-link { 204 link-name = "micfil hifi"; 205 format = "i2s"; 206 cpu { 207 sound-dai = <&micfil>; 208 }; 209 }; 210 }; 211 212 sound-wm8962 { 213 compatible = "fsl,imx-audio-wm8962"; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_hp>; 216 model = "wm8962-audio"; 217 audio-cpu = <&sai3>; 218 audio-codec = <&wm8962>; 219 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 220 audio-routing = "Headphone Jack", "HPOUTL", 221 "Headphone Jack", "HPOUTR", 222 "Ext Spk", "SPKOUTL", 223 "Ext Spk", "SPKOUTR", 224 "AMIC", "MICBIAS", 225 "IN3R", "AMIC", 226 "IN1R", "AMIC"; 227 }; 228}; 229 230&adc1 { 231 vref-supply = <®_vref_1v8>; 232 status = "okay"; 233}; 234 235&enetc_port0 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_enetc0>; 238 phy-handle = <ðphy0>; 239 phy-mode = "rgmii-id"; 240 status = "okay"; 241}; 242 243&flexcan1 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_flexcan1>; 246 phys = <&flexcan1_phy>; 247 status = "disabled"; 248}; 249 250&flexcan2 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_flexcan2>; 253 phys = <&flexcan2_phy>; 254 status = "okay"; 255}; 256 257&flexspi1 { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_flexspi1>; 260 status = "okay"; 261 262 flash@0 { 263 compatible = "jedec,spi-nor"; 264 reg = <0>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_flexspi1_reset>; 267 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 268 #address-cells = <1>; 269 #size-cells = <1>; 270 spi-max-frequency = <200000000>; 271 spi-tx-bus-width = <8>; 272 spi-rx-bus-width = <8>; 273 }; 274}; 275 276&lpi2c2 { 277 clock-frequency = <400000>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_lpi2c2>; 280 status = "okay"; 281 282 adp5585: io-expander@34 { 283 compatible = "adi,adp5585-00", "adi,adp5585"; 284 reg = <0x34>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 gpio-reserved-ranges = <5 1>; 288 #pwm-cells = <3>; 289 }; 290}; 291 292&lpi2c3 { 293 clock-frequency = <400000>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_lpi2c3>; 296 status = "okay"; 297 298 i2c3_gpio_expander_20: gpio@20 { 299 compatible = "nxp,pcal6408"; 300 #gpio-cells = <2>; 301 gpio-controller; 302 reg = <0x20>; 303 vcc-supply = <®_3p3v>; 304 }; 305}; 306 307&lpi2c4 { 308 clock-frequency = <400000>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_lpi2c4>; 311 status = "okay"; 312 313 wm8962: audio-codec@1a { 314 compatible = "wlf,wm8962"; 315 reg = <0x1a>; 316 clocks = <&scmi_clk IMX95_CLK_SAI3>; 317 DCVDD-supply = <®_audio_pwr>; 318 DBVDD-supply = <®_audio_pwr>; 319 AVDD-supply = <®_audio_pwr>; 320 CPVDD-supply = <®_audio_pwr>; 321 MICVDD-supply = <®_audio_pwr>; 322 PLLVDD-supply = <®_audio_pwr>; 323 SPKVDD1-supply = <®_audio_pwr>; 324 SPKVDD2-supply = <®_audio_pwr>; 325 gpio-cfg = < 0x0000 /* 0:Default */ 326 0x0000 /* 1:Default */ 327 0x0000 /* 2:FN_DMICCLK */ 328 0x0000 /* 3:Default */ 329 0x0000 /* 4:FN_DMICCDAT */ 330 0x0000 /* 5:Default */ 331 >; 332 }; 333 334 i2c4_gpio_expander_21: gpio@21 { 335 compatible = "nxp,pcal6408"; 336 reg = <0x21>; 337 #gpio-cells = <2>; 338 gpio-controller; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 interrupt-parent = <&gpio2>; 342 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 345 vcc-supply = <®_3p3v>; 346 }; 347}; 348 349&lpi2c5 { 350 clock-frequency = <100000>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_lpi2c5>; 353 status = "okay"; 354 355 i2c5_pcal6408: gpio@21 { 356 compatible = "nxp,pcal6408"; 357 reg = <0x21>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 vcc-supply = <®_3p3v>; 361 }; 362}; 363 364&lpi2c6 { 365 clock-frequency = <100000>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_lpi2c6>; 368 status = "okay"; 369 370 i2c6_pcal6416: gpio@21 { 371 compatible = "nxp,pcal6416"; 372 reg = <0x21>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 interrupt-parent = <&gpio4>; 378 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_pcal6416>; 381 vcc-supply = <®_3p3v>; 382 }; 383}; 384 385&lpi2c7 { 386 clock-frequency = <1000000>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_lpi2c7>; 389 status = "okay"; 390 391 i2c7_pcal6524: i2c7-gpio@22 { 392 compatible = "nxp,pcal6524"; 393 reg = <0x22>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 interrupt-parent = <&gpio5>; 401 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 402 }; 403 404 ptn5110: tcpc@50 { 405 compatible = "nxp,ptn5110", "tcpci"; 406 reg = <0x50>; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_typec>; 409 interrupt-parent = <&gpio5>; 410 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 411 412 typec_con: connector { 413 compatible = "usb-c-connector"; 414 label = "USB-C"; 415 power-role = "dual"; 416 data-role = "dual"; 417 try-power-role = "sink"; 418 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 419 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 420 op-sink-microwatt = <0>; 421 self-powered; 422 423 ports { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 427 port@0 { 428 reg = <0>; 429 430 typec_con_hs: endpoint { 431 remote-endpoint = <&usb3_data_hs>; 432 }; 433 }; 434 435 port@1 { 436 reg = <1>; 437 438 typec_con_ss: endpoint { 439 remote-endpoint = <&usb3_data_ss>; 440 }; 441 }; 442 }; 443 }; 444 }; 445}; 446 447&lpuart1 { 448 /* console */ 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_uart1>; 451 status = "okay"; 452}; 453 454&lpuart5 { 455 pinctrl-names = "default"; 456 pinctrl-0 = <&pinctrl_uart5>; 457 status = "disabled"; 458 459 bluetooth { 460 compatible = "nxp,88w8987-bt"; 461 }; 462}; 463 464&lpspi7 { 465 num-cs = <1>; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pinctrl_lpspi7>; 468 cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 469 status = "okay"; 470}; 471 472&micfil { 473 #sound-dai-cells = <0>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_pdm>; 476 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 477 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 478 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 479 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 480 <&scmi_clk IMX95_CLK_PDM>; 481 assigned-clock-parents = <0>, <0>, <0>, <0>, 482 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 483 assigned-clock-rates = <3932160000>, 484 <3612672000>, <393216000>, 485 <361267200>, <49152000>; 486 status = "okay"; 487}; 488 489&mu7 { 490 status = "okay"; 491}; 492 493&netcmix_blk_ctrl { 494 status = "okay"; 495}; 496 497&netc_blk_ctrl { 498 status = "okay"; 499}; 500 501&netc_emdio { 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_emdio>; 504 status = "okay"; 505 506 ethphy0: ethernet-phy@1 { 507 reg = <1>; 508 reset-gpios = <&i2c5_pcal6408 2 GPIO_ACTIVE_LOW>; 509 reset-assert-us = <10000>; 510 reset-deassert-us = <80000>; 511 realtek,clkout-disable; 512 }; 513}; 514 515&netc_timer { 516 status = "okay"; 517}; 518 519&pcie0 { 520 pinctrl-0 = <&pinctrl_pcie0>; 521 pinctrl-names = "default"; 522 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 523 vpcie-supply = <®_pcie0>; 524 status = "okay"; 525}; 526 527&pcie0_ep { 528 pinctrl-0 = <&pinctrl_pcie0>; 529 pinctrl-names = "default"; 530 vpcie-supply = <®_pcie0>; 531 status = "disabled"; 532}; 533 534&pcie1 { 535 pinctrl-0 = <&pinctrl_pcie1>; 536 pinctrl-names = "default"; 537 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 538 vpcie-supply = <®_slot_pwr>; 539 status = "okay"; 540}; 541 542&pcie1_ep { 543 pinctrl-0 = <&pinctrl_pcie1>; 544 pinctrl-names = "default"; 545 vpcie-supply = <®_slot_pwr>; 546 status = "disabled"; 547}; 548 549&sai1 { 550 #sound-dai-cells = <0>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_sai1>; 553 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 554 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 555 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 556 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 557 <&scmi_clk IMX95_CLK_SAI1>; 558 assigned-clock-parents = <0>, <0>, <0>, <0>, 559 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 560 assigned-clock-rates = <3932160000>, 561 <3612672000>, <393216000>, 562 <361267200>, <12288000>; 563 fsl,sai-mclk-direction-output; 564 status = "okay"; 565}; 566 567&sai3 { 568 #sound-dai-cells = <0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_sai3>; 571 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 572 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 573 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 574 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 575 <&scmi_clk IMX95_CLK_SAI3>; 576 assigned-clock-parents = <0>, <0>, <0>, <0>, 577 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 578 assigned-clock-rates = <3932160000>, 579 <3612672000>, <393216000>, 580 <361267200>, <12288000>; 581 fsl,sai-mclk-direction-output; 582 status = "okay"; 583}; 584 585&tpm3 { 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_tpm3>; 588 status = "okay"; 589}; 590 591&usb2 { 592 dr_mode = "host"; 593 disable-over-current; 594 vbus-supply = <®_usb_vbus>; 595 status = "okay"; 596}; 597 598&usb3 { 599 status = "okay"; 600}; 601 602&usb3_dwc3 { 603 dr_mode = "otg"; 604 hnp-disable; 605 srp-disable; 606 adp-disable; 607 usb-role-switch; 608 role-switch-default-mode = "peripheral"; 609 snps,dis-u1-entry-quirk; 610 snps,dis-u2-entry-quirk; 611 status = "okay"; 612 613 port { 614 usb3_data_hs: endpoint { 615 remote-endpoint = <&typec_con_hs>; 616 }; 617 }; 618}; 619 620&usb3_phy { 621 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; 622 fsl,phy-pcs-tx-swing-full-percent = <100>; 623 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 624 fsl,phy-tx-vboost-level-microvolt = <1156>; 625 orientation-switch; 626 status = "okay"; 627 628 port { 629 usb3_data_ss: endpoint { 630 remote-endpoint = <&typec_con_ss>; 631 }; 632 }; 633}; 634 635&usdhc1 { 636 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 637 pinctrl-0 = <&pinctrl_usdhc1>; 638 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 639 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 640 pinctrl-3 = <&pinctrl_usdhc1>; 641 bus-width = <8>; 642 non-removable; 643 no-sdio; 644 no-sd; 645 status = "okay"; 646}; 647 648&usdhc2 { 649 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 650 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 651 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 652 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 653 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 654 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 655 vmmc-supply = <®_usdhc2_vmmc>; 656 bus-width = <4>; 657 status = "okay"; 658}; 659 660&scmi_misc { 661 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 662 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 663 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 664 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 665 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 666}; 667 668&wdog3 { 669 fsl,ext-reset-output; 670 status = "okay"; 671}; 672 673&scmi_iomuxc { 674 pinctrl_emdio: emdiogrp{ 675 fsl,pins = < 676 IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e 677 IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 678 >; 679 }; 680 681 pinctrl_enetc0: enetc0grp { 682 fsl,pins = < 683 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 684 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 685 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 686 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 687 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 688 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 689 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 690 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 691 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 692 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 693 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 694 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 695 >; 696 }; 697 698 pinctrl_flexcan1: flexcan1grp { 699 fsl,pins = < 700 IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e 701 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e 702 >; 703 }; 704 705 pinctrl_flexcan2: flexcan2grp { 706 fsl,pins = < 707 IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e 708 IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e 709 >; 710 }; 711 712 pinctrl_flexspi1: flexspi1grp { 713 fsl,pins = < 714 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe 715 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe 716 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe 717 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe 718 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe 719 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe 720 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe 721 IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe 722 IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe 723 IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe 724 IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe 725 >; 726 }; 727 728 pinctrl_flexspi1_reset: flexspi1-reset-grp { 729 fsl,pins = < 730 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe 731 >; 732 }; 733 734 pinctrl_hp: hpgrp { 735 fsl,pins = < 736 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 737 >; 738 }; 739 740 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 741 fsl,pins = < 742 IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e 743 >; 744 }; 745 746 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 747 fsl,pins = < 748 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 749 >; 750 }; 751 752 pinctrl_lpi2c1: lpi2c1grp { 753 fsl,pins = < 754 IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e 755 IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e 756 >; 757 }; 758 759 pinctrl_lpi2c2: lpi2c2grp { 760 fsl,pins = < 761 IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 762 IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 763 >; 764 }; 765 766 pinctrl_lpi2c3: lpi2c3grp { 767 fsl,pins = < 768 IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e 769 IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e 770 >; 771 }; 772 773 pinctrl_lpi2c4: lpi2c4grp { 774 fsl,pins = < 775 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 776 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 777 >; 778 }; 779 780 pinctrl_lpi2c5: lpi2c5grp { 781 fsl,pins = < 782 IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 783 IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 784 >; 785 }; 786 787 pinctrl_lpi2c6: lpi2c6grp { 788 fsl,pins = < 789 IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 790 IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 791 >; 792 }; 793 794 pinctrl_lpi2c7: lpi2c7grp { 795 fsl,pins = < 796 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 797 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 798 >; 799 }; 800 801 pinctrl_lpspi7: lpspi7grp { 802 fsl,pins = < 803 IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe 804 IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe 805 IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe 806 IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe 807 >; 808 }; 809 810 pinctrl_pcie0: pcie0grp { 811 fsl,pins = < 812 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 813 >; 814 }; 815 816 pinctrl_pcie1: pcie1grp { 817 fsl,pins = < 818 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 819 >; 820 }; 821 822 pinctrl_pcal6416: pcal6416grp { 823 fsl,pins = < 824 IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 825 >; 826 }; 827 828 pinctrl_pdm: pdmgrp { 829 fsl,pins = < 830 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 831 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 832 >; 833 }; 834 835 pinctrl_sai1: sai1grp { 836 fsl,pins = < 837 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 838 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 839 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 840 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 841 >; 842 }; 843 844 pinctrl_sai2: sai2grp { 845 fsl,pins = < 846 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 847 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 848 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 849 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 850 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 851 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 852 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 853 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 854 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 855 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 856 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 857 >; 858 }; 859 860 pinctrl_sai3: sai3grp { 861 fsl,pins = < 862 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 863 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 864 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 865 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 866 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 867 >; 868 }; 869 870 pinctrl_tpm3: tpm3grp { 871 fsl,pins = < 872 IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e 873 >; 874 }; 875 876 pinctrl_tpm6: tpm6grp { 877 fsl,pins = < 878 IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e 879 >; 880 }; 881 882 pinctrl_uart1: uart1grp { 883 fsl,pins = < 884 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 885 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 886 >; 887 }; 888 889 pinctrl_uart5: uart5grp { 890 fsl,pins = < 891 IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 892 IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e 893 IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 894 IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 895 >; 896 }; 897 898 pinctrl_usdhc1: usdhc1grp { 899 fsl,pins = < 900 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 901 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 902 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 903 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 904 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 905 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 906 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 907 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 908 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 909 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 910 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 911 >; 912 }; 913 914 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 915 fsl,pins = < 916 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 917 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 918 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 919 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 920 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 921 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 922 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 923 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 924 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 925 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 926 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 927 >; 928 }; 929 930 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 931 fsl,pins = < 932 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 933 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 934 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 935 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 936 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 937 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 938 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 939 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 940 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 941 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 942 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 943 >; 944 }; 945 946 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 947 fsl,pins = < 948 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 949 >; 950 }; 951 952 pinctrl_typec: typecgrp { 953 fsl,pins = < 954 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 955 >; 956 }; 957 958 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 959 fsl,pins = < 960 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 961 >; 962 }; 963 964 pinctrl_usdhc2: usdhc2grp { 965 fsl,pins = < 966 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 967 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 968 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 969 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 970 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 971 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 972 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 973 >; 974 }; 975 976 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 977 fsl,pins = < 978 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 979 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 980 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 981 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 982 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 983 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 984 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 985 >; 986 }; 987 988 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 989 fsl,pins = < 990 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 991 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 992 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 993 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 994 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 995 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 996 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 997 >; 998 }; 999}; 1000 1001&thermal_zones { 1002 a55-thermal { 1003 trips { 1004 atrip2: trip2 { 1005 temperature = <55000>; 1006 hysteresis = <2000>; 1007 type = "active"; 1008 }; 1009 1010 atrip3: trip3 { 1011 temperature = <65000>; 1012 hysteresis = <2000>; 1013 type = "active"; 1014 }; 1015 1016 atrip4: trip4 { 1017 temperature = <75000>; 1018 hysteresis = <2000>; 1019 type = "active"; 1020 }; 1021 }; 1022 1023 cooling-maps { 1024 map1 { 1025 trip = <&atrip2>; 1026 cooling-device = <&fan0 0 1>; 1027 }; 1028 1029 map2 { 1030 trip = <&atrip3>; 1031 cooling-device = <&fan0 1 2>; 1032 }; 1033 1034 map3 { 1035 trip = <&atrip4>; 1036 cooling-device = <&fan0 2 3>; 1037 }; 1038 }; 1039 }; 1040}; 1041 1042&tpm6 { 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&pinctrl_tpm6>; 1045 status = "okay"; 1046}; 1047