1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx95.dtsi" 11 12#define FALLING_EDGE 1 13#define RISING_EDGE 2 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 16#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 18#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 20 21/ { 22 model = "NXP i.MX95 19X19 board"; 23 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 24 25 aliases { 26 ethernet0 = &enetc_port0; 27 gpio0 = &gpio1; 28 gpio1 = &gpio2; 29 gpio2 = &gpio3; 30 gpio3 = &gpio4; 31 gpio4 = &gpio5; 32 i2c0 = &lpi2c1; 33 i2c1 = &lpi2c2; 34 i2c2 = &lpi2c3; 35 i2c3 = &lpi2c4; 36 i2c4 = &lpi2c5; 37 i2c5 = &lpi2c6; 38 i2c6 = &lpi2c7; 39 i2c7 = &lpi2c8; 40 mmc0 = &usdhc1; 41 mmc1 = &usdhc2; 42 serial0 = &lpuart1; 43 }; 44 45 bt_sco_codec: audio-codec-bt-sco { 46 #sound-dai-cells = <1>; 47 compatible = "linux,bt-sco"; 48 }; 49 50 chosen { 51 stdout-path = &lpuart1; 52 }; 53 54 memory@80000000 { 55 device_type = "memory"; 56 reg = <0x0 0x80000000 0 0x80000000>; 57 }; 58 59 fan0: pwm-fan { 60 compatible = "pwm-fan"; 61 #cooling-cells = <2>; 62 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 63 cooling-levels = <64 128 192 255>; 64 }; 65 66 reserved-memory { 67 #address-cells = <2>; 68 #size-cells = <2>; 69 ranges; 70 71 linux_cma: linux,cma { 72 compatible = "shared-dma-pool"; 73 alloc-ranges = <0 0x80000000 0 0x7f000000>; 74 size = <0 0x3c000000>; 75 linux,cma-default; 76 reusable; 77 }; 78 }; 79 80 reg_3p3v: regulator-3p3v { 81 compatible = "regulator-fixed"; 82 regulator-max-microvolt = <3300000>; 83 regulator-min-microvolt = <3300000>; 84 regulator-name = "+V3.3_SW"; 85 }; 86 87 reg_audio_pwr: regulator-audio-pwr { 88 compatible = "regulator-fixed"; 89 regulator-name = "audio-pwr"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 gpio = <&i2c4_gpio_expander_21 1 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 regulator-always-on; 95 }; 96 97 reg_audio_slot: regulator-audio-slot { 98 compatible = "regulator-fixed"; 99 regulator-name = "audio-wm8962"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 gpio = <&i2c4_gpio_expander_21 7 GPIO_ACTIVE_HIGH>; 103 enable-active-high; 104 regulator-always-on; 105 status = "disabled"; 106 }; 107 108 reg_m2_pwr: regulator-m2-pwr { 109 compatible = "regulator-fixed"; 110 regulator-name = "M.2-power"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 114 enable-active-high; 115 }; 116 117 reg_pcie0: regulator-pcie { 118 compatible = "regulator-fixed"; 119 regulator-name = "PCIE_WLAN_EN"; 120 regulator-min-microvolt = <3300000>; 121 regulator-max-microvolt = <3300000>; 122 vin-supply = <®_m2_pwr>; 123 gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 124 enable-active-high; 125 }; 126 127 reg_slot_pwr: regulator-slot-pwr { 128 compatible = "regulator-fixed"; 129 regulator-name = "PCIe slot-power"; 130 regulator-min-microvolt = <3300000>; 131 regulator-max-microvolt = <3300000>; 132 gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 133 enable-active-high; 134 }; 135 136 reg_usdhc2_vmmc: regulator-usdhc2 { 137 compatible = "regulator-fixed"; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 140 regulator-name = "VDD_SD2_3V3"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 144 enable-active-high; 145 off-on-delay-us = <12000>; 146 }; 147 148 sound-bt-sco { 149 compatible = "simple-audio-card"; 150 simple-audio-card,name = "bt-sco-audio"; 151 simple-audio-card,format = "dsp_a"; 152 simple-audio-card,bitclock-inversion; 153 simple-audio-card,frame-master = <&btcpu>; 154 simple-audio-card,bitclock-master = <&btcpu>; 155 156 btcpu: simple-audio-card,cpu { 157 sound-dai = <&sai1>; 158 dai-tdm-slot-num = <2>; 159 dai-tdm-slot-width = <16>; 160 }; 161 162 simple-audio-card,codec { 163 sound-dai = <&bt_sco_codec 1>; 164 }; 165 }; 166 167 sound-micfil { 168 compatible = "fsl,imx-audio-card"; 169 model = "micfil-audio"; 170 171 pri-dai-link { 172 link-name = "micfil hifi"; 173 format = "i2s"; 174 cpu { 175 sound-dai = <&micfil>; 176 }; 177 }; 178 }; 179 180 sound-wm8962 { 181 compatible = "fsl,imx-audio-wm8962"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_hp>; 184 model = "wm8962-audio"; 185 audio-cpu = <&sai3>; 186 audio-codec = <&wm8962>; 187 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 188 audio-routing = "Headphone Jack", "HPOUTL", 189 "Headphone Jack", "HPOUTR", 190 "Ext Spk", "SPKOUTL", 191 "Ext Spk", "SPKOUTR", 192 "AMIC", "MICBIAS", 193 "IN3R", "AMIC", 194 "IN1R", "AMIC"; 195 }; 196}; 197 198&enetc_port0 { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_enetc0>; 201 phy-handle = <ðphy0>; 202 phy-mode = "rgmii-id"; 203 status = "okay"; 204}; 205 206&flexspi1 { 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_flexspi1>; 209 status = "okay"; 210 211 flash@0 { 212 compatible = "jedec,spi-nor"; 213 reg = <0>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_flexspi1_reset>; 216 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 spi-max-frequency = <200000000>; 220 spi-tx-bus-width = <8>; 221 spi-rx-bus-width = <8>; 222 }; 223}; 224 225&lpi2c4 { 226 clock-frequency = <400000>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_lpi2c4>; 229 status = "okay"; 230 231 wm8962: audio-codec@1a { 232 compatible = "wlf,wm8962"; 233 reg = <0x1a>; 234 clocks = <&scmi_clk IMX95_CLK_SAI3>; 235 DCVDD-supply = <®_audio_pwr>; 236 DBVDD-supply = <®_audio_pwr>; 237 AVDD-supply = <®_audio_pwr>; 238 CPVDD-supply = <®_audio_pwr>; 239 MICVDD-supply = <®_audio_pwr>; 240 PLLVDD-supply = <®_audio_pwr>; 241 SPKVDD1-supply = <®_audio_pwr>; 242 SPKVDD2-supply = <®_audio_pwr>; 243 gpio-cfg = < 0x0000 /* 0:Default */ 244 0x0000 /* 1:Default */ 245 0x0000 /* 2:FN_DMICCLK */ 246 0x0000 /* 3:Default */ 247 0x0000 /* 4:FN_DMICCDAT */ 248 0x0000 /* 5:Default */ 249 >; 250 }; 251 252 i2c4_gpio_expander_21: gpio@21 { 253 compatible = "nxp,pcal6408"; 254 reg = <0x21>; 255 #gpio-cells = <2>; 256 gpio-controller; 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 interrupt-parent = <&gpio2>; 260 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 263 vcc-supply = <®_3p3v>; 264 }; 265}; 266 267&lpi2c5 { 268 clock-frequency = <100000>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_lpi2c5>; 271 status = "okay"; 272 273 i2c5_pcal6408: gpio@21 { 274 compatible = "nxp,pcal6408"; 275 reg = <0x21>; 276 gpio-controller; 277 #gpio-cells = <2>; 278 vcc-supply = <®_3p3v>; 279 }; 280}; 281 282&lpi2c6 { 283 clock-frequency = <100000>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_lpi2c6>; 286 status = "okay"; 287 288 i2c6_pcal6416: gpio@21 { 289 compatible = "nxp,pcal6416"; 290 reg = <0x21>; 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 interrupt-parent = <&gpio4>; 296 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_pcal6416>; 299 vcc-supply = <®_3p3v>; 300 }; 301}; 302 303&lpi2c7 { 304 clock-frequency = <1000000>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_lpi2c7>; 307 status = "okay"; 308 309 i2c7_pcal6524: i2c7-gpio@22 { 310 compatible = "nxp,pcal6524"; 311 reg = <0x22>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupt-parent = <&gpio5>; 319 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 320 }; 321 322 ptn5110: tcpc@50 { 323 compatible = "nxp,ptn5110", "tcpci"; 324 reg = <0x50>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_typec>; 327 interrupt-parent = <&gpio5>; 328 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 329 330 typec_con: connector { 331 compatible = "usb-c-connector"; 332 label = "USB-C"; 333 power-role = "dual"; 334 data-role = "dual"; 335 try-power-role = "sink"; 336 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 337 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 338 op-sink-microwatt = <0>; 339 self-powered; 340 341 ports { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 345 port@0 { 346 reg = <0>; 347 348 typec_con_hs: endpoint { 349 remote-endpoint = <&usb3_data_hs>; 350 }; 351 }; 352 353 port@1 { 354 reg = <1>; 355 356 typec_con_ss: endpoint { 357 remote-endpoint = <&usb3_data_ss>; 358 }; 359 }; 360 }; 361 }; 362 }; 363}; 364 365&lpuart1 { 366 /* console */ 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_uart1>; 369 status = "okay"; 370}; 371 372&micfil { 373 #sound-dai-cells = <0>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_pdm>; 376 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 377 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 378 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 379 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 380 <&scmi_clk IMX95_CLK_PDM>; 381 assigned-clock-parents = <0>, <0>, <0>, <0>, 382 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 383 assigned-clock-rates = <3932160000>, 384 <3612672000>, <393216000>, 385 <361267200>, <49152000>; 386 status = "okay"; 387}; 388 389&mu7 { 390 status = "okay"; 391}; 392 393&netcmix_blk_ctrl { 394 status = "okay"; 395}; 396 397&netc_blk_ctrl { 398 status = "okay"; 399}; 400 401&netc_emdio { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_emdio>; 404 status = "okay"; 405 406 ethphy0: ethernet-phy@1 { 407 reg = <1>; 408 realtek,clkout-disable; 409 }; 410}; 411 412&pcie0 { 413 pinctrl-0 = <&pinctrl_pcie0>; 414 pinctrl-names = "default"; 415 reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 416 vpcie-supply = <®_pcie0>; 417 status = "okay"; 418}; 419 420&pcie1 { 421 pinctrl-0 = <&pinctrl_pcie1>; 422 pinctrl-names = "default"; 423 reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 424 vpcie-supply = <®_slot_pwr>; 425 status = "okay"; 426}; 427 428&sai1 { 429 #sound-dai-cells = <0>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_sai1>; 432 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 433 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 434 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 435 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 436 <&scmi_clk IMX95_CLK_SAI1>; 437 assigned-clock-parents = <0>, <0>, <0>, <0>, 438 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 439 assigned-clock-rates = <3932160000>, 440 <3612672000>, <393216000>, 441 <361267200>, <12288000>; 442 fsl,sai-mclk-direction-output; 443 status = "okay"; 444}; 445 446&sai3 { 447 #sound-dai-cells = <0>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_sai3>; 450 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 451 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 452 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 453 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 454 <&scmi_clk IMX95_CLK_SAI3>; 455 assigned-clock-parents = <0>, <0>, <0>, <0>, 456 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 457 assigned-clock-rates = <3932160000>, 458 <3612672000>, <393216000>, 459 <361267200>, <12288000>; 460 fsl,sai-mclk-direction-output; 461 status = "okay"; 462}; 463 464&usb3 { 465 status = "okay"; 466}; 467 468&usb3_dwc3 { 469 dr_mode = "otg"; 470 hnp-disable; 471 srp-disable; 472 adp-disable; 473 usb-role-switch; 474 role-switch-default-mode = "peripheral"; 475 snps,dis-u1-entry-quirk; 476 snps,dis-u2-entry-quirk; 477 status = "okay"; 478 479 port { 480 usb3_data_hs: endpoint { 481 remote-endpoint = <&typec_con_hs>; 482 }; 483 }; 484}; 485 486&usb3_phy { 487 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 488 orientation-switch; 489 status = "okay"; 490 491 port { 492 usb3_data_ss: endpoint { 493 remote-endpoint = <&typec_con_ss>; 494 }; 495 }; 496}; 497 498&usdhc1 { 499 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 500 pinctrl-0 = <&pinctrl_usdhc1>; 501 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 502 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 503 pinctrl-3 = <&pinctrl_usdhc1>; 504 bus-width = <8>; 505 non-removable; 506 no-sdio; 507 no-sd; 508 status = "okay"; 509}; 510 511&usdhc2 { 512 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 513 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 514 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 515 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 516 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 517 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 518 vmmc-supply = <®_usdhc2_vmmc>; 519 bus-width = <4>; 520 status = "okay"; 521}; 522 523&scmi_misc { 524 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 525 BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 526 BRD_SM_CTRL_BT_WAKE FALLING_EDGE 527 BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 528 BRD_SM_CTRL_BUTTON FALLING_EDGE>; 529}; 530 531&wdog3 { 532 fsl,ext-reset-output; 533 status = "okay"; 534}; 535 536&scmi_iomuxc { 537 pinctrl_emdio: emdiogrp{ 538 fsl,pins = < 539 IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e 540 IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e 541 >; 542 }; 543 544 pinctrl_enetc0: enetc0grp { 545 fsl,pins = < 546 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e 547 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e 548 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e 549 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e 550 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 551 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 552 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 553 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 554 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 555 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 556 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 557 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 558 >; 559 }; 560 561 pinctrl_flexspi1: flexspi1grp { 562 fsl,pins = < 563 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe 564 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe 565 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe 566 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe 567 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe 568 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe 569 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe 570 IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe 571 IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe 572 IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe 573 IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe 574 >; 575 }; 576 577 pinctrl_flexspi1_reset: flexspi1-reset-grp { 578 fsl,pins = < 579 IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe 580 >; 581 }; 582 583 pinctrl_hp: hpgrp { 584 fsl,pins = < 585 IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e 586 >; 587 }; 588 589 pinctrl_i2c4_pcal6408: i2c4pcal6498grp { 590 fsl,pins = < 591 IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e 592 >; 593 }; 594 595 pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 596 fsl,pins = < 597 IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 598 >; 599 }; 600 601 pinctrl_lpi2c4: lpi2c4grp { 602 fsl,pins = < 603 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 604 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 605 >; 606 }; 607 608 pinctrl_lpi2c5: lpi2c5grp { 609 fsl,pins = < 610 IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 611 IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 612 >; 613 }; 614 615 pinctrl_lpi2c6: lpi2c6grp { 616 fsl,pins = < 617 IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 618 IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 619 >; 620 }; 621 622 pinctrl_lpi2c7: lpi2c7grp { 623 fsl,pins = < 624 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 625 IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 626 >; 627 }; 628 629 pinctrl_pcie0: pcie0grp { 630 fsl,pins = < 631 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 632 >; 633 }; 634 635 pinctrl_pcie1: pcie1grp { 636 fsl,pins = < 637 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 638 >; 639 }; 640 641 pinctrl_pcal6416: pcal6416grp { 642 fsl,pins = < 643 IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 644 >; 645 }; 646 647 pinctrl_pdm: pdmgrp { 648 fsl,pins = < 649 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 650 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 651 >; 652 }; 653 654 pinctrl_sai1: sai1grp { 655 fsl,pins = < 656 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e 657 IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 658 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 659 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e 660 >; 661 }; 662 663 pinctrl_sai2: sai2grp { 664 fsl,pins = < 665 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e 666 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e 667 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e 668 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e 669 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e 670 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e 671 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e 672 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e 673 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e 674 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e 675 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e 676 >; 677 }; 678 679 pinctrl_sai3: sai3grp { 680 fsl,pins = < 681 IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e 682 IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 683 IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 684 IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e 685 IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e 686 >; 687 }; 688 689 pinctrl_tpm6: tpm6grp { 690 fsl,pins = < 691 IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e 692 >; 693 }; 694 695 pinctrl_uart1: uart1grp { 696 fsl,pins = < 697 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 698 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 699 >; 700 }; 701 702 pinctrl_usdhc1: usdhc1grp { 703 fsl,pins = < 704 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 705 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 706 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 707 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 708 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 709 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 710 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 711 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 712 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 713 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 714 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 715 >; 716 }; 717 718 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 719 fsl,pins = < 720 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 721 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 722 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 723 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 724 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 725 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 726 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 727 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 728 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 729 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 730 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 731 >; 732 }; 733 734 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 735 fsl,pins = < 736 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 737 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 738 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 739 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 740 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 741 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 742 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 743 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 744 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 745 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 746 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 747 >; 748 }; 749 750 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 751 fsl,pins = < 752 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 753 >; 754 }; 755 756 pinctrl_typec: typecgrp { 757 fsl,pins = < 758 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 759 >; 760 }; 761 762 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 763 fsl,pins = < 764 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 765 >; 766 }; 767 768 pinctrl_usdhc2: usdhc2grp { 769 fsl,pins = < 770 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 771 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 772 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 773 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 774 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 775 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 776 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 777 >; 778 }; 779 780 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 781 fsl,pins = < 782 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 783 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 784 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 785 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 786 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 787 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 788 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 789 >; 790 }; 791 792 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 793 fsl,pins = < 794 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 795 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 796 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 797 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 798 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 799 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 800 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 801 >; 802 }; 803}; 804 805&thermal_zones { 806 a55-thermal { 807 trips { 808 atrip2: trip2 { 809 temperature = <55000>; 810 hysteresis = <2000>; 811 type = "active"; 812 }; 813 814 atrip3: trip3 { 815 temperature = <65000>; 816 hysteresis = <2000>; 817 type = "active"; 818 }; 819 820 atrip4: trip4 { 821 temperature = <75000>; 822 hysteresis = <2000>; 823 type = "active"; 824 }; 825 }; 826 827 cooling-maps { 828 map1 { 829 trip = <&atrip2>; 830 cooling-device = <&fan0 0 1>; 831 }; 832 833 map2 { 834 trip = <&atrip3>; 835 cooling-device = <&fan0 1 2>; 836 }; 837 838 map3 { 839 trip = <&atrip4>; 840 cooling-device = <&fan0 2 3>; 841 }; 842 }; 843 }; 844}; 845 846&tpm6 { 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_tpm6>; 849 status = "okay"; 850}; 851