1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6#include "imx94.dtsi" 7 8/ { 9 cpus { 10 #address-cells = <1>; 11 #size-cells = <0>; 12 13 idle-states { 14 entry-method = "psci"; 15 16 cpu_pd_wait: cpu-pd-wait { 17 compatible = "arm,idle-state"; 18 arm,psci-suspend-param = <0x0010033>; 19 local-timer-stop; 20 entry-latency-us = <1000>; 21 exit-latency-us = <700>; 22 min-residency-us = <2700>; 23 wakeup-latency-us = <1500>; 24 }; 25 }; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a55"; 29 device_type = "cpu"; 30 reg = <0x0>; 31 enable-method = "psci"; 32 #cooling-cells = <2>; 33 cpu-idle-states = <&cpu_pd_wait>; 34 power-domains = <&scmi_perf IMX94_PERF_A55>; 35 power-domain-names = "perf"; 36 i-cache-size = <32768>; 37 i-cache-line-size = <64>; 38 i-cache-sets = <128>; 39 d-cache-size = <32768>; 40 d-cache-line-size = <64>; 41 d-cache-sets = <128>; 42 next-level-cache = <&l2_cache_l0>; 43 }; 44 45 cpu1: cpu@100 { 46 compatible = "arm,cortex-a55"; 47 device_type = "cpu"; 48 reg = <0x100>; 49 enable-method = "psci"; 50 #cooling-cells = <2>; 51 cpu-idle-states = <&cpu_pd_wait>; 52 power-domains = <&scmi_perf IMX94_PERF_A55>; 53 power-domain-names = "perf"; 54 i-cache-size = <32768>; 55 i-cache-line-size = <64>; 56 i-cache-sets = <128>; 57 d-cache-size = <32768>; 58 d-cache-line-size = <64>; 59 d-cache-sets = <128>; 60 next-level-cache = <&l2_cache_l1>; 61 }; 62 63 cpu2: cpu@200 { 64 compatible = "arm,cortex-a55"; 65 device_type = "cpu"; 66 reg = <0x200>; 67 enable-method = "psci"; 68 #cooling-cells = <2>; 69 cpu-idle-states = <&cpu_pd_wait>; 70 power-domains = <&scmi_perf IMX94_PERF_A55>; 71 power-domain-names = "perf"; 72 i-cache-size = <32768>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <128>; 75 d-cache-size = <32768>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&l2_cache_l2>; 79 }; 80 81 cpu3: cpu@300 { 82 compatible = "arm,cortex-a55"; 83 device_type = "cpu"; 84 reg = <0x300>; 85 enable-method = "psci"; 86 #cooling-cells = <2>; 87 cpu-idle-states = <&cpu_pd_wait>; 88 power-domains = <&scmi_perf IMX94_PERF_A55>; 89 power-domain-names = "perf"; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <128>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_cache_l3>; 97 }; 98 99 l2_cache_l0: l2-cache-l0 { 100 compatible = "cache"; 101 cache-size = <65536>; 102 cache-line-size = <64>; 103 cache-sets = <256>; 104 cache-level = <2>; 105 cache-unified; 106 next-level-cache = <&l3_cache>; 107 }; 108 109 l2_cache_l1: l2-cache-l1 { 110 compatible = "cache"; 111 cache-size = <65536>; 112 cache-line-size = <64>; 113 cache-sets = <256>; 114 cache-level = <2>; 115 cache-unified; 116 next-level-cache = <&l3_cache>; 117 }; 118 119 l2_cache_l2: l2-cache-l2 { 120 compatible = "cache"; 121 cache-size = <65536>; 122 cache-line-size = <64>; 123 cache-sets = <256>; 124 cache-level = <2>; 125 cache-unified; 126 next-level-cache = <&l3_cache>; 127 }; 128 129 l2_cache_l3: l2-cache-l3 { 130 compatible = "cache"; 131 cache-size = <65536>; 132 cache-line-size = <64>; 133 cache-sets = <256>; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&l3_cache>; 137 }; 138 139 l3_cache: l3-cache { 140 compatible = "cache"; 141 cache-size = <1048576>; 142 cache-line-size = <64>; 143 cache-sets = <1024>; 144 cache-level = <3>; 145 cache-unified; 146 }; 147 }; 148}; 149