1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright 2024-2025 NXP 4 */ 5 6 #ifndef __IMX94_POWER_H 7 #define __IMX94_POWER_H 8 9 #define IMX94_PD_ANA 0 10 #define IMX94_PD_AON 1 11 #define IMX94_PD_BBSM 2 12 #define IMX94_PD_M71 3 13 #define IMX94_PD_CCMSRCGPC 4 14 #define IMX94_PD_A55C0 5 15 #define IMX94_PD_A55C1 6 16 #define IMX94_PD_A55C2 7 17 #define IMX94_PD_A55C3 8 18 #define IMX94_PD_A55P 9 19 #define IMX94_PD_DDR 10 20 #define IMX94_PD_DISPLAY 11 21 #define IMX94_PD_M70 12 22 #define IMX94_PD_HSIO_TOP 13 23 #define IMX94_PD_HSIO_WAON 14 24 #define IMX94_PD_NETC 15 25 #define IMX94_PD_NOC 16 26 #define IMX94_PD_NPU 17 27 #define IMX94_PD_WAKEUP 18 28 29 #define IMX94_PERF_M33 0 30 #define IMX94_PERF_M33S 1 31 #define IMX94_PERF_WAKEUP 2 32 #define IMX94_PERF_M70 3 33 #define IMX94_PERF_M71 4 34 #define IMX94_PERF_DRAM 5 35 #define IMX94_PERF_HSIO 6 36 #define IMX94_PERF_NPU 7 37 #define IMX94_PERF_NOC 8 38 #define IMX94_PERF_A55 9 39 #define IMX94_PERF_DISP 10 40 41 #endif /* __IMX94_POWER_H */ 42