1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 */ 5 6#include <dt-bindings/net/ti-dp83867.h> 7#include "imx8mp.dtsi" 8 9/ { 10 compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; 11 model = "PHYTEC phyCORE-i.MX8MP FPSC"; 12 13 aliases { 14 rtc0 = &rv3028; 15 rtc1 = &snvs_rtc; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 reg = <0x0 0x40000000 0x0 0x80000000>; 21 }; 22 23 reg_usdhc2_vmmc: regulator-usdhc2 { 24 compatible = "regulator-fixed"; 25 off-on-delay-us = <12000>; 26 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 27 pinctrl-names = "default"; 28 regulator-max-microvolt = <3300000>; 29 regulator-min-microvolt = <3300000>; 30 regulator-name = "VDDSW_SD2"; 31 startup-delay-us = <100>; 32 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 33 enable-active-high; 34 }; 35 36 reg_vdd_io: regulator-vdd-io { 37 compatible = "regulator-fixed"; 38 regulator-always-on; 39 regulator-boot-on; 40 regulator-name = "VDD_IO"; 41 }; 42}; 43 44&A53_0 { 45 cpu-supply = <&buck2>; 46}; 47 48&A53_1 { 49 cpu-supply = <&buck2>; 50}; 51 52&A53_2 { 53 cpu-supply = <&buck2>; 54}; 55 56&A53_3 { 57 cpu-supply = <&buck2>; 58}; 59 60&ecspi1 { /* FPSC SPI1 */ 61 pinctrl-0 = <&pinctrl_ecspi1>; 62 pinctrl-names = "default"; 63}; 64 65&ecspi2 { /* FPSC SPI2 */ 66 pinctrl-0 = <&pinctrl_ecspi2>; 67 pinctrl-names = "default"; 68}; 69 70&ecspi3 { /* FPSC SPI3 */ 71 pinctrl-0 = <&pinctrl_ecspi3>; 72 pinctrl-names = "default"; 73}; 74 75&eqos { /* FPSC RGMII2 */ 76 phy-mode = "rgmii-id"; 77 pinctrl-0 = <&pinctrl_eqos>; 78 pinctrl-names = "default"; 79}; 80 81&fec { /* FPSC GB_ETH1 */ 82 phy-handle = <ðphy0>; 83 phy-mode = "rgmii-id"; 84 pinctrl-0 = <&pinctrl_fec>; 85 pinctrl-names = "default"; 86 fsl,magic-packet; 87 status = "okay"; 88 89 mdio { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 93 ethphy0: ethernet-phy@0 { 94 compatible = "ethernet-phy-ieee802.3-c22"; 95 reg = <0>; 96 interrupt-parent = <&gpio4>; 97 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 98 enet-phy-lane-no-swap; 99 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 100 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 101 ti,min-output-impedance; 102 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 103 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 104 }; 105 }; 106}; 107 108&flexcan1 { /* FPSC CAN1 */ 109 pinctrl-0 = <&pinctrl_flexcan1>; 110 pinctrl-names = "default"; 111}; 112 113&flexcan2 { /* FPSC CAN2 */ 114 pinctrl-0 = <&pinctrl_flexcan2>; 115 pinctrl-names = "default"; 116}; 117 118&flexspi { /* FPSC QSPI */ 119 pinctrl-0 = <&pinctrl_flexspi>; 120 pinctrl-names = "default"; 121}; 122 123&gpio1 { 124 gpio-line-names = "", "", "", "", "", 125 "", "", "", "PCIE1_nPERST"; 126}; 127 128&gpio2 { 129 gpio-line-names = "", "", "", "", "", 130 "", "", "", "", "", 131 "", "", "", "", "", 132 "", "", "", "", "SD2_RESET_B"; 133}; 134 135&gpio3 { 136 gpio-line-names = "", "", "", "", "", 137 "", "", "", "", "", 138 "", "", "", "", "", 139 "", "", "", "", "I2C6_SCL", 140 "I2C6_SDA", "I2C5_SCL"; 141}; 142 143&gpio4 { /* FPSC GPIO */ 144 gpio-line-names = "GPIO6", "RGMII2_nINT", "GPIO7", "GPIO4", "", 145 "", "", "", "", "", 146 "", "", "", "", "", 147 "", "", "", "X_PMIC_IRQ_B", "", 148 "", "GPIO5", "", "", "RGMII2_EVENT_OUT", 149 "", "", "RGMII2_EVENT_IN"; 150 pinctrl-0 = <&pinctrl_gpio4>; 151 pinctrl-names = "default"; 152}; 153 154&gpio5 { /* FPSC GPIO */ 155 gpio-line-names = "", "", "", "", "I2C5_SDA", 156 "GPIO1", "", "", "", "SPI1_CS", 157 "", "", "", "SPI2_CS", "I2C1_SCL", 158 "I2C1_SDA", "I2C2_SCL", "I2C2_SDA", "I2C3_SCL", "I2C3_SDA", 159 "", "GPIO2", "", "", "SPI3_CS", 160 "", "GPIO3"; 161 pinctrl-0 = <&pinctrl_gpio5>; 162 pinctrl-names = "default"; 163}; 164 165&i2c1 { /* FPSC I2C1 */ 166 clock-frequency = <400000>; 167 pinctrl-0 = <&pinctrl_i2c1>; 168 pinctrl-1 = <&pinctrl_i2c1_gpio>; 169 pinctrl-names = "default", "gpio"; 170 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 171 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 172 status = "okay"; 173 174 pmic: pmic@25 { 175 compatible = "nxp,pca9450c"; 176 reg = <0x25>; 177 interrupt-parent = <&gpio4>; 178 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 179 pinctrl-0 = <&pinctrl_pmic>; 180 pinctrl-names = "default"; 181 182 regulators { 183 buck1: BUCK1 { 184 regulator-always-on; 185 regulator-boot-on; 186 regulator-max-microvolt = <950000>; 187 regulator-min-microvolt = <850000>; 188 regulator-name = "VDD_SOC (BUCK1)"; 189 regulator-ramp-delay = <3125>; 190 }; 191 192 buck2: BUCK2 { 193 regulator-always-on; 194 regulator-boot-on; 195 regulator-max-microvolt = <1000000>; 196 regulator-min-microvolt = <850000>; 197 regulator-name = "VDD_ARM (BUCK2)"; 198 regulator-ramp-delay = <3125>; 199 nxp,dvs-run-voltage = <950000>; 200 nxp,dvs-standby-voltage = <850000>; 201 }; 202 203 buck4: BUCK4 { 204 regulator-always-on; 205 regulator-boot-on; 206 regulator-max-microvolt = <3300000>; 207 regulator-min-microvolt = <3300000>; 208 regulator-name = "VDD_3V3 (BUCK4)"; 209 }; 210 211 buck5: BUCK5 { 212 regulator-always-on; 213 regulator-boot-on; 214 regulator-max-microvolt = <1800000>; 215 regulator-min-microvolt = <1800000>; 216 regulator-name = "VDD_1V8 (BUCK5)"; 217 }; 218 219 buck6: BUCK6 { 220 regulator-always-on; 221 regulator-boot-on; 222 regulator-max-microvolt = <1155000>; 223 regulator-min-microvolt = <1045000>; 224 regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; 225 }; 226 227 ldo1: LDO1 { 228 regulator-always-on; 229 regulator-boot-on; 230 regulator-max-microvolt = <1800000>; 231 regulator-min-microvolt = <1800000>; 232 regulator-name = "NVCC_SNVS_1V8 (LDO1)"; 233 }; 234 235 ldo3: LDO3 { 236 regulator-always-on; 237 regulator-boot-on; 238 regulator-max-microvolt = <1800000>; 239 regulator-min-microvolt = <1800000>; 240 regulator-name = "VDDA_1V8 (LDO3)"; 241 }; 242 243 ldo5: LDO5 { 244 regulator-always-on; 245 regulator-boot-on; 246 regulator-max-microvolt = <3300000>; 247 regulator-min-microvolt = <1800000>; 248 regulator-name = "NVCC_SD2 (LDO5)"; 249 }; 250 }; 251 }; 252 253 /* User EEPROM */ 254 eeprom@50 { 255 compatible = "atmel,24c32"; 256 reg = <0x50>; 257 pagesize = <32>; 258 vcc-supply = <®_vdd_io>; 259 }; 260 261 /* factory EEPROM */ 262 eeprom@51 { 263 compatible = "atmel,24c32"; 264 reg = <0x51>; 265 pagesize = <32>; 266 read-only; 267 vcc-supply = <®_vdd_io>; 268 }; 269 270 rv3028: rtc@52 { 271 compatible = "microcrystal,rv3028"; 272 reg = <0x52>; 273 }; 274}; 275 276&i2c2 { /* FPSC I2C2 */ 277 pinctrl-0 = <&pinctrl_i2c2>; 278 pinctrl-1 = <&pinctrl_i2c2_gpio>; 279 pinctrl-names = "default", "gpio"; 280 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 281 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 282}; 283 284&i2c3 { /* FPSC I2C3 */ 285 pinctrl-0 = <&pinctrl_i2c3>; 286 pinctrl-1 = <&pinctrl_i2c3_gpio>; 287 pinctrl-names = "default", "gpio"; 288 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 289 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 290}; 291 292&i2c5 { /* FPSC I2C4 */ 293 pinctrl-0 = <&pinctrl_i2c5>; 294 pinctrl-1 = <&pinctrl_i2c5_gpio>; 295 pinctrl-names = "default", "gpio"; 296 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 297 sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 298}; 299 300&i2c6 { /* FPSC I2C5 */ 301 pinctrl-0 = <&pinctrl_i2c6>; 302 pinctrl-1 = <&pinctrl_i2c6_gpio>; 303 pinctrl-names = "default", "gpio"; 304 scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 305 sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 306}; 307 308&iomuxc { 309 pinctrl_flexcan1: can1grp { 310 fsl,pins = < 311 MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN1_TX */ 312 MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN1_RX */ 313 >; 314 }; 315 316 pinctrl_flexcan2: can2grp { 317 fsl,pins = < 318 MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN2_TX */ 319 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 /* CAN2_RX */ 320 >; 321 }; 322 323 pinctrl_eqos: eqosgrp { 324 fsl,pins = < 325 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* RGMII2_nINT */ 326 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 /* RGMII2_EVENT_IN */ 327 MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 /* RGMII2_EVENT_OUT */ 328 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 /* RGMII2_MDIO */ 329 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 /* RGMII2_MDC */ 330 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 /* RGMII2_TX_D3 */ 331 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 /* RGMII2_TX_D2 */ 332 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 /* RGMII2_TX_D1 */ 333 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 /* RGMII2_TX_D0 */ 334 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 /* RGMII2_TX_CTL */ 335 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 /* RGMII2_TXC */ 336 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 /* RGMII2_RX_D3 */ 337 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 /* RGMII2_RX_D2 */ 338 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 /* RGMII2_RX_D1 */ 339 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 /* RGMII2_RX_D0 */ 340 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 /* RGMII2_RX_CTL */ 341 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 /* RGMII2_RXC */ 342 >; 343 }; 344 345 pinctrl_fec: fecgrp { 346 fsl,pins = < 347 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 348 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 349 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 350 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 351 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 352 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 353 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 354 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 355 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 356 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 357 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 358 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 359 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 360 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 361 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 362 >; 363 }; 364 365 pinctrl_flexspi: flexspigrp { 366 fsl,pins = < 367 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 /* QSPI_CE */ 368 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 /* QSPI_CLK */ 369 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 /* QSPI_DATA_0 */ 370 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 /* QSPI_DATA_1 */ 371 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 /* QSPI_DATA_2 */ 372 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 /* QSPI_DATA_3 */ 373 MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82 /* QSPI_DQS */ 374 >; 375 }; 376 377 pinctrl_gpio4: gpio4grp { 378 fsl,pins = < 379 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* GPIO4 */ 380 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 /* GPIO5 */ 381 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x106 /* GPIO6 */ 382 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x106 /* GPIO7 */ 383 >; 384 }; 385 386 pinctrl_gpio5: gpio5grp { 387 fsl,pins = < 388 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* GPIO1 */ 389 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x106 /* GPIO2 */ 390 MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x106 /* GPIO3 */ 391 >; 392 }; 393 394 pinctrl_hdmi: hdmigrp { 395 fsl,pins = < 396 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x106 /* HDMI_CEC */ 397 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x106 /* HDMI_SCL */ 398 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x106 /* HDMI_SDA */ 399 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x106 /* HDMI_HPD */ 400 >; 401 }; 402 403 pinctrl_i2c1_gpio: i2c1gpiogrp { 404 fsl,pins = < 405 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 406 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 407 >; 408 }; 409 410 pinctrl_i2c1: i2c1grp { 411 fsl,pins = < 412 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 /* I2C1_SDA_DNU */ 413 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 /* I2C1_SCL_DNU */ 414 >; 415 }; 416 417 pinctrl_i2c2_gpio: i2c2gpiogrp { 418 fsl,pins = < 419 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 420 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 421 >; 422 }; 423 424 pinctrl_i2c2: i2c2grp { 425 fsl,pins = < 426 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 /* I2C2_SDA */ 427 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 /* I2C2_SCL */ 428 >; 429 }; 430 431 pinctrl_i2c3_gpio: i2c3gpiogrp { 432 fsl,pins = < 433 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 434 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 435 >; 436 }; 437 438 pinctrl_i2c3: i2c3grp { 439 fsl,pins = < 440 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 /* I2C3_SDA */ 441 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 /* I2C3_SCL */ 442 >; 443 }; 444 445 pinctrl_i2c5_gpio: i2c5gpiogrp { 446 fsl,pins = < 447 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 448 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 449 >; 450 }; 451 452 pinctrl_i2c5: i2c5grp { 453 fsl,pins = < 454 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ 455 MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ 456 >; 457 }; 458 459 pinctrl_i2c6_gpio: i2c6gpiogrp { 460 fsl,pins = < 461 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e2 462 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e2 463 >; 464 }; 465 466 pinctrl_i2c6: i2c6grp { 467 fsl,pins = < 468 MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c2 /* I2C5_SDA */ 469 MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c2 /* I2C5_SCL */ 470 >; 471 }; 472 473 pinctrl_pcie0: pcie0grp { 474 fsl,pins = < 475 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x10 /* PCIE1_nCLKREQ */ 476 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* PCIE1_nPERST */ 477 >; 478 }; 479 480 pinctrl_pmic: pmicirqgrp { 481 fsl,pins = < 482 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 483 >; 484 }; 485 486 pinctrl_pwm1: pwm1grp { 487 fsl,pins = < 488 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x106 /* PWM1 */ 489 >; 490 }; 491 492 pinctrl_pwm2: pwm2grp { 493 fsl,pins = < 494 MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x106 /* PWM2 */ 495 >; 496 }; 497 498 pinctrl_pwm3: pwm3grp { 499 fsl,pins = < 500 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x106 /* PWM3 */ 501 >; 502 }; 503 504 pinctrl_pwm4: pwm4grp { 505 fsl,pins = < 506 MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x106 /* PWM4 */ 507 >; 508 }; 509 510 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 511 fsl,pins = < 512 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 513 >; 514 }; 515 516 pinctrl_sai5: sai5grp { 517 fsl,pins = < 518 MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x106 /* SAI1_MCLK */ 519 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x106 /* SAI1_RX_SYNC */ 520 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x106 /* SAI1_RX_BCLK */ 521 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x106 /* SAI1_RX_DATA */ 522 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x106 /* SAI1_TX_SYNC */ 523 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x106 /* SAI1_TX_BCLK */ 524 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x106 /* SAI1_TX_DATA */ 525 >; 526 }; 527 528 pinctrl_ecspi1: spi1grp { 529 fsl,pins = < 530 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 /* SPI1_SCLK */ 531 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 /* SPI1_MOSI */ 532 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 /* SPI1_MISO */ 533 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x106 /* SPI1_CS */ 534 >; 535 }; 536 537 pinctrl_ecspi2: spi2grp { 538 fsl,pins = < 539 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* SPI2_SCLK */ 540 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* SPI2_MOSI */ 541 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* SPI2_MISO */ 542 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x106 /* SPI2_CS */ 543 >; 544 }; 545 546 pinctrl_ecspi3: spi3grp { 547 fsl,pins = < 548 MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x82 /* SPI3_SCLK */ 549 MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x82 /* SPI3_MOSI */ 550 MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x82 /* SPI3_MISO */ 551 MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x106 /* SPI3_CS */ 552 >; 553 }; 554 555 pinctrl_uart2: uart2grp { 556 fsl,pins = < 557 MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x140 /* UART2_RXD */ 558 MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x140 /* UART2_TXD */ 559 MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x140 /* UART2_RTS */ 560 MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x140 /* UART2_CTS */ 561 >; 562 }; 563 564 pinctrl_uart3: uart3grp { 565 fsl,pins = < 566 MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x140 /* UART1_RXD */ 567 MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x140 /* UART1_TXD */ 568 MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x140 /* UART1_RTS */ 569 MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x140 /* UART1_CTS */ 570 >; 571 }; 572 573 pinctrl_uart4: uart4grp { 574 fsl,pins = < 575 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 /* UART3_RXD */ 576 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART3_TXD */ 577 >; 578 }; 579 580 pinctrl_usb0: usb0grp { 581 fsl,pins = < 582 MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x106 /* USB1_PWR_EN */ 583 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x106 /* USB1_OC */ 584 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x106 /* USB1_ID */ 585 >; 586 }; 587 588 pinctrl_usb1: usb1grp { 589 fsl,pins = < 590 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x106 /* USB2_PWR_EN */ 591 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x106 /* USB2_OC */ 592 MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x106 /* USB2_ID */ 593 >; 594 }; 595 596 pinctrl_usdhc1: usdhc1grp { 597 fsl,pins = < 598 MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x106 /* SDIO_WP */ 599 MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x106 /* SDIO_CD */ 600 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x106 /* SDIO_CLK */ 601 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x106 /* SDIO_CLK */ 602 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x106 /* SDIO_DATA0 */ 603 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x106 /* SDIO_DATA1 */ 604 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x106 /* SDIO_DATA2 */ 605 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x106 /* SDIO_DATA3 */ 606 >; 607 }; 608 609 pinctrl_usdhc2: usdhc2grp { 610 fsl,pins = < 611 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ 612 MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ 613 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDCARD_CLK */ 614 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDCARD_CMD */ 615 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDCARD_DATA0 */ 616 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDCARD_DATA1 */ 617 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDCARD_DATA2 */ 618 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDCARD_DATA3 */ 619 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 620 >; 621 }; 622 623 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 624 fsl,pins = < 625 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ 626 MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ 627 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDCARD_CLK */ 628 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDCARD_CMD */ 629 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDCARD_DATA0 */ 630 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDCARD_DATA1 */ 631 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDCARD_DATA2 */ 632 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDCARD_DATA3 */ 633 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 634 >; 635 }; 636 637 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 638 fsl,pins = < 639 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x40 /* SDCARD_CD */ 640 MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x40 /* SDCARD_WP */ 641 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDCARD_CLK */ 642 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDCARD_CMD */ 643 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDCARD_DATA0 */ 644 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDCARD_DATA1 */ 645 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDCARD_DATA2 */ 646 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDCARD_DATA3 */ 647 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 648 >; 649 }; 650 651 pinctrl_usdhc3: usdhc3grp { 652 fsl,pins = < 653 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 654 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 655 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 656 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 657 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 658 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 659 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 660 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 661 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 662 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 663 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 664 >; 665 }; 666 667 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 668 fsl,pins = < 669 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 670 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 671 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 672 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 673 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 674 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 675 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 676 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 677 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 678 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 679 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 680 >; 681 }; 682 683 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 684 fsl,pins = < 685 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 686 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 687 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 688 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 689 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 690 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 691 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 692 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 693 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 694 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 695 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 696 >; 697 }; 698 699 pinctrl_wdog: wdoggrp { 700 fsl,pins = < 701 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 702 >; 703 }; 704}; 705 706&pcie { /* FPSC PCIE1 */ 707 pinctrl-0 = <&pinctrl_pcie0>; 708 pinctrl-names = "default"; 709}; 710 711&pwm1 { /* FPSC PWM1 */ 712 pinctrl-0 = <&pinctrl_pwm1>; 713 pinctrl-names = "default"; 714}; 715 716&pwm2 { /* FPSC PWM2 */ 717 pinctrl-0 = <&pinctrl_pwm2>; 718 pinctrl-names = "default"; 719}; 720 721&pwm3 { /* FPSC PWM3 */ 722 pinctrl-0 = <&pinctrl_pwm3>; 723 pinctrl-names = "default"; 724}; 725 726&pwm4 { /* FPSC PWM4 */ 727 pinctrl-0 = <&pinctrl_pwm4>; 728 pinctrl-names = "default"; 729}; 730 731&sai5 { /* FPSC SAI1 */ 732 pinctrl-0 = <&pinctrl_sai5>; 733 pinctrl-names = "default"; 734}; 735 736&uart2 { /* FPSC UART2 */ 737 pinctrl-0 = <&pinctrl_uart2>; 738 pinctrl-names = "default"; 739 fsl,dte-mode; 740}; 741 742&uart3 { /* FPSC UART1 */ 743 pinctrl-0 = <&pinctrl_uart3>; 744 pinctrl-names = "default"; 745 fsl,dte-mode; 746}; 747 748&uart4 { /* FPSC UART3 */ 749 pinctrl-0 = <&pinctrl_uart4>; 750 pinctrl-names = "default"; 751}; 752 753&usb3_0 { /* FPSC USB1 */ 754 pinctrl-0 = <&pinctrl_usb0>; 755 pinctrl-names = "default"; 756}; 757 758&usb3_1 { /* FPSC USB2 */ 759 pinctrl-0 = <&pinctrl_usb1>; 760 pinctrl-names = "default"; 761}; 762 763&usdhc1 { /* FPSC SDIO */ 764 pinctrl-0 = <&pinctrl_usdhc1>; 765 pinctrl-names = "default"; 766}; 767 768&usdhc2 { /* FPSC SDCARD */ 769 pinctrl-0 = <&pinctrl_usdhc2>; 770 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 771 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 772 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 773 sd-uhs-sdr104; 774 vmmc-supply = <®_usdhc2_vmmc>; 775 vqmmc-supply = <&ldo5>; 776}; 777 778/* eMMC */ 779&usdhc3 { 780 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 781 assigned-clock-rates = <400000000>; 782 bus-width = <8>; 783 non-removable; 784 pinctrl-0 = <&pinctrl_usdhc3>; 785 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 786 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 787 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 788 status = "okay"; 789}; 790 791&wdog1 { 792 pinctrl-0 = <&pinctrl_wdog>; 793 pinctrl-names = "default"; 794 fsl,ext-reset-output; 795 status = "okay"; 796}; 797