1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Boundary Devices 4 * Copyright 2025 Collabora Ltd. 5 */ 6 7#include "imx8mp.dtsi" 8 9/ { 10 model = "Boundary Devices Nitrogen8M Plus Som"; 11 compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp"; 12 13 rfkill-bt { 14 compatible = "rfkill-gpio"; 15 label = "rfkill-bluetooth"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_rfkill_bt>; 18 radio-type = "bluetooth"; 19 shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; 20 }; 21 22 rfkill-wlan { 23 compatible = "rfkill-gpio"; 24 label = "rfkill-wlan"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_rfkill_wlan>; 27 radio-type = "wlan"; 28 shutdown-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; 29 }; 30}; 31 32&A53_0 { 33 cpu-supply = <&buck2>; 34}; 35 36&A53_1 { 37 cpu-supply = <&buck2>; 38}; 39 40&A53_2 { 41 cpu-supply = <&buck2>; 42}; 43 44&A53_3 { 45 cpu-supply = <&buck2>; 46}; 47 48&eqos { 49 phy-handle = <ðphy0>; 50 phy-mode = "rgmii-id"; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_eqos>; 53 status = "okay"; 54 55 mdio { 56 compatible = "snps,dwmac-mdio"; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 ethphy0: ethernet-phy@4 { 61 compatible = "ethernet-phy-ieee802.3-c22"; 62 reg = <4>; 63 eee-broken-1000t; 64 }; 65 }; 66}; 67 68&i2c1 { 69 clock-frequency = <400000>; 70 pinctrl-names = "default", "gpio"; 71 pinctrl-0 = <&pinctrl_i2c1>; 72 pinctrl-1 = <&pinctrl_i2c1_gpio>; 73 scl-gpios = <&gpio5 14 GPIO_OPEN_DRAIN>; 74 sda-gpios = <&gpio5 15 GPIO_OPEN_DRAIN>; 75 status = "okay"; 76 77 pmic: pmic@25 { 78 compatible = "nxp,pca9450c"; 79 reg = <0x25>; 80 interrupt-parent = <&gpio3>; 81 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 82 pinctrl-0 = <&pinctrl_pmic>; 83 84 regulators { 85 86 buck1: BUCK1 { 87 regulator-name = "VDD_SOC (BUCK1)"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-max-microvolt = <2187500>; 91 regulator-min-microvolt = <600000>; 92 regulator-ramp-delay = <3125>; 93 }; 94 95 buck2: BUCK2 { 96 regulator-name = "VDD_ARM (BUCK2)"; 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-max-microvolt = <2187500>; 100 regulator-min-microvolt = <600000>; 101 regulator-ramp-delay = <3125>; 102 }; 103 104 buck4: BUCK4 { 105 regulator-name = "VDD_3P3V (BUCK4)"; 106 regulator-always-on; 107 regulator-boot-on; 108 regulator-max-microvolt = <3400000>; 109 regulator-min-microvolt = <600000>; 110 }; 111 112 buck5: BUCK5 { 113 regulator-name = "VDD_1P8V (BUCK5)"; 114 regulator-always-on; 115 regulator-boot-on; 116 regulator-max-microvolt = <3400000>; 117 regulator-min-microvolt = <600000>; 118 }; 119 120 buck6: BUCK6 { 121 regulator-name = "NVCC_DRAM_1P1V (BUCK6)"; 122 regulator-always-on; 123 regulator-boot-on; 124 regulator-max-microvolt = <3400000>; 125 regulator-min-microvolt = <600000>; 126 }; 127 128 ldo1: LDO1 { 129 regulator-name = "NVCC_SNVS_1V8 (LDO1)"; 130 regulator-always-on; 131 regulator-boot-on; 132 regulator-max-microvolt = <3300000>; 133 regulator-min-microvolt = <1600000>; 134 }; 135 136 ldo3: LDO3 { 137 regulator-name = "VDDA_1V8 (LDO3)"; 138 regulator-always-on; 139 regulator-boot-on; 140 regulator-max-microvolt = <3300000>; 141 regulator-min-microvolt = <800000>; 142 }; 143 144 ldo5: LDO5 { 145 regulator-name = "NVCC_SD1 (LDO5)"; 146 regulator-max-microvolt = <3300000>; 147 regulator-min-microvolt = <1800000>; 148 }; 149 }; 150 }; 151}; 152 153&i2c2 { 154 clock-frequency = <100000>; 155 pinctrl-names = "default", "gpio"; 156 pinctrl-0 = <&pinctrl_i2c2>; 157 pinctrl-1 = <&pinctrl_i2c2_gpio>; 158 scl-gpios = <&gpio5 16 GPIO_OPEN_DRAIN>; 159 sda-gpios = <&gpio5 17 GPIO_OPEN_DRAIN>; 160 status = "okay"; 161}; 162 163&i2c3 { 164 clock-frequency = <100000>; 165 pinctrl-names = "default", "gpio"; 166 pinctrl-0 = <&pinctrl_i2c3>; 167 pinctrl-1 = <&pinctrl_i2c3_gpio>; 168 scl-gpios = <&gpio5 18 GPIO_OPEN_DRAIN>; 169 sda-gpios = <&gpio5 19 GPIO_OPEN_DRAIN>; 170 status = "okay"; 171}; 172 173&i2c4 { 174 clock-frequency = <100000>; 175 pinctrl-names = "default", "gpio"; 176 pinctrl-0 = <&pinctrl_i2c4>; 177 pinctrl-1 = <&pinctrl_i2c4_gpio>; 178 scl-gpios = <&gpio5 20 GPIO_OPEN_DRAIN>; 179 sda-gpios = <&gpio5 21 GPIO_OPEN_DRAIN>; 180 status = "okay"; 181}; 182 183&uart1 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_uart1>; 186 status = "okay"; 187}; 188 189&usdhc2 { 190 bus-width = <4>; 191 keep-power-in-suspend; 192 non-removable; 193 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 194 pinctrl-0 = <&pinctrl_usdhc2>; 195 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 196 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 197 status = "okay"; 198}; 199 200&usdhc3 { 201 bus-width = <8>; 202 non-removable; 203 no-mmc-hs400; 204 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 205 pinctrl-0 = <&pinctrl_usdhc3>; 206 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 207 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 208 status = "okay"; 209}; 210 211&wdog1 { 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_wdog>; 214 fsl,ext-reset-output; 215 status = "okay"; 216}; 217 218&iomuxc { 219 pinctrl_eqos: eqosgrp { 220 fsl,pins = < 221 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20 222 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0 223 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 224 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 225 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 226 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 227 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 228 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 229 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 230 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 231 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 232 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 233 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 234 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 235 236 MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10 237 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100 238 >; 239 }; 240 241 pinctrl_i2c1_gpio: i2c1gpiogrp { 242 fsl,pins = < 243 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 244 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 245 >; 246 }; 247 248 pinctrl_i2c1: i2c1grp { 249 fsl,pins = < 250 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 251 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 252 >; 253 }; 254 255 pinctrl_i2c2_gpio: i2c2gpiogrp { 256 fsl,pins = < 257 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 258 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 259 >; 260 }; 261 262 pinctrl_i2c2: i2c2grp { 263 fsl,pins = < 264 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 265 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 266 >; 267 }; 268 269 pinctrl_i2c3_gpio: i2c3gpiogrp { 270 fsl,pins = < 271 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 272 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 273 >; 274 }; 275 276 pinctrl_i2c3: i2c3grp { 277 fsl,pins = < 278 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 279 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 280 >; 281 }; 282 283 pinctrl_i2c4_gpio: i2c4gpiogrp { 284 fsl,pins = < 285 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3 286 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3 287 >; 288 }; 289 290 pinctrl_i2c4: i2c4grp { 291 fsl,pins = < 292 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 293 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 294 >; 295 }; 296 297 pinctrl_pmic: pmicirqgrp { 298 fsl,pins = < 299 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 300 >; 301 }; 302 303 pinctrl_rfkill_bt: rfkill-btgrp { 304 fsl,pins = < 305 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 306 >; 307 }; 308 309 pinctrl_rfkill_wlan: rfkill-wlangrp { 310 fsl,pins = < 311 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16 312 >; 313 }; 314 315 pinctrl_uart1: uart1grp { 316 fsl,pins = < 317 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 318 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 319 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 320 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 321 >; 322 }; 323 324 pinctrl_usdhc2: usdhc2grp { 325 fsl,pins = < 326 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 327 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 328 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 329 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 330 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 331 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 332 >; 333 }; 334 335 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 336 fsl,pins = < 337 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 338 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 339 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 340 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 341 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 342 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 343 >; 344 }; 345 346 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 347 fsl,pins = < 348 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 349 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 350 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 351 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 352 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 353 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 354 >; 355 }; 356 357 pinctrl_usdhc3: usdhc3grp { 358 fsl,pins = < 359 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x10 360 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x150 361 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x150 362 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x150 363 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x150 364 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x150 365 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x150 366 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x150 367 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x150 368 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x150 369 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140 370 371 >; 372 }; 373 374 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 375 fsl,pins = < 376 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x14 377 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x154 378 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x154 379 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x154 380 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x154 381 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x154 382 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x154 383 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x154 384 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x154 385 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x154 386 >; 387 }; 388 389 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 390 fsl,pins = < 391 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x12 392 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x152 393 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x152 394 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x152 395 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x152 396 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x152 397 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x152 398 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x152 399 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x152 400 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x152 401 >; 402 }; 403 404 pinctrl_wdog: wdoggrp { 405 fsl,pins = < 406 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 407 >; 408 }; 409}; 410