1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6#include "imx8mm-overdrive.dtsi" 7 8/ { 9 aliases { 10 rtc0 = &rtc; 11 rtc1 = &snvs_rtc; 12 }; 13 14 usdhc1_pwrseq: usdhc1_pwrseq { 15 compatible = "mmc-pwrseq-simple"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 18 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 19 clocks = <&osc_32k>; 20 clock-names = "ext_clock"; 21 post-power-on-delay-ms = <80>; 22 }; 23 24 memory@40000000 { 25 device_type = "memory"; 26 reg = <0x0 0x40000000 0 0x80000000>; 27 }; 28}; 29 30&A53_0 { 31 cpu-supply = <&buck2_reg>; 32}; 33 34&A53_1 { 35 cpu-supply = <&buck2_reg>; 36}; 37 38&A53_2 { 39 cpu-supply = <&buck2_reg>; 40}; 41 42&A53_3 { 43 cpu-supply = <&buck2_reg>; 44}; 45 46&ddrc { 47 operating-points-v2 = <&ddrc_opp_table>; 48 49 ddrc_opp_table: opp-table { 50 compatible = "operating-points-v2"; 51 52 opp-25000000 { 53 opp-hz = /bits/ 64 <25000000>; 54 }; 55 56 opp-100000000 { 57 opp-hz = /bits/ 64 <100000000>; 58 }; 59 60 opp-750000000 { 61 opp-hz = /bits/ 64 <750000000>; 62 }; 63 }; 64}; 65 66&fec1 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_fec1>; 69 phy-mode = "rgmii-id"; 70 phy-handle = <ðphy0>; 71 fsl,magic-packet; 72 status = "okay"; 73 74 mdio { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 ethphy0: ethernet-phy@0 { 79 compatible = "ethernet-phy-ieee802.3-c22"; 80 reg = <0>; 81 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 82 interrupt-parent = <&gpio1>; 83 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 84 }; 85 }; 86}; 87 88&flexspi { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_flexspi>; 91 status = "okay"; 92 93 flash@0 { 94 reg = <0>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "jedec,spi-nor"; 98 spi-max-frequency = <80000000>; 99 spi-tx-bus-width = <1>; 100 spi-rx-bus-width = <4>; 101 }; 102}; 103 104&i2c1 { 105 clock-frequency = <400000>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_i2c1>; 108 status = "okay"; 109 110 pmic@4b { 111 compatible = "rohm,bd71847"; 112 reg = <0x4b>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_pmic>; 115 interrupt-parent = <&gpio1>; 116 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 117 rohm,reset-snvs-powered; 118 119 #clock-cells = <0>; 120 clocks = <&osc_32k>; 121 clock-output-names = "clk-32k-out"; 122 123 regulators { 124 buck1_reg: BUCK1 { 125 regulator-name = "buck1"; 126 regulator-min-microvolt = <700000>; 127 regulator-max-microvolt = <1300000>; 128 regulator-boot-on; 129 regulator-always-on; 130 regulator-ramp-delay = <1250>; 131 }; 132 133 buck2_reg: BUCK2 { 134 regulator-name = "buck2"; 135 regulator-min-microvolt = <700000>; 136 regulator-max-microvolt = <1300000>; 137 regulator-boot-on; 138 regulator-always-on; 139 regulator-ramp-delay = <1250>; 140 rohm,dvs-run-voltage = <1000000>; 141 rohm,dvs-idle-voltage = <900000>; 142 }; 143 144 buck3_reg: BUCK3 { 145 // BUCK5 in datasheet 146 regulator-name = "buck3"; 147 regulator-min-microvolt = <700000>; 148 regulator-max-microvolt = <1350000>; 149 regulator-boot-on; 150 regulator-always-on; 151 }; 152 153 buck4_reg: BUCK4 { 154 // BUCK6 in datasheet 155 regulator-name = "buck4"; 156 regulator-min-microvolt = <3000000>; 157 regulator-max-microvolt = <3300000>; 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 162 buck5_reg: BUCK5 { 163 // BUCK7 in datasheet 164 regulator-name = "buck5"; 165 regulator-min-microvolt = <1605000>; 166 regulator-max-microvolt = <1995000>; 167 regulator-boot-on; 168 regulator-always-on; 169 }; 170 171 buck6_reg: BUCK6 { 172 // BUCK8 in datasheet 173 regulator-name = "buck6"; 174 regulator-min-microvolt = <800000>; 175 regulator-max-microvolt = <1400000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 ldo1_reg: LDO1 { 181 regulator-name = "ldo1"; 182 regulator-min-microvolt = <1600000>; 183 regulator-max-microvolt = <3300000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 ldo2_reg: LDO2 { 189 regulator-name = "ldo2"; 190 regulator-min-microvolt = <800000>; 191 regulator-max-microvolt = <900000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 ldo3_reg: LDO3 { 197 regulator-name = "ldo3"; 198 regulator-min-microvolt = <1800000>; 199 regulator-max-microvolt = <3300000>; 200 regulator-boot-on; 201 regulator-always-on; 202 }; 203 204 ldo4_reg: LDO4 { 205 regulator-name = "ldo4"; 206 regulator-min-microvolt = <900000>; 207 regulator-max-microvolt = <1800000>; 208 regulator-boot-on; 209 regulator-always-on; 210 }; 211 212 ldo6_reg: LDO6 { 213 regulator-name = "ldo6"; 214 regulator-min-microvolt = <900000>; 215 regulator-max-microvolt = <1800000>; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 }; 220 }; 221}; 222 223&i2c3 { 224 clock-frequency = <400000>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_i2c3>; 227 status = "okay"; 228 229 eeprom@50 { 230 compatible = "microchip,24c64", "atmel,24c64"; 231 pagesize = <32>; 232 read-only; /* Manufacturing EEPROM programmed at factory */ 233 reg = <0x50>; 234 }; 235 236 rtc: rtc@51 { 237 compatible = "nxp,pcf85263"; 238 reg = <0x51>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_rtc>; 241 interrupt-parent = <&gpio1>; 242 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 243 quartz-load-femtofarads = <12500>; 244 wakeup-source; 245 }; 246}; 247 248&uart1 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_uart1>; 251 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 252 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 253 uart-has-rtscts; 254 status = "okay"; 255 256 bluetooth { 257 compatible = "brcm,bcm43438-bt"; 258 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 259 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 260 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 261 clocks = <&osc_32k>; 262 max-speed = <4000000>; 263 clock-names = "extclk"; 264 }; 265}; 266 267&usdhc1 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 271 pinctrl-0 = <&pinctrl_usdhc1>; 272 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 273 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 274 bus-width = <4>; 275 non-removable; 276 cap-power-off-card; 277 keep-power-in-suspend; 278 mmc-pwrseq = <&usdhc1_pwrseq>; 279 status = "okay"; 280 281 brcmf: wifi@1 { 282 reg = <1>; 283 compatible = "brcm,bcm4329-fmac"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_wlan>; 286 interrupt-parent = <&gpio2>; 287 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-names = "host-wake"; 289 }; 290}; 291 292&usdhc3 { 293 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 294 pinctrl-0 = <&pinctrl_usdhc3>; 295 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 296 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 297 bus-width = <8>; 298 non-removable; 299 status = "okay"; 300}; 301 302&wdog1 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_wdog>; 305 fsl,ext-reset-output; 306 status = "okay"; 307}; 308 309&iomuxc { 310 pinctrl_fec1: fec1grp { 311 fsl,pins = < 312 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 313 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 314 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 315 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 316 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 317 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 318 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 319 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 320 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 321 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 322 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 323 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 324 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 325 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 326 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 327 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 328 >; 329 }; 330 331 pinctrl_i2c1: i2c1grp { 332 fsl,pins = < 333 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 334 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 335 >; 336 }; 337 338 pinctrl_i2c3: i2c3grp { 339 fsl,pins = < 340 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 341 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 342 >; 343 }; 344 345 pinctrl_flexspi: flexspigrp { 346 fsl,pins = < 347 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 348 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 349 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 350 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 351 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 352 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 353 >; 354 }; 355 356 pinctrl_pmic: pmicirqgrp { 357 fsl,pins = < 358 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 359 >; 360 }; 361 362 pinctrl_rtc: rtcgrp { 363 fsl,pins = < 364 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 365 >; 366 }; 367 368 pinctrl_uart1: uart1grp { 369 fsl,pins = < 370 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 371 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 372 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 373 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 374 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 375 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 376 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 377 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 378 >; 379 }; 380 381 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 382 fsl,pins = < 383 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 384 >; 385 }; 386 387 pinctrl_usdhc1: usdhc1grp { 388 fsl,pins = < 389 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 390 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 391 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 392 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 393 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 394 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 395 >; 396 }; 397 398 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 399 fsl,pins = < 400 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 401 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 402 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 403 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 404 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 405 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 406 >; 407 }; 408 409 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 410 fsl,pins = < 411 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 412 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 413 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 414 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 415 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 416 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 417 >; 418 }; 419 420 pinctrl_usdhc3: usdhc3grp { 421 fsl,pins = < 422 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 423 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 424 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 425 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 426 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 427 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 428 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 429 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 430 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 431 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 432 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 433 >; 434 }; 435 436 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 437 fsl,pins = < 438 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 439 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 440 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 441 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 442 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 443 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 444 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 445 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 446 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 447 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 448 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 449 >; 450 }; 451 452 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 453 fsl,pins = < 454 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 455 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 456 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 457 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 458 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 459 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 460 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 461 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 462 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 463 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 464 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 465 >; 466 }; 467 468 pinctrl_wdog: wdoggrp { 469 fsl,pins = < 470 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 471 >; 472 }; 473 474 pinctrl_wlan: wlangrp { 475 fsl,pins = < 476 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 477 >; 478 }; 479}; 480