1e426d63eSAlex Marginean// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2e426d63eSAlex Marginean/* 3e426d63eSAlex Marginean * Device Tree fragment for LS1028A QDS board, serdes 69xx 4e426d63eSAlex Marginean * 5e426d63eSAlex Marginean * Copyright 2019-2021 NXP 6e426d63eSAlex Marginean * 7e426d63eSAlex Marginean * Requires a LS1028A QDS board with lane B rework. 8e426d63eSAlex Marginean * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. 9e426d63eSAlex Marginean */ 10e426d63eSAlex Marginean 11e426d63eSAlex Marginean/dts-v1/; 12e426d63eSAlex Marginean/plugin/; 13e426d63eSAlex Marginean 14*d7a38566SShawn Guo&mdio_slot1 { 15e426d63eSAlex Marginean #address-cells = <1>; 16e426d63eSAlex Marginean #size-cells = <0>; 17e426d63eSAlex Marginean 18e426d63eSAlex Marginean slot1_sgmii: ethernet-phy@2 { 19e426d63eSAlex Marginean /* AQR112 */ 20e426d63eSAlex Marginean reg = <0x2>; 21e426d63eSAlex Marginean compatible = "ethernet-phy-ieee802.3-c45"; 22e426d63eSAlex Marginean }; 23e426d63eSAlex Marginean}; 24e426d63eSAlex Marginean 25*d7a38566SShawn Guo&enetc_port0 { 26e426d63eSAlex Marginean phy-handle = <&slot1_sgmii>; 27e426d63eSAlex Marginean phy-mode = "2500base-x"; 28e426d63eSAlex Marginean status = "okay"; 29e426d63eSAlex Marginean}; 30e426d63eSAlex Marginean 31*d7a38566SShawn Guo&mdio_slot2 { 32e426d63eSAlex Marginean #address-cells = <1>; 33e426d63eSAlex Marginean #size-cells = <0>; 34e426d63eSAlex Marginean 35e426d63eSAlex Marginean /* 4 ports on VSC8514 */ 36e426d63eSAlex Marginean slot2_qsgmii0: ethernet-phy@8 { 37e426d63eSAlex Marginean reg = <0x8>; 38e426d63eSAlex Marginean }; 39e426d63eSAlex Marginean 40e426d63eSAlex Marginean slot2_qsgmii1: ethernet-phy@9 { 41e426d63eSAlex Marginean reg = <0x9>; 42e426d63eSAlex Marginean }; 43e426d63eSAlex Marginean 44e426d63eSAlex Marginean slot2_qsgmii2: ethernet-phy@a { 45e426d63eSAlex Marginean reg = <0xa>; 46e426d63eSAlex Marginean }; 47e426d63eSAlex Marginean 48e426d63eSAlex Marginean slot2_qsgmii3: ethernet-phy@b { 49e426d63eSAlex Marginean reg = <0xb>; 50e426d63eSAlex Marginean }; 51e426d63eSAlex Marginean}; 52e426d63eSAlex Marginean 53*d7a38566SShawn Guo&mscc_felix_ports { 54e426d63eSAlex Marginean port@0 { 55e426d63eSAlex Marginean status = "okay"; 56e426d63eSAlex Marginean phy-handle = <&slot2_qsgmii0>; 57e426d63eSAlex Marginean phy-mode = "qsgmii"; 58e426d63eSAlex Marginean managed = "in-band-status"; 59e426d63eSAlex Marginean }; 60e426d63eSAlex Marginean 61e426d63eSAlex Marginean port@1 { 62e426d63eSAlex Marginean status = "okay"; 63e426d63eSAlex Marginean phy-handle = <&slot2_qsgmii1>; 64e426d63eSAlex Marginean phy-mode = "qsgmii"; 65e426d63eSAlex Marginean managed = "in-band-status"; 66e426d63eSAlex Marginean }; 67e426d63eSAlex Marginean 68e426d63eSAlex Marginean port@2 { 69e426d63eSAlex Marginean status = "okay"; 70e426d63eSAlex Marginean phy-handle = <&slot2_qsgmii2>; 71e426d63eSAlex Marginean phy-mode = "qsgmii"; 72e426d63eSAlex Marginean managed = "in-band-status"; 73e426d63eSAlex Marginean }; 74e426d63eSAlex Marginean 75e426d63eSAlex Marginean port@3 { 76e426d63eSAlex Marginean status = "okay"; 77e426d63eSAlex Marginean phy-handle = <&slot2_qsgmii3>; 78e426d63eSAlex Marginean phy-mode = "qsgmii"; 79e426d63eSAlex Marginean managed = "in-band-status"; 80e426d63eSAlex Marginean }; 81e426d63eSAlex Marginean}; 82e426d63eSAlex Marginean 83*d7a38566SShawn Guo&mscc_felix { 84e426d63eSAlex Marginean status = "okay"; 85e426d63eSAlex Marginean}; 86