1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8012 "T2" SoC 4 * 5 * Other names: H9M, "Gibraltar" 6 * 7 * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@10000 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x10000>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 }; 40 41 cpu1: cpu@10001 { 42 compatible = "apple,hurricane-zephyr"; 43 reg = <0x0 0x10001>; 44 cpu-release-addr = <0 0>; /* To be filled by loader */ 45 operating-points-v2 = <&fusion_opp>; 46 performance-domains = <&cpufreq>; 47 enable-method = "spin-table"; 48 device_type = "cpu"; 49 }; 50 }; 51 52 fusion_opp: opp-table { 53 compatible = "operating-points-v2"; 54 55 /* 56 * Apple Fusion Architecture: Hardware big.LITTLE switcher 57 * that use p-state transitions to switch between cores. 58 * Only one type of core can be active at a given time. 59 * 60 * The E-core frequencies are adjusted so performance scales 61 * linearly with reported clock speed. 62 */ 63 64 opp01 { 65 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 66 opp-level = <1>; 67 clock-latency-ns = <11000>; 68 }; 69 opp02 { 70 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 71 opp-level = <2>; 72 clock-latency-ns = <140000>; 73 }; 74 opp03 { 75 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ 76 opp-level = <3>; 77 clock-latency-ns = <110000>; 78 }; 79 opp04 { 80 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ 81 opp-level = <4>; 82 clock-latency-ns = <130000>; 83 }; 84 opp05 { 85 opp-hz = /bits/ 64 <756000000>; 86 opp-level = <5>; 87 clock-latency-ns = <130000>; 88 }; 89 opp06 { 90 opp-hz = /bits/ 64 <1056000000>; 91 opp-level = <6>; 92 clock-latency-ns = <130000>; 93 }; 94 opp07 { 95 opp-hz = /bits/ 64 <1356000000>; 96 opp-level = <7>; 97 clock-latency-ns = <130000>; 98 }; 99 opp08 { 100 opp-hz = /bits/ 64 <1644000000>; 101 opp-level = <8>; 102 clock-latency-ns = <135000>; 103 }; 104 opp09 { 105 opp-hz = /bits/ 64 <1944000000>; 106 opp-level = <9>; 107 clock-latency-ns = <140000>; 108 }; 109 opp10 { 110 opp-hz = /bits/ 64 <2244000000>; 111 opp-level = <10>; 112 clock-latency-ns = <150000>; 113 }; 114#if 0 115 /* Not available until CPU deep sleep is implemented */ 116 opp11 { 117 opp-hz = /bits/ 64 <2340000000>; 118 opp-level = <11>; 119 clock-latency-ns = <150000>; 120 turbo-mode; 121 }; 122#endif 123 }; 124 125 soc { 126 compatible = "simple-bus"; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 nonposted-mmio; 130 ranges; 131 132 cpufreq: performance-controller@202f20000 { 133 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 134 reg = <0x2 0x02f20000 0 0x1000>; 135 #performance-domain-cells = <0>; 136 }; 137 138 serial0: serial@20a600000 { 139 compatible = "apple,s5l-uart"; 140 reg = <0x2 0x0a600000 0x0 0x4000>; 141 reg-io-width = <4>; 142 interrupt-parent = <&aic>; 143 interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>; 144 /* Use the bootloader-enabled clocks for now. */ 145 clocks = <&clkref>, <&clkref>; 146 clock-names = "uart", "clk_uart_baud0"; 147 power-domains = <&ps_uart0>; 148 status = "disabled"; 149 }; 150 151 pmgr: power-management@20e000000 { 152 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 156 reg = <0x2 0xe000000 0 0x8c000>; 157 }; 158 159 aic: interrupt-controller@20e100000 { 160 compatible = "apple,t8010-aic", "apple,aic"; 161 reg = <0x2 0x0e100000 0x0 0x100000>; 162 #interrupt-cells = <3>; 163 interrupt-controller; 164 power-domains = <&ps_aic>; 165 }; 166 167 pinctrl_ap: pinctrl@20f100000 { 168 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 169 reg = <0x2 0x0f100000 0x0 0x100000>; 170 power-domains = <&ps_gpio>; 171 172 gpio-controller; 173 #gpio-cells = <2>; 174 gpio-ranges = <&pinctrl_ap 0 0 221>; 175 apple,npins = <221>; 176 177 interrupt-controller; 178 #interrupt-cells = <2>; 179 interrupt-parent = <&aic>; 180 interrupts = <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 181 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 182 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 183 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>, 184 <AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH>, 185 <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 186 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>; 187 }; 188 189 pinctrl_aop: pinctrl@2100f0000 { 190 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 191 reg = <0x2 0x0100f0000 0x0 0x10000>; 192 193 gpio-controller; 194 #gpio-cells = <2>; 195 gpio-ranges = <&pinctrl_aop 0 0 41>; 196 apple,npins = <41>; 197 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 interrupt-parent = <&aic>; 201 interrupts = <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 202 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 203 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 204 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>, 205 <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 206 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 207 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>; 208 }; 209 210 pinctrl_nub: pinctrl@2111f0000 { 211 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 212 reg = <0x2 0x111f0000 0x0 0x1000>; 213 214 gpio-controller; 215 #gpio-cells = <2>; 216 gpio-ranges = <&pinctrl_nub 0 0 19>; 217 apple,npins = <19>; 218 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 interrupt-parent = <&aic>; 222 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>, 223 <AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH>, 224 <AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 227 pmgr_mini: power-management@211200000 { 228 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 232 reg = <0x2 0x11200000 0 0x84000>; 233 }; 234 235 wdt: watchdog@2112b0000 { 236 compatible = "apple,t8010-wdt", "apple,wdt"; 237 reg = <0x2 0x112b0000 0x0 0x4000>; 238 clocks = <&clkref>; 239 interrupt-parent = <&aic>; 240 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>; 241 }; 242 243 pinctrl_smc: pinctrl@212024000 { 244 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 245 reg = <0x2 0x12024000 0x0 0x1000>; 246 power-domains = <&ps_smc_cpu>; 247 248 gpio-controller; 249 #gpio-cells = <2>; 250 gpio-ranges = <&pinctrl_smc 0 0 81>; 251 apple,npins = <81>; 252 253 interrupt-controller; 254 #interrupt-cells = <2>; 255 interrupt-parent = <&aic>; 256 interrupts = <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 257 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>, 258 <AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH>, 259 <AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH>, 260 <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 261 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 262 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>; 263 /* 264 * SMC is not yet supported and accessing this pinctrl while SMC is 265 * suspended results in a hang. 266 */ 267 status = "disabled"; 268 }; 269 }; 270 271 timer { 272 compatible = "arm,armv8-timer"; 273 interrupt-parent = <&aic>; 274 interrupt-names = "phys", "virt"; 275 /* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */ 276 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 277 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 278 }; 279}; 280 281#include "t8012-pmgr.dtsi" 282