xref: /linux/arch/arm/boot/dts/vt8500/wm8505.dtsi (revision e78f70bad29c5ae1e1076698b690b15794e9b81e) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	compatible = "wm,wm8505";
12
13	cpus {
14		#address-cells = <0>;
15		#size-cells = <0>;
16
17		cpu {
18			device_type = "cpu";
19			compatible = "arm,arm926ej-s";
20		};
21	};
22
23	memory {
24		device_type = "memory";
25		reg = <0x0 0x0>;
26	};
27
28 	aliases {
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &uart2;
32		serial3 = &uart3;
33		serial4 = &uart4;
34		serial5 = &uart5;
35 	};
36
37	soc {
38		#address-cells = <1>;
39		#size-cells = <1>;
40		compatible = "simple-bus";
41		ranges;
42		interrupt-parent = <&intc0>;
43
44		intc0: interrupt-controller@d8140000 {
45			compatible = "via,vt8500-intc";
46			interrupt-controller;
47			reg = <0xd8140000 0x10000>;
48			#interrupt-cells = <1>;
49		};
50
51		/* Secondary IC cascaded to intc0 */
52		intc1: interrupt-controller@d8150000 {
53			compatible = "via,vt8500-intc";
54			interrupt-controller;
55			#interrupt-cells = <1>;
56			reg = <0xD8150000 0x10000>;
57			interrupts = <56 57 58 59 60 61 62 63>;
58		};
59
60		pinctrl: pinctrl@d8110000 {
61			compatible = "wm,wm8505-pinctrl";
62			reg = <0xd8110000 0x10000>;
63			interrupt-controller;
64			#interrupt-cells = <2>;
65			gpio-controller;
66			#gpio-cells = <2>;
67		};
68
69		chipid@d8120000 {
70			compatible = "via,vt8500-scc-id";
71			reg = <0xd8120000 0x4>;
72		};
73
74		pmc@d8130000 {
75			compatible = "via,vt8500-pmc";
76			reg = <0xd8130000 0x1000>;
77			clocks {
78				#address-cells = <1>;
79				#size-cells = <0>;
80
81				ref24: ref24M {
82					#clock-cells = <0>;
83					compatible = "fixed-clock";
84					clock-frequency = <24000000>;
85				};
86
87				ref25: ref25M {
88					#clock-cells = <0>;
89					compatible = "fixed-clock";
90					clock-frequency = <25000000>;
91				};
92
93				plla: plla {
94					#clock-cells = <0>;
95					compatible = "via,vt8500-pll-clock";
96					clocks = <&ref25>;
97					reg = <0x200>;
98				};
99
100				pllb: pllb {
101					#clock-cells = <0>;
102					compatible = "via,vt8500-pll-clock";
103					clocks = <&ref25>;
104					reg = <0x204>;
105				};
106
107				pllc: pllc {
108					#clock-cells = <0>;
109					compatible = "via,vt8500-pll-clock";
110					clocks = <&ref25>;
111					reg = <0x208>;
112				};
113
114				plld: plld {
115					#clock-cells = <0>;
116					compatible = "via,vt8500-pll-clock";
117					clocks = <&ref25>;
118					reg = <0x20c>;
119				};
120
121				clkarm: arm {
122					#clock-cells = <0>;
123					compatible = "via,vt8500-device-clock";
124					clocks = <&plla>;
125					divisor-reg = <0x300>;
126				};
127
128				clkahb: ahb {
129					#clock-cells = <0>;
130					compatible = "via,vt8500-device-clock";
131					clocks = <&pllb>;
132					divisor-reg = <0x304>;
133				};
134
135				clkapb: apb {
136					#clock-cells = <0>;
137					compatible = "via,vt8500-device-clock";
138					clocks = <&pllb>;
139					divisor-reg = <0x350>;
140				};
141
142				clkddr: ddr {
143					#clock-cells = <0>;
144					compatible = "via,vt8500-device-clock";
145					clocks = <&plld>;
146					divisor-reg = <0x310>;
147				};
148
149				clkuart0: uart0 {
150					#clock-cells = <0>;
151					compatible = "via,vt8500-device-clock";
152					clocks = <&ref24>;
153					enable-reg = <0x250>;
154					enable-bit = <1>;
155				};
156
157				clkuart1: uart1 {
158					#clock-cells = <0>;
159					compatible = "via,vt8500-device-clock";
160					clocks = <&ref24>;
161					enable-reg = <0x250>;
162					enable-bit = <2>;
163				};
164
165				clkuart2: uart2 {
166					#clock-cells = <0>;
167					compatible = "via,vt8500-device-clock";
168					clocks = <&ref24>;
169					enable-reg = <0x250>;
170					enable-bit = <3>;
171				};
172
173				clkuart3: uart3 {
174					#clock-cells = <0>;
175					compatible = "via,vt8500-device-clock";
176					clocks = <&ref24>;
177					enable-reg = <0x250>;
178					enable-bit = <4>;
179				};
180
181				clkuart4: uart4 {
182					#clock-cells = <0>;
183					compatible = "via,vt8500-device-clock";
184					clocks = <&ref24>;
185					enable-reg = <0x250>;
186					enable-bit = <22>;
187				};
188
189				clkuart5: uart5 {
190					#clock-cells = <0>;
191					compatible = "via,vt8500-device-clock";
192					clocks = <&ref24>;
193					enable-reg = <0x250>;
194					enable-bit = <23>;
195				};
196
197				clksdhc: sdhc {
198					#clock-cells = <0>;
199					compatible = "via,vt8500-device-clock";
200					clocks = <&pllb>;
201					divisor-reg = <0x328>;
202					divisor-mask = <0x3f>;
203					enable-reg = <0x254>;
204					enable-bit = <18>;
205				};
206			};
207		};
208
209		timer@d8130100 {
210			compatible = "via,vt8500-timer";
211			reg = <0xd8130100 0x28>;
212			interrupts = <36>, <37>, <38>, <39>;
213		};
214
215		usb@d8007100 {
216			compatible = "via,vt8500-ehci";
217			reg = <0xd8007100 0x200>;
218			interrupts = <1>;
219		};
220
221		usb@d8007300 {
222			compatible = "platform-uhci";
223			reg = <0xd8007300 0x200>;
224			interrupts = <0>;
225		};
226
227		fb: fb@d8050800 {
228			compatible = "wm,wm8505-fb";
229			reg = <0xd8050800 0x200>;
230		};
231
232		ge_rops@d8050400 {
233			compatible = "wm,prizm-ge-rops";
234			reg = <0xd8050400 0x100>;
235		};
236
237		uart0: serial@d8200000 {
238			compatible = "via,vt8500-uart";
239			reg = <0xd8200000 0x1040>;
240			interrupts = <32>;
241			clocks = <&clkuart0>;
242			status = "disabled";
243		};
244
245		uart1: serial@d82b0000 {
246			compatible = "via,vt8500-uart";
247			reg = <0xd82b0000 0x1040>;
248			interrupts = <33>;
249			clocks = <&clkuart1>;
250			status = "disabled";
251		};
252
253		uart2: serial@d8210000 {
254			compatible = "via,vt8500-uart";
255			reg = <0xd8210000 0x1040>;
256			interrupts = <47>;
257			clocks = <&clkuart2>;
258			status = "disabled";
259		};
260
261		uart3: serial@d82c0000 {
262			compatible = "via,vt8500-uart";
263			reg = <0xd82c0000 0x1040>;
264			interrupts = <50>;
265			clocks = <&clkuart3>;
266			status = "disabled";
267		};
268
269		uart4: serial@d8370000 {
270			compatible = "via,vt8500-uart";
271			reg = <0xd8370000 0x1040>;
272			interrupts = <31>;
273			clocks = <&clkuart4>;
274			status = "disabled";
275		};
276
277		uart5: serial@d8380000 {
278			compatible = "via,vt8500-uart";
279			reg = <0xd8380000 0x1040>;
280			interrupts = <30>;
281			clocks = <&clkuart5>;
282			status = "disabled";
283		};
284
285		rtc@d8100000 {
286			compatible = "via,vt8500-rtc";
287			reg = <0xd8100000 0x10000>;
288			interrupts = <48>;
289		};
290
291		sdhc@d800a000 {
292			compatible = "wm,wm8505-sdhc";
293			reg = <0xd800a000 0x400>;
294			interrupts = <20>, <21>;
295			clocks = <&clksdhc>;
296			bus-width = <4>;
297		};
298	};
299};
300