1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&l2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&cpu_spc>; 48 }; 49 50 cpu1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&l2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&cpu_spc>; 59 }; 60 61 cpu2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&l2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&cpu_spc>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&l2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&cpu_spc>; 81 }; 82 83 l2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 cpu_spc: cpu-spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 smem { 217 compatible = "qcom,smem"; 218 memory-region = <&smem_region>; 219 220 hwlocks = <&sfpb_mutex 3>; 221 }; 222 223 smsm { 224 compatible = "qcom,smsm"; 225 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 qcom,ipc-1 = <&l2cc 8 4>; 230 qcom,ipc-2 = <&l2cc 8 14>; 231 qcom,ipc-3 = <&l2cc 8 23>; 232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 233 234 apps_smsm: apps@0 { 235 reg = <0>; 236 #qcom,smem-state-cells = <1>; 237 }; 238 239 modem_smsm: modem@1 { 240 reg = <1>; 241 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; 242 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 q6_smsm: q6@2 { 248 reg = <2>; 249 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 250 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 255 wcnss_smsm: wcnss@3 { 256 reg = <3>; 257 interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; 258 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 }; 262 263 dsps_smsm: dsps@4 { 264 reg = <4>; 265 interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-apq8064", "qcom,scm"; 275 276 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 277 clock-names = "core"; 278 }; 279 }; 280 281 replicator { 282 compatible = "arm,coresight-static-replicator"; 283 284 clocks = <&rpmcc RPM_QDSS_CLK>; 285 clock-names = "apb_pclk"; 286 287 in-ports { 288 port { 289 replicator_in: endpoint { 290 remote-endpoint = <&funnel_out>; 291 }; 292 }; 293 }; 294 295 out-ports { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 replicator_out0: endpoint { 302 remote-endpoint = <&etb_in>; 303 }; 304 }; 305 306 port@1 { 307 reg = <1>; 308 replicator_out1: endpoint { 309 remote-endpoint = <&tpiu_in>; 310 }; 311 }; 312 }; 313 }; 314 315 soc: soc { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges; 319 compatible = "simple-bus"; 320 321 tlmm_pinmux: pinctrl@800000 { 322 compatible = "qcom,apq8064-pinctrl"; 323 reg = <0x800000 0x4000>; 324 325 gpio-controller; 326 gpio-ranges = <&tlmm_pinmux 0 0 90>; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 331 332 pinctrl-names = "default"; 333 pinctrl-0 = <&ps_hold_default_state>; 334 }; 335 336 sfpb_mutex: hwmutex@1200600 { 337 compatible = "qcom,sfpb-mutex"; 338 reg = <0x01200600 0x100>; 339 #hwlock-cells = <1>; 340 }; 341 342 intc: interrupt-controller@2000000 { 343 compatible = "qcom,msm-qgic2"; 344 interrupt-controller; 345 #interrupt-cells = <3>; 346 reg = <0x02000000 0x1000>, 347 <0x02002000 0x1000>; 348 }; 349 350 timer@200a000 { 351 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 352 "qcom,msm-timer"; 353 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 354 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, 355 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 356 reg = <0x0200a000 0x100>; 357 clock-frequency = <27000000>; 358 clocks = <&sleep_clk>; 359 clock-names = "sleep"; 360 cpu-offset = <0x80000>; 361 }; 362 363 acc0: clock-controller@2088000 { 364 compatible = "qcom,kpss-acc-v1"; 365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 366 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 367 clock-names = "pll8_vote", "pxo"; 368 clock-output-names = "acpu0_aux"; 369 #clock-cells = <0>; 370 }; 371 372 acc1: clock-controller@2098000 { 373 compatible = "qcom,kpss-acc-v1"; 374 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 375 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 376 clock-names = "pll8_vote", "pxo"; 377 clock-output-names = "acpu1_aux"; 378 #clock-cells = <0>; 379 }; 380 381 acc2: clock-controller@20a8000 { 382 compatible = "qcom,kpss-acc-v1"; 383 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 384 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 385 clock-names = "pll8_vote", "pxo"; 386 clock-output-names = "acpu2_aux"; 387 #clock-cells = <0>; 388 }; 389 390 acc3: clock-controller@20b8000 { 391 compatible = "qcom,kpss-acc-v1"; 392 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 393 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 394 clock-names = "pll8_vote", "pxo"; 395 clock-output-names = "acpu3_aux"; 396 #clock-cells = <0>; 397 }; 398 399 saw0: power-manager@2089000 { 400 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 401 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 402 403 saw0_vreg: regulator { 404 regulator-min-microvolt = <850000>; 405 regulator-max-microvolt = <1300000>; 406 }; 407 }; 408 409 saw1: power-manager@2099000 { 410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 411 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 412 413 saw1_vreg: regulator { 414 regulator-min-microvolt = <850000>; 415 regulator-max-microvolt = <1300000>; 416 }; 417 }; 418 419 saw2: power-manager@20a9000 { 420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 422 423 saw2_vreg: regulator { 424 regulator-min-microvolt = <850000>; 425 regulator-max-microvolt = <1300000>; 426 }; 427 }; 428 429 saw3: power-manager@20b9000 { 430 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 431 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 432 433 saw3_vreg: regulator { 434 regulator-min-microvolt = <850000>; 435 regulator-max-microvolt = <1300000>; 436 }; 437 }; 438 439 sps_sic_non_secure: interrupt-controller@12100000 { 440 compatible = "qcom,apq8064-sps-sic", "syscon"; 441 reg = <0x12100000 0x10000>; 442 }; 443 444 gsbi1: gsbi@12440000 { 445 status = "disabled"; 446 compatible = "qcom,gsbi-v1.0.0"; 447 cell-index = <1>; 448 reg = <0x12440000 0x100>; 449 clocks = <&gcc GSBI1_H_CLK>; 450 clock-names = "iface"; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges; 454 455 syscon-tcsr = <&tcsr>; 456 457 gsbi1_serial: serial@12450000 { 458 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 459 reg = <0x12450000 0x100>, 460 <0x12400000 0x03>; 461 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 463 clock-names = "core", "iface"; 464 status = "disabled"; 465 }; 466 467 gsbi1_i2c: i2c@12460000 { 468 compatible = "qcom,i2c-qup-v1.1.1"; 469 pinctrl-0 = <&i2c1_default_state>; 470 pinctrl-1 = <&i2c1_sleep_state>; 471 pinctrl-names = "default", "sleep"; 472 reg = <0x12460000 0x1000>; 473 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 475 clock-names = "core", "iface"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 status = "disabled"; 479 }; 480 481 }; 482 483 gsbi2: gsbi@12480000 { 484 status = "disabled"; 485 compatible = "qcom,gsbi-v1.0.0"; 486 cell-index = <2>; 487 reg = <0x12480000 0x100>; 488 clocks = <&gcc GSBI2_H_CLK>; 489 clock-names = "iface"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges; 493 494 syscon-tcsr = <&tcsr>; 495 496 gsbi2_i2c: i2c@124a0000 { 497 compatible = "qcom,i2c-qup-v1.1.1"; 498 reg = <0x124a0000 0x1000>; 499 pinctrl-0 = <&i2c2_default_state>; 500 pinctrl-1 = <&i2c2_sleep_state>; 501 pinctrl-names = "default", "sleep"; 502 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 504 clock-names = "core", "iface"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 status = "disabled"; 508 }; 509 }; 510 511 gsbi3: gsbi@16200000 { 512 status = "disabled"; 513 compatible = "qcom,gsbi-v1.0.0"; 514 cell-index = <3>; 515 reg = <0x16200000 0x100>; 516 clocks = <&gcc GSBI3_H_CLK>; 517 clock-names = "iface"; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges; 521 gsbi3_i2c: i2c@16280000 { 522 compatible = "qcom,i2c-qup-v1.1.1"; 523 pinctrl-0 = <&i2c3_default_state>; 524 pinctrl-1 = <&i2c3_sleep_state>; 525 pinctrl-names = "default", "sleep"; 526 reg = <0x16280000 0x1000>; 527 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GSBI3_QUP_CLK>, 529 <&gcc GSBI3_H_CLK>; 530 clock-names = "core", "iface"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 }; 536 537 gsbi4: gsbi@16300000 { 538 status = "disabled"; 539 compatible = "qcom,gsbi-v1.0.0"; 540 cell-index = <4>; 541 reg = <0x16300000 0x03>; 542 clocks = <&gcc GSBI4_H_CLK>; 543 clock-names = "iface"; 544 #address-cells = <1>; 545 #size-cells = <1>; 546 ranges; 547 548 gsbi4_serial: serial@16340000 { 549 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 550 reg = <0x16340000 0x100>, 551 <0x16300000 0x3>; 552 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 553 pinctrl-0 = <&gsbi4_uart_pin_a>; 554 pinctrl-names = "default"; 555 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 556 clock-names = "core", "iface"; 557 status = "disabled"; 558 }; 559 560 gsbi4_i2c: i2c@16380000 { 561 compatible = "qcom,i2c-qup-v1.1.1"; 562 pinctrl-0 = <&i2c4_default_state>; 563 pinctrl-1 = <&i2c4_sleep_state>; 564 pinctrl-names = "default", "sleep"; 565 reg = <0x16380000 0x1000>; 566 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&gcc GSBI4_QUP_CLK>, 568 <&gcc GSBI4_H_CLK>; 569 clock-names = "core", "iface"; 570 status = "disabled"; 571 }; 572 }; 573 574 gsbi5: gsbi@1a200000 { 575 status = "disabled"; 576 compatible = "qcom,gsbi-v1.0.0"; 577 cell-index = <5>; 578 reg = <0x1a200000 0x03>; 579 clocks = <&gcc GSBI5_H_CLK>; 580 clock-names = "iface"; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges; 584 585 gsbi5_serial: serial@1a240000 { 586 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 587 reg = <0x1a240000 0x100>, 588 <0x1a200000 0x03>; 589 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 591 clock-names = "core", "iface"; 592 status = "disabled"; 593 }; 594 595 gsbi5_spi: spi@1a280000 { 596 compatible = "qcom,spi-qup-v1.1.1"; 597 reg = <0x1a280000 0x1000>; 598 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 599 pinctrl-0 = <&spi5_default_state>; 600 pinctrl-1 = <&spi5_sleep_state>; 601 pinctrl-names = "default", "sleep"; 602 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 603 clock-names = "core", "iface"; 604 status = "disabled"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 }; 608 }; 609 610 gsbi6: gsbi@16500000 { 611 status = "disabled"; 612 compatible = "qcom,gsbi-v1.0.0"; 613 cell-index = <6>; 614 reg = <0x16500000 0x03>; 615 clocks = <&gcc GSBI6_H_CLK>; 616 clock-names = "iface"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges; 620 621 gsbi6_serial: serial@16540000 { 622 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 623 reg = <0x16540000 0x100>, 624 <0x16500000 0x03>; 625 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 627 clock-names = "core", "iface"; 628 status = "disabled"; 629 }; 630 631 gsbi6_i2c: i2c@16580000 { 632 compatible = "qcom,i2c-qup-v1.1.1"; 633 pinctrl-0 = <&i2c6_default_state>; 634 pinctrl-1 = <&i2c6_sleep_state>; 635 pinctrl-names = "default", "sleep"; 636 reg = <0x16580000 0x1000>; 637 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&gcc GSBI6_QUP_CLK>, 639 <&gcc GSBI6_H_CLK>; 640 clock-names = "core", "iface"; 641 status = "disabled"; 642 }; 643 }; 644 645 gsbi7: gsbi@16600000 { 646 status = "disabled"; 647 compatible = "qcom,gsbi-v1.0.0"; 648 cell-index = <7>; 649 reg = <0x16600000 0x100>; 650 clocks = <&gcc GSBI7_H_CLK>; 651 clock-names = "iface"; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges; 655 syscon-tcsr = <&tcsr>; 656 657 gsbi7_serial: serial@16640000 { 658 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 659 reg = <0x16640000 0x1000>, 660 <0x16600000 0x1000>; 661 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 663 clock-names = "core", "iface"; 664 status = "disabled"; 665 }; 666 667 gsbi7_i2c: i2c@16680000 { 668 compatible = "qcom,i2c-qup-v1.1.1"; 669 pinctrl-0 = <&i2c7_default_state>; 670 pinctrl-1 = <&i2c7_sleep_state>; 671 pinctrl-names = "default", "sleep"; 672 reg = <0x16680000 0x1000>; 673 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&gcc GSBI7_QUP_CLK>, 675 <&gcc GSBI7_H_CLK>; 676 clock-names = "core", "iface"; 677 status = "disabled"; 678 }; 679 }; 680 681 rng@1a500000 { 682 compatible = "qcom,prng"; 683 reg = <0x1a500000 0x200>; 684 clocks = <&gcc PRNG_CLK>; 685 clock-names = "core"; 686 }; 687 688 ssbi2: ssbi@c00000 { 689 compatible = "qcom,ssbi"; 690 reg = <0x00c00000 0x1000>; 691 qcom,controller-type = "pmic-arbiter"; 692 }; 693 694 ssbi: ssbi@500000 { 695 compatible = "qcom,ssbi"; 696 reg = <0x00500000 0x1000>; 697 qcom,controller-type = "pmic-arbiter"; 698 }; 699 700 qfprom: efuse@700000 { 701 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 702 reg = <0x00700000 0x1000>; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 706 tsens_calib: calib@404 { 707 reg = <0x404 0x10>; 708 }; 709 tsens_backup: backup-calib@414 { 710 reg = <0x414 0x10>; 711 }; 712 }; 713 714 gcc: clock-controller@900000 { 715 compatible = "qcom,gcc-apq8064", "syscon"; 716 reg = <0x00900000 0x4000>; 717 #clock-cells = <1>; 718 #reset-cells = <1>; 719 clocks = <&cxo_board>, 720 <&pxo_board>, 721 <&lcc PLL4>; 722 clock-names = "cxo", "pxo", "pll4"; 723 724 tsens: thermal-sensor { 725 compatible = "qcom,msm8960-tsens"; 726 727 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 728 nvmem-cell-names = "calib", "calib_backup"; 729 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 730 interrupt-names = "uplow"; 731 732 #qcom,sensors = <11>; 733 #thermal-sensor-cells = <1>; 734 }; 735 }; 736 737 lcc: clock-controller@28000000 { 738 compatible = "qcom,lcc-apq8064"; 739 reg = <0x28000000 0x1000>; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 clocks = <&pxo_board>, 743 <&gcc PLL4_VOTE>, 744 <0>, 745 <0>, <0>, 746 <0>, <0>, 747 <0>; 748 clock-names = "pxo", 749 "pll4_vote", 750 "mi2s_codec_clk", 751 "codec_i2s_mic_codec_clk", 752 "spare_i2s_mic_codec_clk", 753 "codec_i2s_spkr_codec_clk", 754 "spare_i2s_spkr_codec_clk", 755 "pcm_codec_clk"; 756 }; 757 758 mmcc: clock-controller@4000000 { 759 compatible = "qcom,mmcc-apq8064"; 760 reg = <0x4000000 0x1000>; 761 #clock-cells = <1>; 762 #power-domain-cells = <1>; 763 #reset-cells = <1>; 764 clocks = <&pxo_board>, 765 <&gcc PLL3>, 766 <&gcc PLL8_VOTE>, 767 <&dsi0_phy 1>, 768 <&dsi0_phy 0>, 769 <&dsi1_phy 1>, 770 <&dsi1_phy 0>, 771 <&hdmi_phy>; 772 clock-names = "pxo", 773 "pll3", 774 "pll8_vote", 775 "dsi1pll", 776 "dsi1pllbyte", 777 "dsi2pll", 778 "dsi2pllbyte", 779 "hdmipll"; 780 }; 781 782 l2cc: clock-controller@2011000 { 783 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 784 reg = <0x2011000 0x1000>; 785 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 786 clock-names = "pll8_vote", "pxo"; 787 #clock-cells = <0>; 788 }; 789 790 rpm: rpm@108000 { 791 compatible = "qcom,rpm-apq8064"; 792 reg = <0x108000 0x1000>; 793 qcom,ipc = <&l2cc 0x8 2>; 794 795 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 796 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 797 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 798 interrupt-names = "ack", "err", "wakeup"; 799 800 rpmcc: clock-controller { 801 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 802 #clock-cells = <1>; 803 clocks = <&pxo_board>, <&cxo_board>; 804 clock-names = "pxo", "cxo"; 805 }; 806 }; 807 808 usb1: usb@12500000 { 809 compatible = "qcom,ci-hdrc"; 810 reg = <0x12500000 0x200>, 811 <0x12500200 0x200>; 812 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 814 clock-names = "core", "iface"; 815 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 816 assigned-clock-rates = <60000000>; 817 resets = <&gcc USB_HS1_RESET>; 818 reset-names = "core"; 819 phy_type = "ulpi"; 820 ahb-burst-config = <0>; 821 phys = <&usb_hs1_phy>; 822 phy-names = "usb-phy"; 823 status = "disabled"; 824 #reset-cells = <1>; 825 826 ulpi { 827 usb_hs1_phy: phy { 828 compatible = "qcom,usb-hs-phy-apq8064", 829 "qcom,usb-hs-phy"; 830 clocks = <&sleep_clk>, <&cxo_board>; 831 clock-names = "sleep", "ref"; 832 resets = <&usb1 0>; 833 reset-names = "por"; 834 #phy-cells = <0>; 835 }; 836 }; 837 }; 838 839 usb3: usb@12520000 { 840 compatible = "qcom,ci-hdrc"; 841 reg = <0x12520000 0x200>, 842 <0x12520200 0x200>; 843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 845 clock-names = "core", "iface"; 846 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 847 assigned-clock-rates = <60000000>; 848 resets = <&gcc USB_HS3_RESET>; 849 reset-names = "core"; 850 phy_type = "ulpi"; 851 ahb-burst-config = <0>; 852 phys = <&usb_hs3_phy>; 853 phy-names = "usb-phy"; 854 status = "disabled"; 855 #reset-cells = <1>; 856 857 ulpi { 858 usb_hs3_phy: phy { 859 compatible = "qcom,usb-hs-phy-apq8064", 860 "qcom,usb-hs-phy"; 861 #phy-cells = <0>; 862 clocks = <&sleep_clk>, <&cxo_board>; 863 clock-names = "sleep", "ref"; 864 resets = <&usb3 0>; 865 reset-names = "por"; 866 }; 867 }; 868 }; 869 870 usb4: usb@12530000 { 871 compatible = "qcom,ci-hdrc"; 872 reg = <0x12530000 0x200>, 873 <0x12530200 0x200>; 874 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 876 clock-names = "core", "iface"; 877 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 878 assigned-clock-rates = <60000000>; 879 resets = <&gcc USB_HS4_RESET>; 880 reset-names = "core"; 881 phy_type = "ulpi"; 882 ahb-burst-config = <0>; 883 phys = <&usb_hs4_phy>; 884 phy-names = "usb-phy"; 885 status = "disabled"; 886 #reset-cells = <1>; 887 888 ulpi { 889 usb_hs4_phy: phy { 890 compatible = "qcom,usb-hs-phy-apq8064", 891 "qcom,usb-hs-phy"; 892 #phy-cells = <0>; 893 clocks = <&sleep_clk>, <&cxo_board>; 894 clock-names = "sleep", "ref"; 895 resets = <&usb4 0>; 896 reset-names = "por"; 897 }; 898 }; 899 }; 900 901 sata_phy0: phy@1b400000 { 902 compatible = "qcom,apq8064-sata-phy"; 903 status = "disabled"; 904 reg = <0x1b400000 0x200>; 905 clocks = <&gcc SATA_PHY_CFG_CLK>; 906 clock-names = "cfg"; 907 #phy-cells = <0>; 908 }; 909 910 sata0: sata@29000000 { 911 compatible = "qcom,apq8064-ahci", "generic-ahci"; 912 status = "disabled"; 913 reg = <0x29000000 0x180>; 914 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 915 916 clocks = <&gcc SFAB_SATA_S_H_CLK>, 917 <&gcc SATA_H_CLK>, 918 <&gcc SATA_A_CLK>, 919 <&gcc SATA_RXOOB_CLK>, 920 <&gcc SATA_PMALIVE_CLK>; 921 clock-names = "slave_iface", 922 "iface", 923 "core", 924 "rxoob", 925 "pmalive"; 926 927 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 928 <&gcc SATA_PMALIVE_CLK>; 929 assigned-clock-rates = <100000000>, <100000000>; 930 931 phys = <&sata_phy0>; 932 phy-names = "sata-phy"; 933 ports-implemented = <0x1>; 934 }; 935 936 sdcc3: mmc@12180000 { 937 compatible = "arm,pl18x", "arm,primecell"; 938 arm,primecell-periphid = <0x00051180>; 939 status = "disabled"; 940 reg = <0x12180000 0x2000>; 941 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 943 clock-names = "mclk", "apb_pclk"; 944 bus-width = <4>; 945 cap-sd-highspeed; 946 cap-mmc-highspeed; 947 max-frequency = <192000000>; 948 no-1-8-v; 949 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 950 dma-names = "tx", "rx"; 951 }; 952 953 sdcc3bam: dma-controller@12182000 { 954 compatible = "qcom,bam-v1.3.0"; 955 reg = <0x12182000 0x8000>; 956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&gcc SDC3_H_CLK>; 958 clock-names = "bam_clk"; 959 #dma-cells = <1>; 960 qcom,ee = <0>; 961 }; 962 963 sdcc4: mmc@121c0000 { 964 compatible = "arm,pl18x", "arm,primecell"; 965 arm,primecell-periphid = <0x00051180>; 966 status = "disabled"; 967 reg = <0x121c0000 0x2000>; 968 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 970 clock-names = "mclk", "apb_pclk"; 971 bus-width = <4>; 972 cap-sd-highspeed; 973 cap-mmc-highspeed; 974 max-frequency = <48000000>; 975 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 976 dma-names = "tx", "rx"; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&sdc4_default_state>; 979 }; 980 981 sdcc4bam: dma-controller@121c2000 { 982 compatible = "qcom,bam-v1.3.0"; 983 reg = <0x121c2000 0x8000>; 984 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&gcc SDC4_H_CLK>; 986 clock-names = "bam_clk"; 987 #dma-cells = <1>; 988 qcom,ee = <0>; 989 }; 990 991 sdcc1: mmc@12400000 { 992 status = "disabled"; 993 compatible = "arm,pl18x", "arm,primecell"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&sdcc1_default_state>; 996 arm,primecell-periphid = <0x00051180>; 997 reg = <0x12400000 0x2000>; 998 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1000 clock-names = "mclk", "apb_pclk"; 1001 bus-width = <8>; 1002 max-frequency = <96000000>; 1003 non-removable; 1004 cap-sd-highspeed; 1005 cap-mmc-highspeed; 1006 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1007 dma-names = "tx", "rx"; 1008 }; 1009 1010 sdcc1bam: dma-controller@12402000 { 1011 compatible = "qcom,bam-v1.3.0"; 1012 reg = <0x12402000 0x8000>; 1013 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&gcc SDC1_H_CLK>; 1015 clock-names = "bam_clk"; 1016 #dma-cells = <1>; 1017 qcom,ee = <0>; 1018 }; 1019 1020 tcsr: syscon@1a400000 { 1021 compatible = "qcom,tcsr-apq8064", "syscon"; 1022 reg = <0x1a400000 0x100>; 1023 }; 1024 1025 gpu: gpu@4300000 { 1026 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1027 reg = <0x04300000 0x20000>; 1028 reg-names = "kgsl_3d0_reg_memory"; 1029 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "kgsl_3d0_irq"; 1031 clock-names = 1032 "core", 1033 "iface", 1034 "mem", 1035 "mem_iface"; 1036 clocks = 1037 <&mmcc GFX3D_CLK>, 1038 <&mmcc GFX3D_AHB_CLK>, 1039 <&mmcc GFX3D_AXI_CLK>, 1040 <&mmcc MMSS_IMEM_AHB_CLK>; 1041 1042 iommus = <&gfx3d 0 1043 &gfx3d 1 1044 &gfx3d 2 1045 &gfx3d 3 1046 &gfx3d 4 1047 &gfx3d 5 1048 &gfx3d 6 1049 &gfx3d 7 1050 &gfx3d 8 1051 &gfx3d 9 1052 &gfx3d 10 1053 &gfx3d 11 1054 &gfx3d 12 1055 &gfx3d 13 1056 &gfx3d 14 1057 &gfx3d 15 1058 &gfx3d 16 1059 &gfx3d 17 1060 &gfx3d 18 1061 &gfx3d 19 1062 &gfx3d 20 1063 &gfx3d 21 1064 &gfx3d 22 1065 &gfx3d 23 1066 &gfx3d 24 1067 &gfx3d 25 1068 &gfx3d 26 1069 &gfx3d 27 1070 &gfx3d 28 1071 &gfx3d 29 1072 &gfx3d 30 1073 &gfx3d 31 1074 &gfx3d1 0 1075 &gfx3d1 1 1076 &gfx3d1 2 1077 &gfx3d1 3 1078 &gfx3d1 4 1079 &gfx3d1 5 1080 &gfx3d1 6 1081 &gfx3d1 7 1082 &gfx3d1 8 1083 &gfx3d1 9 1084 &gfx3d1 10 1085 &gfx3d1 11 1086 &gfx3d1 12 1087 &gfx3d1 13 1088 &gfx3d1 14 1089 &gfx3d1 15 1090 &gfx3d1 16 1091 &gfx3d1 17 1092 &gfx3d1 18 1093 &gfx3d1 19 1094 &gfx3d1 20 1095 &gfx3d1 21 1096 &gfx3d1 22 1097 &gfx3d1 23 1098 &gfx3d1 24 1099 &gfx3d1 25 1100 &gfx3d1 26 1101 &gfx3d1 27 1102 &gfx3d1 28 1103 &gfx3d1 29 1104 &gfx3d1 30 1105 &gfx3d1 31>; 1106 1107 operating-points-v2 = <&gpu_opp_table>; 1108 1109 gpu_opp_table: opp-table { 1110 compatible = "operating-points-v2"; 1111 1112 opp-450000000 { 1113 opp-hz = /bits/ 64 <450000000>; 1114 }; 1115 1116 opp-27000000 { 1117 opp-hz = /bits/ 64 <27000000>; 1118 }; 1119 }; 1120 }; 1121 1122 mmss_sfpb: syscon@5700000 { 1123 compatible = "qcom,apq8064-mmss-sfpb", "syscon"; 1124 reg = <0x5700000 0x70>; 1125 }; 1126 1127 dsi0: dsi@4700000 { 1128 compatible = "qcom,apq8064-dsi-ctrl", 1129 "qcom,mdss-dsi-ctrl"; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1133 reg = <0x04700000 0x200>; 1134 reg-names = "dsi_ctrl"; 1135 1136 clocks = <&mmcc DSI_M_AHB_CLK>, 1137 <&mmcc DSI_S_AHB_CLK>, 1138 <&mmcc AMP_AHB_CLK>, 1139 <&mmcc DSI_CLK>, 1140 <&mmcc DSI1_BYTE_CLK>, 1141 <&mmcc DSI_PIXEL_CLK>, 1142 <&mmcc DSI1_ESC_CLK>; 1143 clock-names = "iface", "bus", "core_mmss", 1144 "src", "byte", "pixel", 1145 "core"; 1146 1147 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1148 <&mmcc DSI1_ESC_SRC>, 1149 <&mmcc DSI_SRC>, 1150 <&mmcc DSI_PIXEL_SRC>; 1151 assigned-clock-parents = <&dsi0_phy 0>, 1152 <&dsi0_phy 0>, 1153 <&dsi0_phy 1>, 1154 <&dsi0_phy 1>; 1155 syscon-sfpb = <&mmss_sfpb>; 1156 phys = <&dsi0_phy>; 1157 status = "disabled"; 1158 1159 ports { 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 port@0 { 1164 reg = <0>; 1165 dsi0_in: endpoint { 1166 }; 1167 }; 1168 1169 port@1 { 1170 reg = <1>; 1171 dsi0_out: endpoint { 1172 }; 1173 }; 1174 }; 1175 }; 1176 1177 1178 dsi0_phy: phy@4700200 { 1179 compatible = "qcom,dsi-phy-28nm-8960"; 1180 #clock-cells = <1>; 1181 #phy-cells = <0>; 1182 1183 reg = <0x04700200 0x100>, 1184 <0x04700300 0x200>, 1185 <0x04700500 0x5c>; 1186 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1187 clock-names = "iface", "ref"; 1188 clocks = <&mmcc DSI_M_AHB_CLK>, 1189 <&pxo_board>; 1190 status = "disabled"; 1191 }; 1192 1193 dsi1: dsi@5800000 { 1194 compatible = "qcom,mdss-dsi-ctrl"; 1195 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1196 reg = <0x05800000 0x200>; 1197 reg-names = "dsi_ctrl"; 1198 1199 clocks = <&mmcc DSI2_M_AHB_CLK>, 1200 <&mmcc DSI2_S_AHB_CLK>, 1201 <&mmcc AMP_AHB_CLK>, 1202 <&mmcc DSI2_CLK>, 1203 <&mmcc DSI2_BYTE_CLK>, 1204 <&mmcc DSI2_PIXEL_CLK>, 1205 <&mmcc DSI2_ESC_CLK>; 1206 clock-names = "iface", 1207 "bus", 1208 "core_mmss", 1209 "src", 1210 "byte", 1211 "pixel", 1212 "core"; 1213 1214 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1215 <&mmcc DSI2_ESC_SRC>, 1216 <&mmcc DSI2_SRC>, 1217 <&mmcc DSI2_PIXEL_SRC>; 1218 assigned-clock-parents = <&dsi1_phy 0>, 1219 <&dsi1_phy 0>, 1220 <&dsi1_phy 1>, 1221 <&dsi1_phy 1>; 1222 1223 syscon-sfpb = <&mmss_sfpb>; 1224 phys = <&dsi1_phy>; 1225 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 1229 status = "disabled"; 1230 1231 ports { 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 1235 port@0 { 1236 reg = <0>; 1237 dsi1_in: endpoint { 1238 }; 1239 }; 1240 1241 port@1 { 1242 reg = <1>; 1243 dsi1_out: endpoint { 1244 }; 1245 }; 1246 }; 1247 }; 1248 1249 1250 dsi1_phy: dsi-phy@5800200 { 1251 compatible = "qcom,dsi-phy-28nm-8960"; 1252 reg = <0x05800200 0x100>, 1253 <0x05800300 0x200>, 1254 <0x05800500 0x5c>; 1255 reg-names = "dsi_pll", 1256 "dsi_phy", 1257 "dsi_phy_regulator"; 1258 clock-names = "iface", 1259 "ref"; 1260 clocks = <&mmcc DSI2_M_AHB_CLK>, 1261 <&pxo_board>; 1262 #clock-cells = <1>; 1263 #phy-cells = <0>; 1264 1265 status = "disabled"; 1266 }; 1267 1268 mdp_port0: iommu@7500000 { 1269 compatible = "qcom,apq8064-iommu"; 1270 #iommu-cells = <1>; 1271 clock-names = 1272 "smmu_pclk", 1273 "iommu_clk"; 1274 clocks = 1275 <&mmcc SMMU_AHB_CLK>, 1276 <&mmcc MDP_AXI_CLK>; 1277 reg = <0x07500000 0x100000>; 1278 interrupts = 1279 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1281 qcom,ncb = <2>; 1282 }; 1283 1284 mdp_port1: iommu@7600000 { 1285 compatible = "qcom,apq8064-iommu"; 1286 #iommu-cells = <1>; 1287 clock-names = 1288 "smmu_pclk", 1289 "iommu_clk"; 1290 clocks = 1291 <&mmcc SMMU_AHB_CLK>, 1292 <&mmcc MDP_AXI_CLK>; 1293 reg = <0x07600000 0x100000>; 1294 interrupts = 1295 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1297 qcom,ncb = <2>; 1298 }; 1299 1300 gfx3d: iommu@7c00000 { 1301 compatible = "qcom,apq8064-iommu"; 1302 #iommu-cells = <1>; 1303 clock-names = 1304 "smmu_pclk", 1305 "iommu_clk"; 1306 clocks = 1307 <&mmcc SMMU_AHB_CLK>, 1308 <&mmcc GFX3D_AXI_CLK>; 1309 reg = <0x07c00000 0x100000>; 1310 interrupts = 1311 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1313 qcom,ncb = <3>; 1314 }; 1315 1316 gfx3d1: iommu@7d00000 { 1317 compatible = "qcom,apq8064-iommu"; 1318 #iommu-cells = <1>; 1319 clock-names = 1320 "smmu_pclk", 1321 "iommu_clk"; 1322 clocks = 1323 <&mmcc SMMU_AHB_CLK>, 1324 <&mmcc GFX3D_AXI_CLK>; 1325 reg = <0x07d00000 0x100000>; 1326 interrupts = 1327 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1329 qcom,ncb = <3>; 1330 }; 1331 1332 pcie: pcie@1b500000 { 1333 compatible = "qcom,pcie-apq8064"; 1334 reg = <0x1b500000 0x1000>, 1335 <0x1b502000 0x80>, 1336 <0x1b600000 0x100>, 1337 <0x0ff00000 0x100000>; 1338 reg-names = "dbi", "elbi", "parf", "config"; 1339 device_type = "pci"; 1340 linux,pci-domain = <0>; 1341 bus-range = <0x00 0xff>; 1342 num-lanes = <1>; 1343 #address-cells = <3>; 1344 #size-cells = <2>; 1345 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1346 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1347 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1348 interrupt-names = "msi"; 1349 #interrupt-cells = <1>; 1350 interrupt-map-mask = <0 0 0 0x7>; 1351 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1352 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1353 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1354 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1355 clocks = <&gcc PCIE_A_CLK>, 1356 <&gcc PCIE_H_CLK>, 1357 <&gcc PCIE_PHY_REF_CLK>; 1358 clock-names = "core", "iface", "phy"; 1359 resets = <&gcc PCIE_ACLK_RESET>, 1360 <&gcc PCIE_HCLK_RESET>, 1361 <&gcc PCIE_POR_RESET>, 1362 <&gcc PCIE_PCI_RESET>, 1363 <&gcc PCIE_PHY_RESET>; 1364 reset-names = "axi", "ahb", "por", "pci", "phy"; 1365 status = "disabled"; 1366 1367 pcie@0 { 1368 device_type = "pci"; 1369 reg = <0x0 0x0 0x0 0x0 0x0>; 1370 bus-range = <0x01 0xff>; 1371 1372 #address-cells = <3>; 1373 #size-cells = <2>; 1374 ranges; 1375 }; 1376 }; 1377 1378 hdmi: hdmi-tx@4a00000 { 1379 compatible = "qcom,hdmi-tx-8960"; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&hdmi_pinctrl>; 1382 reg = <0x04a00000 0x2f0>; 1383 reg-names = "core_physical"; 1384 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1385 clocks = <&mmcc HDMI_APP_CLK>, 1386 <&mmcc HDMI_M_AHB_CLK>, 1387 <&mmcc HDMI_S_AHB_CLK>; 1388 clock-names = "core", 1389 "master_iface", 1390 "slave_iface"; 1391 1392 phys = <&hdmi_phy>; 1393 1394 status = "disabled"; 1395 1396 ports { 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 1400 port@0 { 1401 reg = <0>; 1402 hdmi_in: endpoint { 1403 }; 1404 }; 1405 1406 port@1 { 1407 reg = <1>; 1408 hdmi_out: endpoint { 1409 }; 1410 }; 1411 }; 1412 }; 1413 1414 hdmi_phy: phy@4a00400 { 1415 compatible = "qcom,hdmi-phy-8960"; 1416 reg = <0x4a00400 0x60>, 1417 <0x4a00500 0x100>; 1418 reg-names = "hdmi_phy", 1419 "hdmi_pll"; 1420 1421 clocks = <&mmcc HDMI_S_AHB_CLK>; 1422 clock-names = "slave_iface"; 1423 #phy-cells = <0>; 1424 #clock-cells = <0>; 1425 1426 status = "disabled"; 1427 }; 1428 1429 mdp: display-controller@5100000 { 1430 compatible = "qcom,mdp4"; 1431 reg = <0x05100000 0xf0000>; 1432 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&mmcc MDP_CLK>, 1434 <&mmcc MDP_AHB_CLK>, 1435 <&mmcc MDP_AXI_CLK>, 1436 <&mmcc MDP_LUT_CLK>, 1437 <&mmcc HDMI_TV_CLK>, 1438 <&mmcc MDP_TV_CLK>; 1439 clock-names = "core_clk", 1440 "iface_clk", 1441 "bus_clk", 1442 "lut_clk", 1443 "hdmi_clk", 1444 "tv_clk"; 1445 1446 iommus = <&mdp_port0 0 1447 &mdp_port0 2 1448 &mdp_port1 0 1449 &mdp_port1 2>; 1450 1451 ports { 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 1455 port@0 { 1456 reg = <0>; 1457 mdp_lvds_out: endpoint { 1458 }; 1459 }; 1460 1461 port@1 { 1462 reg = <1>; 1463 mdp_dsi1_out: endpoint { 1464 }; 1465 }; 1466 1467 port@2 { 1468 reg = <2>; 1469 mdp_dsi2_out: endpoint { 1470 }; 1471 }; 1472 1473 port@3 { 1474 reg = <3>; 1475 mdp_dtv_out: endpoint { 1476 }; 1477 }; 1478 }; 1479 }; 1480 1481 riva: riva-pil@3200800 { 1482 compatible = "qcom,riva-pil"; 1483 1484 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1485 reg-names = "ccu", "dxe", "pmu"; 1486 1487 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1488 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1489 interrupt-names = "wdog", "fatal"; 1490 1491 memory-region = <&wcnss_mem>; 1492 1493 status = "disabled"; 1494 1495 iris { 1496 compatible = "qcom,wcn3660"; 1497 1498 clocks = <&cxo_board>; 1499 clock-names = "xo"; 1500 }; 1501 1502 smd-edge { 1503 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1504 1505 qcom,ipc = <&l2cc 8 25>; 1506 qcom,smd-edge = <6>; 1507 1508 label = "riva"; 1509 1510 wcnss { 1511 compatible = "qcom,wcnss"; 1512 qcom,smd-channels = "WCNSS_CTRL"; 1513 1514 qcom,mmio = <&riva>; 1515 1516 bluetooth { 1517 compatible = "qcom,wcnss-bt"; 1518 }; 1519 1520 wifi { 1521 compatible = "qcom,wcnss-wlan"; 1522 1523 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupt-names = "tx", "rx"; 1526 1527 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1528 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1529 }; 1530 }; 1531 }; 1532 }; 1533 1534 etb@1a01000 { 1535 compatible = "arm,coresight-etb10", "arm,primecell"; 1536 reg = <0x1a01000 0x1000>; 1537 1538 clocks = <&rpmcc RPM_QDSS_CLK>; 1539 clock-names = "apb_pclk"; 1540 1541 in-ports { 1542 port { 1543 etb_in: endpoint { 1544 remote-endpoint = <&replicator_out0>; 1545 }; 1546 }; 1547 }; 1548 }; 1549 1550 tpiu@1a03000 { 1551 compatible = "arm,coresight-tpiu", "arm,primecell"; 1552 reg = <0x1a03000 0x1000>; 1553 1554 clocks = <&rpmcc RPM_QDSS_CLK>; 1555 clock-names = "apb_pclk"; 1556 1557 in-ports { 1558 port { 1559 tpiu_in: endpoint { 1560 remote-endpoint = <&replicator_out1>; 1561 }; 1562 }; 1563 }; 1564 }; 1565 1566 funnel@1a04000 { 1567 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1568 reg = <0x1a04000 0x1000>; 1569 1570 clocks = <&rpmcc RPM_QDSS_CLK>; 1571 clock-names = "apb_pclk"; 1572 1573 in-ports { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 /* 1578 * Not described input ports: 1579 * 2 - connected to STM component 1580 * 3 - not-connected 1581 * 6 - not-connected 1582 * 7 - not-connected 1583 */ 1584 port@0 { 1585 reg = <0>; 1586 funnel_in0: endpoint { 1587 remote-endpoint = <&etm0_out>; 1588 }; 1589 }; 1590 port@1 { 1591 reg = <1>; 1592 funnel_in1: endpoint { 1593 remote-endpoint = <&etm1_out>; 1594 }; 1595 }; 1596 port@4 { 1597 reg = <4>; 1598 funnel_in4: endpoint { 1599 remote-endpoint = <&etm2_out>; 1600 }; 1601 }; 1602 port@5 { 1603 reg = <5>; 1604 funnel_in5: endpoint { 1605 remote-endpoint = <&etm3_out>; 1606 }; 1607 }; 1608 }; 1609 1610 out-ports { 1611 port { 1612 funnel_out: endpoint { 1613 remote-endpoint = <&replicator_in>; 1614 }; 1615 }; 1616 }; 1617 }; 1618 1619 etm@1a1c000 { 1620 compatible = "arm,coresight-etm3x", "arm,primecell"; 1621 reg = <0x1a1c000 0x1000>; 1622 1623 clocks = <&rpmcc RPM_QDSS_CLK>; 1624 clock-names = "apb_pclk"; 1625 1626 cpu = <&cpu0>; 1627 1628 out-ports { 1629 port { 1630 etm0_out: endpoint { 1631 remote-endpoint = <&funnel_in0>; 1632 }; 1633 }; 1634 }; 1635 }; 1636 1637 etm@1a1d000 { 1638 compatible = "arm,coresight-etm3x", "arm,primecell"; 1639 reg = <0x1a1d000 0x1000>; 1640 1641 clocks = <&rpmcc RPM_QDSS_CLK>; 1642 clock-names = "apb_pclk"; 1643 1644 cpu = <&cpu1>; 1645 1646 out-ports { 1647 port { 1648 etm1_out: endpoint { 1649 remote-endpoint = <&funnel_in1>; 1650 }; 1651 }; 1652 }; 1653 }; 1654 1655 etm@1a1e000 { 1656 compatible = "arm,coresight-etm3x", "arm,primecell"; 1657 reg = <0x1a1e000 0x1000>; 1658 1659 clocks = <&rpmcc RPM_QDSS_CLK>; 1660 clock-names = "apb_pclk"; 1661 1662 cpu = <&cpu2>; 1663 1664 out-ports { 1665 port { 1666 etm2_out: endpoint { 1667 remote-endpoint = <&funnel_in4>; 1668 }; 1669 }; 1670 }; 1671 }; 1672 1673 etm@1a1f000 { 1674 compatible = "arm,coresight-etm3x", "arm,primecell"; 1675 reg = <0x1a1f000 0x1000>; 1676 1677 clocks = <&rpmcc RPM_QDSS_CLK>; 1678 clock-names = "apb_pclk"; 1679 1680 cpu = <&cpu3>; 1681 1682 out-ports { 1683 port { 1684 etm3_out: endpoint { 1685 remote-endpoint = <&funnel_in5>; 1686 }; 1687 }; 1688 }; 1689 }; 1690 }; 1691}; 1692#include "qcom-apq8064-pins.dtsi" 1693