1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// 3// Copyright (C) 2016-2018 Zodiac Inflight Innovations 4 5/dts-v1/; 6#include "vf610.dtsi" 7 8/ { 9 model = "ZII VF610 SCU4 AIB"; 10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; 11 12 chosen { 13 stdout-path = &uart0; 14 }; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x20000000>; 19 }; 20 21 gpio-leds { 22 compatible = "gpio-leds"; 23 pinctrl-0 = <&pinctrl_leds_debug>; 24 pinctrl-names = "default"; 25 26 led-debug { 27 label = "zii:green:debug1"; 28 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 29 linux,default-trigger = "heartbeat"; 30 }; 31 }; 32 33 mdio-mux { 34 compatible = "mdio-mux-gpio"; 35 pinctrl-0 = <&pinctrl_mdio_mux>; 36 pinctrl-names = "default"; 37 gpios = <&gpio4 4 GPIO_ACTIVE_HIGH 38 &gpio4 5 GPIO_ACTIVE_HIGH 39 &gpio3 30 GPIO_ACTIVE_HIGH 40 &gpio3 31 GPIO_ACTIVE_HIGH>; 41 mdio-parent-bus = <&mdio1>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 mdio_mux_1: mdio@1 { 46 reg = <1>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 switch0: ethernet-switch@0 { 51 compatible = "marvell,mv88e6190"; 52 reg = <0>; 53 dsa,member = <0 0>; 54 eeprom-length = <65536>; 55 56 ethernet-ports { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 ethernet-port@0 { 61 reg = <0>; 62 phy-mode = "rmii"; 63 ethernet = <&fec1>; 64 65 fixed-link { 66 speed = <100>; 67 full-duplex; 68 }; 69 }; 70 71 ethernet-port@1 { 72 reg = <1>; 73 label = "aib2main_1"; 74 }; 75 76 ethernet-port@2 { 77 reg = <2>; 78 label = "aib2main_2"; 79 }; 80 81 ethernet-port@3 { 82 reg = <3>; 83 label = "eth_cu_1000_5"; 84 }; 85 86 ethernet-port@4 { 87 reg = <4>; 88 label = "eth_cu_1000_6"; 89 }; 90 91 ethernet-port@5 { 92 reg = <5>; 93 label = "eth_cu_1000_4"; 94 }; 95 96 ethernet-port@6 { 97 reg = <6>; 98 label = "eth_cu_1000_7"; 99 }; 100 101 ethernet-port@7 { 102 reg = <7>; 103 label = "modem_pic"; 104 105 fixed-link { 106 speed = <100>; 107 full-duplex; 108 }; 109 }; 110 111 switch0port10: ethernet-port@10 { 112 reg = <10>; 113 label = "dsa"; 114 phy-mode = "xgmii"; 115 link = <&switch1port10 116 &switch3port10 117 &switch2port10>; 118 119 fixed-link { 120 speed = <10000>; 121 full-duplex; 122 }; 123 }; 124 }; 125 }; 126 }; 127 128 mdio_mux_2: mdio@2 { 129 reg = <2>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 switch1: ethernet-switch@0 { 134 compatible = "marvell,mv88e6190"; 135 reg = <0>; 136 dsa,member = <0 1>; 137 eeprom-length = <65536>; 138 139 ethernet-ports { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 ethernet-port@1 { 144 reg = <1>; 145 label = "eth_cu_1000_3"; 146 }; 147 148 ethernet-port@2 { 149 reg = <2>; 150 label = "eth_cu_100_2"; 151 }; 152 153 ethernet-port@3 { 154 reg = <3>; 155 label = "eth_cu_100_3"; 156 }; 157 158 switch1port9: ethernet-port@9 { 159 reg = <9>; 160 label = "dsa"; 161 phy-mode = "xgmii"; 162 link = <&switch3port10 163 &switch2port10>; 164 165 fixed-link { 166 speed = <10000>; 167 full-duplex; 168 }; 169 }; 170 171 switch1port10: ethernet-port@10 { 172 reg = <10>; 173 label = "dsa"; 174 phy-mode = "xgmii"; 175 link = <&switch0port10>; 176 177 fixed-link { 178 speed = <10000>; 179 full-duplex; 180 }; 181 }; 182 }; 183 }; 184 }; 185 186 mdio_mux_4: mdio@4 { 187 reg = <4>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 switch2: ethernet-switch@0 { 192 compatible = "marvell,mv88e6190"; 193 reg = <0>; 194 dsa,member = <0 2>; 195 eeprom-length = <65536>; 196 197 ethernet-ports { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 ethernet-port@2 { 202 reg = <2>; 203 label = "eth_fc_1000_2"; 204 phy-mode = "1000base-x"; 205 managed = "in-band-status"; 206 sfp = <&sff1>; 207 }; 208 209 ethernet-port@3 { 210 reg = <3>; 211 label = "eth_fc_1000_3"; 212 phy-mode = "1000base-x"; 213 managed = "in-band-status"; 214 sfp = <&sff2>; 215 }; 216 217 ethernet-port@4 { 218 reg = <4>; 219 label = "eth_fc_1000_4"; 220 phy-mode = "1000base-x"; 221 managed = "in-band-status"; 222 sfp = <&sff3>; 223 }; 224 225 ethernet-port@5 { 226 reg = <5>; 227 label = "eth_fc_1000_5"; 228 phy-mode = "1000base-x"; 229 managed = "in-band-status"; 230 sfp = <&sff4>; 231 }; 232 233 ethernet-port@6 { 234 reg = <6>; 235 label = "eth_fc_1000_6"; 236 phy-mode = "1000base-x"; 237 managed = "in-band-status"; 238 sfp = <&sff5>; 239 }; 240 241 ethernet-port@7 { 242 reg = <7>; 243 label = "eth_fc_1000_7"; 244 phy-mode = "1000base-x"; 245 managed = "in-band-status"; 246 sfp = <&sff6>; 247 }; 248 249 ethernet-port@9 { 250 reg = <9>; 251 label = "eth_fc_1000_1"; 252 phy-mode = "1000base-x"; 253 managed = "in-band-status"; 254 sfp = <&sff0>; 255 }; 256 257 switch2port10: ethernet-port@10 { 258 reg = <10>; 259 label = "dsa"; 260 phy-mode = "2500base-x"; 261 link = <&switch3port9 262 &switch1port9 263 &switch0port10>; 264 265 fixed-link { 266 speed = <2500>; 267 full-duplex; 268 }; 269 }; 270 }; 271 }; 272 }; 273 274 mdio_mux_8: mdio@8 { 275 reg = <8>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 switch3: ethernet-switch@0 { 280 compatible = "marvell,mv88e6190"; 281 reg = <0>; 282 dsa,member = <0 3>; 283 eeprom-length = <65536>; 284 285 ethernet-ports { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 ethernet-port@2 { 290 reg = <2>; 291 label = "eth_fc_1000_8"; 292 phy-mode = "1000base-x"; 293 managed = "in-band-status"; 294 sfp = <&sff7>; 295 }; 296 297 ethernet-port@3 { 298 reg = <3>; 299 label = "eth_fc_1000_9"; 300 phy-mode = "1000base-x"; 301 managed = "in-band-status"; 302 sfp = <&sff8>; 303 }; 304 305 ethernet-port@4 { 306 reg = <4>; 307 label = "eth_fc_1000_10"; 308 phy-mode = "1000base-x"; 309 managed = "in-band-status"; 310 sfp = <&sff9>; 311 }; 312 313 switch3port9: ethernet-port@9 { 314 reg = <9>; 315 label = "dsa"; 316 phy-mode = "2500base-x"; 317 link = <&switch2port10>; 318 319 fixed-link { 320 speed = <2500>; 321 full-duplex; 322 }; 323 }; 324 325 switch3port10: ethernet-port@10 { 326 reg = <10>; 327 label = "dsa"; 328 phy-mode = "xgmii"; 329 link = <&switch1port9 330 &switch0port10>; 331 332 fixed-link { 333 speed = <10000>; 334 full-duplex; 335 }; 336 }; 337 }; 338 }; 339 }; 340 }; 341 342 sff0: sff0 { 343 compatible = "sff,sff"; 344 i2c-bus = <&sff0_i2c>; 345 los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; 346 tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 347 }; 348 349 sff1: sff1 { 350 compatible = "sff,sff"; 351 i2c-bus = <&sff1_i2c>; 352 los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; 353 tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 354 }; 355 356 sff2: sff2 { 357 compatible = "sff,sff"; 358 i2c-bus = <&sff2_i2c>; 359 los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; 360 tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 361 }; 362 363 sff3: sff3 { 364 compatible = "sff,sff"; 365 i2c-bus = <&sff3_i2c>; 366 los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; 367 tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; 368 }; 369 370 sff4: sff4 { 371 compatible = "sff,sff"; 372 i2c-bus = <&sff4_i2c>; 373 los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; 374 tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; 375 }; 376 377 sff5: sff5 { 378 compatible = "sff,sff"; 379 i2c-bus = <&sff5_i2c>; 380 los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; 381 tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; 382 }; 383 384 sff6: sff6 { 385 compatible = "sff,sff"; 386 i2c-bus = <&sff6_i2c>; 387 los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; 388 tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; 389 }; 390 391 sff7: sff7 { 392 compatible = "sff,sff"; 393 i2c-bus = <&sff7_i2c>; 394 los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; 395 tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; 396 }; 397 398 sff8: sff8 { 399 compatible = "sff,sff"; 400 i2c-bus = <&sff8_i2c>; 401 los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; 402 tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; 403 }; 404 405 sff9: sff9 { 406 compatible = "sff,sff"; 407 i2c-bus = <&sff9_i2c>; 408 los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; 409 tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; 410 }; 411 412 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { 413 compatible = "regulator-fixed"; 414 regulator-name = "vcc_3v3_mcu"; 415 regulator-min-microvolt = <3300000>; 416 regulator-max-microvolt = <3300000>; 417 }; 418}; 419 420&dspi0 { 421 pinctrl-0 = <&pinctrl_dspi0>; 422 pinctrl-names = "default"; 423 bus-num = <0>; 424 status = "okay"; 425 426 adc@5 { 427 compatible = "holt,hi8435"; 428 reg = <5>; 429 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 430 spi-max-frequency = <1000000>; 431 }; 432}; 433 434&dspi1 { 435 bus-num = <1>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pinctrl_dspi1>; 438 status = "okay"; 439 440 flash@0 { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 compatible = "jedec,spi-nor"; 444 reg = <0>; 445 spi-max-frequency = <50000000>; 446 447 partition@0 { 448 label = "m25p128-0"; 449 reg = <0x0 0x01000000>; 450 }; 451 }; 452 453 flash@1 { 454 #address-cells = <1>; 455 #size-cells = <1>; 456 compatible = "jedec,spi-nor"; 457 reg = <1>; 458 spi-max-frequency = <50000000>; 459 460 partition@0 { 461 label = "m25p128-1"; 462 reg = <0x0 0x01000000>; 463 }; 464 }; 465}; 466 467&adc0 { 468 vref-supply = <®_vcc_3v3_mcu>; 469 status = "okay"; 470}; 471 472&adc1 { 473 vref-supply = <®_vcc_3v3_mcu>; 474 status = "okay"; 475}; 476 477&edma0 { 478 status = "okay"; 479}; 480 481&edma1 { 482 status = "okay"; 483}; 484 485&esdhc0 { 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_esdhc0>; 488 bus-width = <8>; 489 non-removable; 490 no-1-8-v; 491 no-sd; 492 no-sdio; 493 keep-power-in-suspend; 494 status = "okay"; 495}; 496 497&esdhc1 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_esdhc1>; 500 bus-width = <4>; 501 no-sdio; 502 status = "okay"; 503}; 504 505&fec1 { 506 phy-mode = "rmii"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_fec1>; 509 status = "okay"; 510 511 fixed-link { 512 speed = <100>; 513 full-duplex; 514 }; 515 516 mdio1: mdio { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 }; 520}; 521 522&i2c0 { 523 clock-frequency = <100000>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_i2c0>; 526 status = "okay"; 527 528 gpio5: io-expander@20 { 529 compatible = "nxp,pca9554"; 530 reg = <0x20>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 }; 534 535 gpio6: io-expander@22 { 536 compatible = "nxp,pca9554"; 537 reg = <0x22>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 }; 541 542 temp-sensor@48 { 543 compatible = "national,lm75"; 544 reg = <0x48>; 545 }; 546 547 eeprom@50 { 548 compatible = "atmel,24c04"; 549 reg = <0x50>; 550 }; 551 552 eeprom@52 { 553 compatible = "atmel,24c04"; 554 reg = <0x52>; 555 }; 556 557 elapsed-time-recorder@6b { 558 compatible = "dallas,ds1682"; 559 reg = <0x6b>; 560 }; 561}; 562 563&i2c1 { 564 clock-frequency = <100000>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_i2c1>; 567 status = "okay"; 568 569 watchdog@38 { 570 compatible = "zii,rave-wdt"; 571 reg = <0x38>; 572 }; 573 574 adc@4a { 575 compatible = "adi,adt7411"; 576 reg = <0x4a>; 577 }; 578}; 579 580&i2c2 { 581 clock-frequency = <100000>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_i2c2>; 584 status = "okay"; 585 586 gpio9: pinctrl@20 { 587 compatible = "semtech,sx1503q"; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_sx1503_20>; 590 #gpio-cells = <2>; 591 reg = <0x20>; 592 gpio-controller; 593 interrupt-parent = <&gpio1>; 594 interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 595 }; 596 597 temp-sensor@4e { 598 compatible = "national,lm75"; 599 reg = <0x4e>; 600 }; 601 602 temp-sensor@4f { 603 compatible = "national,lm75"; 604 reg = <0x4f>; 605 }; 606 607 gpio7: io-expander@23 { 608 compatible = "nxp,pca9555"; 609 gpio-controller; 610 #gpio-cells = <2>; 611 reg = <0x23>; 612 }; 613 614 adc@4a { 615 compatible = "adi,adt7411"; 616 reg = <0x4a>; 617 }; 618 619 eeprom@54 { 620 compatible = "atmel,24c08"; 621 reg = <0x54>; 622 }; 623 624 i2c-mux@70 { 625 compatible = "nxp,pca9548"; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 reg = <0x70>; 629 i2c-mux-idle-disconnect; 630 631 sff0_i2c: i2c@1 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <1>; 635 }; 636 637 sff1_i2c: i2c@2 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 reg = <2>; 641 }; 642 643 sff2_i2c: i2c@3 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 reg = <3>; 647 }; 648 649 sff3_i2c: i2c@4 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <4>; 653 }; 654 655 sff4_i2c: i2c@5 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 reg = <5>; 659 }; 660 }; 661 662 i2c-mux@71 { 663 compatible = "nxp,pca9548"; 664 reg = <0x71>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 i2c-mux-idle-disconnect; 668 669 sff5_i2c: i2c@1 { 670 #address-cells = <1>; 671 #size-cells = <0>; 672 reg = <1>; 673 }; 674 675 sff6_i2c: i2c@2 { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 reg = <2>; 679 }; 680 681 sff7_i2c: i2c@3 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 reg = <3>; 685 }; 686 687 sff8_i2c: i2c@4 { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 reg = <4>; 691 }; 692 693 sff9_i2c: i2c@5 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 reg = <5>; 697 }; 698 }; 699}; 700 701&snvsrtc { 702 status = "disabled"; 703}; 704 705&uart0 { 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_uart0>; 708 status = "okay"; 709}; 710 711&uart1 { 712 linux,rs485-enabled-at-boot-time; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_uart1>; 715 status = "okay"; 716}; 717 718&uart2 { 719 linux,rs485-enabled-at-boot-time; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&pinctrl_uart2>; 722 status = "okay"; 723}; 724 725&iomuxc { 726 pinctrl_dspi0: dspi0grp { 727 fsl,pins = < 728 VF610_PAD_PTB19__DSPI0_CS0 0x1182 729 VF610_PAD_PTB18__DSPI0_CS1 0x1182 730 VF610_PAD_PTB13__DSPI0_CS4 0x1182 731 VF610_PAD_PTB12__DSPI0_CS5 0x1182 732 VF610_PAD_PTB20__DSPI0_SIN 0x1181 733 VF610_PAD_PTB21__DSPI0_SOUT 0x1182 734 VF610_PAD_PTB22__DSPI0_SCK 0x1182 735 >; 736 }; 737 738 pinctrl_dspi1: dspi1grp { 739 fsl,pins = < 740 VF610_PAD_PTD5__DSPI1_CS0 0x1182 741 VF610_PAD_PTD4__DSPI1_CS1 0x1182 742 VF610_PAD_PTC6__DSPI1_SIN 0x1181 743 VF610_PAD_PTC7__DSPI1_SOUT 0x1182 744 VF610_PAD_PTC8__DSPI1_SCK 0x1182 745 >; 746 }; 747 748 pinctrl_dspi2: dspi2gpiogrp { 749 fsl,pins = < 750 VF610_PAD_PTD30__GPIO_64 0x33e2 751 VF610_PAD_PTD29__GPIO_65 0x33e1 752 VF610_PAD_PTD28__GPIO_66 0x33e2 753 VF610_PAD_PTD27__GPIO_67 0x33e2 754 VF610_PAD_PTD26__GPIO_68 0x31c2 755 >; 756 }; 757 758 pinctrl_esdhc0: esdhc0grp { 759 fsl,pins = < 760 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef 761 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef 762 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef 763 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef 764 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef 765 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef 766 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef 767 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef 768 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef 769 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef 770 >; 771 }; 772 773 pinctrl_esdhc1: esdhc1grp { 774 fsl,pins = < 775 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 776 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 777 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 778 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 779 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 780 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 781 >; 782 }; 783 784 pinctrl_fec1: fec1grp { 785 fsl,pins = < 786 VF610_PAD_PTA6__RMII_CLKIN 0x30d1 787 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 788 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 789 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 790 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 791 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 792 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 793 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 794 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 795 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 796 >; 797 }; 798 799 pinctrl_i2c0: i2c0grp { 800 fsl,pins = < 801 VF610_PAD_PTB14__I2C0_SCL 0x37ff 802 VF610_PAD_PTB15__I2C0_SDA 0x37ff 803 >; 804 }; 805 806 pinctrl_i2c1: i2c1grp { 807 fsl,pins = < 808 VF610_PAD_PTB16__I2C1_SCL 0x37ff 809 VF610_PAD_PTB17__I2C1_SDA 0x37ff 810 >; 811 }; 812 813 pinctrl_i2c2: i2c2grp { 814 fsl,pins = < 815 VF610_PAD_PTA22__I2C2_SCL 0x37ff 816 VF610_PAD_PTA23__I2C2_SDA 0x37ff 817 >; 818 }; 819 820 pinctrl_leds_debug: pinctrl-leds-debuggrp { 821 fsl,pins = < 822 VF610_PAD_PTB26__GPIO_96 0x31c2 823 >; 824 }; 825 826 pinctrl_mdio_mux: pinctrl-mdio-muxgrp { 827 fsl,pins = < 828 VF610_PAD_PTE27__GPIO_132 0x31c2 829 VF610_PAD_PTE28__GPIO_133 0x31c2 830 VF610_PAD_PTE21__GPIO_126 0x31c2 831 VF610_PAD_PTE22__GPIO_127 0x31c2 832 >; 833 }; 834 835 pinctrl_qspi0: qspi0grp { 836 fsl,pins = < 837 VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 838 VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff 839 VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 840 VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 841 VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 842 VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 843 >; 844 }; 845 846 pinctrl_sx1503_20: pinctrl-sx1503-20grp { 847 fsl,pins = < 848 VF610_PAD_PTD31__GPIO_63 0x219d 849 >; 850 }; 851 852 pinctrl_uart0: uart0grp { 853 fsl,pins = < 854 VF610_PAD_PTB10__UART0_TX 0x21a2 855 VF610_PAD_PTB11__UART0_RX 0x21a1 856 >; 857 }; 858 859 pinctrl_uart1: uart1grp { 860 fsl,pins = < 861 VF610_PAD_PTB23__UART1_TX 0x21a2 862 VF610_PAD_PTB24__UART1_RX 0x21a1 863 VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ 864 >; 865 }; 866 867 pinctrl_uart2: uart2grp { 868 fsl,pins = < 869 VF610_PAD_PTD0__UART2_TX 0x21a2 870 VF610_PAD_PTD1__UART2_RX 0x21a1 871 VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ 872 >; 873 }; 874}; 875