1f496e675SAndrey Smirnov// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2f496e675SAndrey Smirnov/* 3f496e675SAndrey Smirnov * Device tree file for ZII's RMU2 board 4f496e675SAndrey Smirnov * 5f496e675SAndrey Smirnov * RMU - Remote Modem Unit 6f496e675SAndrey Smirnov * 7f496e675SAndrey Smirnov * Copyright (C) 2019 Zodiac Inflight Innovations 8f496e675SAndrey Smirnov */ 9f496e675SAndrey Smirnov 10f496e675SAndrey Smirnov/dts-v1/; 11f496e675SAndrey Smirnov#include <dt-bindings/thermal/thermal.h> 12f496e675SAndrey Smirnov#include "imx7d.dtsi" 13f496e675SAndrey Smirnov 14f496e675SAndrey Smirnov/ { 15f496e675SAndrey Smirnov model = "ZII RMU2 Board"; 16f496e675SAndrey Smirnov compatible = "zii,imx7d-rmu2", "fsl,imx7d"; 17f496e675SAndrey Smirnov 18f496e675SAndrey Smirnov chosen { 19f496e675SAndrey Smirnov stdout-path = &uart2; 20f496e675SAndrey Smirnov }; 21f496e675SAndrey Smirnov 22f496e675SAndrey Smirnov gpio-leds { 23f496e675SAndrey Smirnov compatible = "gpio-leds"; 24f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_leds_debug>; 25f496e675SAndrey Smirnov pinctrl-names = "default"; 26f496e675SAndrey Smirnov 271bad8bcaSKrzysztof Kozlowski led-debug { 28f496e675SAndrey Smirnov label = "zii:green:debug1"; 29f496e675SAndrey Smirnov gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 30f496e675SAndrey Smirnov linux,default-trigger = "heartbeat"; 31f496e675SAndrey Smirnov }; 32f496e675SAndrey Smirnov }; 33f496e675SAndrey Smirnov}; 34f496e675SAndrey Smirnov 35f496e675SAndrey Smirnov&cpu0 { 36f2e3d666SAnson Huang cpu-supply = <&sw1a_reg>; 37f496e675SAndrey Smirnov}; 38f496e675SAndrey Smirnov 39f496e675SAndrey Smirnov&ecspi1 { 40f496e675SAndrey Smirnov pinctrl-names = "default"; 41f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_ecspi1>; 422bfdd113SFabio Estevam cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 43f496e675SAndrey Smirnov status = "okay"; 44f496e675SAndrey Smirnov 45f496e675SAndrey Smirnov flash@0 { 46f496e675SAndrey Smirnov compatible = "jedec,spi-nor"; 47f496e675SAndrey Smirnov spi-max-frequency = <20000000>; 48f496e675SAndrey Smirnov reg = <0>; 49f496e675SAndrey Smirnov #address-cells = <1>; 50f496e675SAndrey Smirnov #size-cells = <1>; 51f496e675SAndrey Smirnov }; 52f496e675SAndrey Smirnov}; 53f496e675SAndrey Smirnov 54f496e675SAndrey Smirnov&fec1 { 55f496e675SAndrey Smirnov pinctrl-names = "default"; 56f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_enet1>; 57f496e675SAndrey Smirnov assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 58f496e675SAndrey Smirnov <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 59f496e675SAndrey Smirnov assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 60f496e675SAndrey Smirnov assigned-clock-rates = <0>, <100000000>; 615cbb80d5SChris Healy phy-mode = "rgmii-id"; 62f496e675SAndrey Smirnov phy-handle = <&fec1_phy>; 63f496e675SAndrey Smirnov status = "okay"; 64f496e675SAndrey Smirnov 65f496e675SAndrey Smirnov mdio { 66f496e675SAndrey Smirnov #address-cells = <1>; 67f496e675SAndrey Smirnov #size-cells = <0>; 68f496e675SAndrey Smirnov 69f496e675SAndrey Smirnov fec1_phy: ethernet-phy@0 { 70f496e675SAndrey Smirnov pinctrl-names = "default"; 71f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_enet1_phy_reset>, 72f496e675SAndrey Smirnov <&pinctrl_enet1_phy_interrupt>; 73f496e675SAndrey Smirnov reg = <0>; 74f496e675SAndrey Smirnov interrupt-parent = <&gpio1>; 75f496e675SAndrey Smirnov interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 76f496e675SAndrey Smirnov reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 77f496e675SAndrey Smirnov }; 78f496e675SAndrey Smirnov }; 79f496e675SAndrey Smirnov}; 80f496e675SAndrey Smirnov 81f496e675SAndrey Smirnov&i2c1 { 82f496e675SAndrey Smirnov clock-frequency = <100000>; 83f496e675SAndrey Smirnov pinctrl-names = "default"; 84f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_i2c1>; 85f496e675SAndrey Smirnov status = "okay"; 86f496e675SAndrey Smirnov 87f496e675SAndrey Smirnov pmic@8 { 88f496e675SAndrey Smirnov compatible = "fsl,pfuze3000"; 89f496e675SAndrey Smirnov reg = <0x08>; 90f496e675SAndrey Smirnov 91f496e675SAndrey Smirnov regulators { 92f496e675SAndrey Smirnov sw1a_reg: sw1a { 93f496e675SAndrey Smirnov regulator-min-microvolt = <700000>; 94f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 95f496e675SAndrey Smirnov regulator-boot-on; 96f496e675SAndrey Smirnov regulator-always-on; 97f496e675SAndrey Smirnov regulator-ramp-delay = <6250>; 98f496e675SAndrey Smirnov }; 99f496e675SAndrey Smirnov 100f496e675SAndrey Smirnov sw1c_reg: sw1b { 101f496e675SAndrey Smirnov regulator-min-microvolt = <700000>; 102f496e675SAndrey Smirnov regulator-max-microvolt = <1475000>; 103f496e675SAndrey Smirnov regulator-boot-on; 104f496e675SAndrey Smirnov regulator-always-on; 105f496e675SAndrey Smirnov regulator-ramp-delay = <6250>; 106f496e675SAndrey Smirnov }; 107f496e675SAndrey Smirnov 108f496e675SAndrey Smirnov sw2_reg: sw2 { 109f496e675SAndrey Smirnov regulator-min-microvolt = <1500000>; 110f496e675SAndrey Smirnov regulator-max-microvolt = <1850000>; 111f496e675SAndrey Smirnov regulator-boot-on; 112f496e675SAndrey Smirnov regulator-always-on; 113f496e675SAndrey Smirnov }; 114f496e675SAndrey Smirnov 115f496e675SAndrey Smirnov sw3a_reg: sw3 { 116f496e675SAndrey Smirnov regulator-min-microvolt = <900000>; 117f496e675SAndrey Smirnov regulator-max-microvolt = <1650000>; 118f496e675SAndrey Smirnov regulator-boot-on; 119f496e675SAndrey Smirnov regulator-always-on; 120f496e675SAndrey Smirnov }; 121f496e675SAndrey Smirnov 122f496e675SAndrey Smirnov swbst_reg: swbst { 123f496e675SAndrey Smirnov regulator-min-microvolt = <5000000>; 124f496e675SAndrey Smirnov regulator-max-microvolt = <5150000>; 125f496e675SAndrey Smirnov }; 126f496e675SAndrey Smirnov 127f496e675SAndrey Smirnov snvs_reg: vsnvs { 128f496e675SAndrey Smirnov regulator-min-microvolt = <1000000>; 129f496e675SAndrey Smirnov regulator-max-microvolt = <3000000>; 130f496e675SAndrey Smirnov regulator-boot-on; 131f496e675SAndrey Smirnov regulator-always-on; 132f496e675SAndrey Smirnov }; 133f496e675SAndrey Smirnov 134f496e675SAndrey Smirnov vref_reg: vrefddr { 135f496e675SAndrey Smirnov regulator-boot-on; 136f496e675SAndrey Smirnov regulator-always-on; 137f496e675SAndrey Smirnov }; 138f496e675SAndrey Smirnov 139f496e675SAndrey Smirnov vgen1_reg: vldo1 { 140f496e675SAndrey Smirnov regulator-min-microvolt = <1800000>; 141f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 142f496e675SAndrey Smirnov regulator-always-on; 143f496e675SAndrey Smirnov }; 144f496e675SAndrey Smirnov 145f496e675SAndrey Smirnov vgen2_reg: vldo2 { 146f496e675SAndrey Smirnov regulator-min-microvolt = <800000>; 147f496e675SAndrey Smirnov regulator-max-microvolt = <1550000>; 148f496e675SAndrey Smirnov regulator-always-on; 149f496e675SAndrey Smirnov }; 150f496e675SAndrey Smirnov 151f496e675SAndrey Smirnov vgen3_reg: vccsd { 152f496e675SAndrey Smirnov regulator-min-microvolt = <2850000>; 153f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 154f496e675SAndrey Smirnov regulator-always-on; 155f496e675SAndrey Smirnov }; 156f496e675SAndrey Smirnov 157f496e675SAndrey Smirnov vgen4_reg: v33 { 158f496e675SAndrey Smirnov regulator-min-microvolt = <2850000>; 159f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 160f496e675SAndrey Smirnov regulator-always-on; 161f496e675SAndrey Smirnov }; 162f496e675SAndrey Smirnov 163f496e675SAndrey Smirnov vgen5_reg: vldo3 { 164f496e675SAndrey Smirnov regulator-min-microvolt = <1800000>; 165f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 166f496e675SAndrey Smirnov regulator-always-on; 167f496e675SAndrey Smirnov }; 168f496e675SAndrey Smirnov 169f496e675SAndrey Smirnov vgen6_reg: vldo4 { 170f496e675SAndrey Smirnov regulator-min-microvolt = <1800000>; 171f496e675SAndrey Smirnov regulator-max-microvolt = <3300000>; 172f496e675SAndrey Smirnov regulator-always-on; 173f496e675SAndrey Smirnov }; 174f496e675SAndrey Smirnov }; 175f496e675SAndrey Smirnov }; 176f496e675SAndrey Smirnov 177f496e675SAndrey Smirnov eeprom@50 { 178f496e675SAndrey Smirnov compatible = "atmel,24c04"; 179f496e675SAndrey Smirnov reg = <0x50>; 180f496e675SAndrey Smirnov }; 181f496e675SAndrey Smirnov 182f496e675SAndrey Smirnov eeprom@52 { 183f496e675SAndrey Smirnov compatible = "atmel,24c04"; 184f496e675SAndrey Smirnov reg = <0x52>; 185f496e675SAndrey Smirnov }; 186f496e675SAndrey Smirnov}; 187f496e675SAndrey Smirnov 188f496e675SAndrey Smirnov&snvs_rtc { 189f496e675SAndrey Smirnov status = "disabled"; 190f496e675SAndrey Smirnov}; 191f496e675SAndrey Smirnov 192f496e675SAndrey Smirnov&uart2 { 193f496e675SAndrey Smirnov pinctrl-names = "default"; 194f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_uart2>; 195f496e675SAndrey Smirnov assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; 196f496e675SAndrey Smirnov assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; 197f496e675SAndrey Smirnov status = "okay"; 198f496e675SAndrey Smirnov}; 199f496e675SAndrey Smirnov 200f496e675SAndrey Smirnov&uart4 { 201f496e675SAndrey Smirnov pinctrl-names = "default"; 202f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_uart4>; 203f496e675SAndrey Smirnov assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; 204f496e675SAndrey Smirnov assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 205f496e675SAndrey Smirnov status = "okay"; 206f496e675SAndrey Smirnov 20766bd7a30SKrzysztof Kozlowski mcu { 208f496e675SAndrey Smirnov compatible = "zii,rave-sp-rdu2"; 209f496e675SAndrey Smirnov current-speed = <1000000>; 210f496e675SAndrey Smirnov #address-cells = <1>; 211f496e675SAndrey Smirnov #size-cells = <1>; 212f496e675SAndrey Smirnov 213f496e675SAndrey Smirnov watchdog { 214f496e675SAndrey Smirnov compatible = "zii,rave-sp-watchdog"; 215f496e675SAndrey Smirnov }; 216f496e675SAndrey Smirnov 217f496e675SAndrey Smirnov eeprom@a3 { 218f496e675SAndrey Smirnov compatible = "zii,rave-sp-eeprom"; 219f496e675SAndrey Smirnov reg = <0xa3 0x4000>; 220f496e675SAndrey Smirnov #address-cells = <1>; 221f496e675SAndrey Smirnov #size-cells = <1>; 222f496e675SAndrey Smirnov zii,eeprom-name = "main-eeprom"; 223f496e675SAndrey Smirnov }; 224f496e675SAndrey Smirnov }; 225f496e675SAndrey Smirnov}; 226f496e675SAndrey Smirnov 227f496e675SAndrey Smirnov&usbotg2 { 228f496e675SAndrey Smirnov dr_mode = "host"; 229f496e675SAndrey Smirnov disable-over-current; 230f496e675SAndrey Smirnov status = "okay"; 231f496e675SAndrey Smirnov}; 232f496e675SAndrey Smirnov 233f496e675SAndrey Smirnov&usdhc1 { 234f496e675SAndrey Smirnov pinctrl-names = "default"; 235f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_usdhc1>; 236f496e675SAndrey Smirnov bus-width = <4>; 237f496e675SAndrey Smirnov no-1-8-v; 238f496e675SAndrey Smirnov no-sdio; 239f496e675SAndrey Smirnov keep-power-in-suspend; 240f496e675SAndrey Smirnov status = "okay"; 241f496e675SAndrey Smirnov}; 242f496e675SAndrey Smirnov 243f496e675SAndrey Smirnov&usdhc3 { 244f496e675SAndrey Smirnov pinctrl-names = "default"; 245f496e675SAndrey Smirnov pinctrl-0 = <&pinctrl_usdhc3>; 246f496e675SAndrey Smirnov bus-width = <8>; 247f496e675SAndrey Smirnov no-1-8-v; 248f496e675SAndrey Smirnov non-removable; 249f496e675SAndrey Smirnov no-sdio; 250f496e675SAndrey Smirnov no-sd; 251f496e675SAndrey Smirnov keep-power-in-suspend; 252f496e675SAndrey Smirnov status = "okay"; 253f496e675SAndrey Smirnov}; 254f496e675SAndrey Smirnov 255f496e675SAndrey Smirnov&wdog1 { 256f496e675SAndrey Smirnov status = "disabled"; 257f496e675SAndrey Smirnov}; 258f496e675SAndrey Smirnov 259f496e675SAndrey Smirnov&iomuxc { 260f496e675SAndrey Smirnov pinctrl_ecspi1: ecspi1grp { 261f496e675SAndrey Smirnov fsl,pins = < 262f496e675SAndrey Smirnov MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 263f496e675SAndrey Smirnov MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 264f496e675SAndrey Smirnov MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 265f496e675SAndrey Smirnov MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 266f496e675SAndrey Smirnov >; 267f496e675SAndrey Smirnov }; 268f496e675SAndrey Smirnov 269f496e675SAndrey Smirnov pinctrl_enet1: enet1grp { 270f496e675SAndrey Smirnov fsl,pins = < 271f496e675SAndrey Smirnov MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 272f496e675SAndrey Smirnov MX7D_PAD_SD2_WP__ENET1_MDC 0x3 273f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 274f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 275f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 276f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 277f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 278f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 279f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 280f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 281f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 282f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 283f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 284f496e675SAndrey Smirnov MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 285f496e675SAndrey Smirnov >; 286f496e675SAndrey Smirnov }; 287f496e675SAndrey Smirnov 288f496e675SAndrey Smirnov pinctrl_enet1_phy_reset: enet1phyresetgrp { 289f496e675SAndrey Smirnov fsl,pins = < 290f496e675SAndrey Smirnov MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 291f496e675SAndrey Smirnov 292f496e675SAndrey Smirnov >; 293f496e675SAndrey Smirnov }; 294f496e675SAndrey Smirnov 295f496e675SAndrey Smirnov pinctrl_i2c1: i2c1grp { 296f496e675SAndrey Smirnov fsl,pins = < 297f496e675SAndrey Smirnov MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 298f496e675SAndrey Smirnov MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 299f496e675SAndrey Smirnov >; 300f496e675SAndrey Smirnov }; 301f496e675SAndrey Smirnov 302f496e675SAndrey Smirnov pinctrl_leds_debug: ledsgrp { 303f496e675SAndrey Smirnov fsl,pins = < 304f496e675SAndrey Smirnov MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 305f496e675SAndrey Smirnov >; 306f496e675SAndrey Smirnov }; 307f496e675SAndrey Smirnov 308f496e675SAndrey Smirnov 309f496e675SAndrey Smirnov pinctrl_uart2: uart2grp { 310f496e675SAndrey Smirnov fsl,pins = < 311f496e675SAndrey Smirnov MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 312f496e675SAndrey Smirnov MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 313f496e675SAndrey Smirnov >; 314f496e675SAndrey Smirnov }; 315f496e675SAndrey Smirnov 316f496e675SAndrey Smirnov pinctrl_uart4: uart4grp { 317f496e675SAndrey Smirnov fsl,pins = < 318f496e675SAndrey Smirnov MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 319f496e675SAndrey Smirnov MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 320f496e675SAndrey Smirnov >; 321f496e675SAndrey Smirnov }; 322f496e675SAndrey Smirnov 323f496e675SAndrey Smirnov pinctrl_usdhc1: usdhc1grp { 324f496e675SAndrey Smirnov fsl,pins = < 325f496e675SAndrey Smirnov MX7D_PAD_SD1_CMD__SD1_CMD 0x59 326f496e675SAndrey Smirnov MX7D_PAD_SD1_CLK__SD1_CLK 0x19 327f496e675SAndrey Smirnov MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 328f496e675SAndrey Smirnov MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 329f496e675SAndrey Smirnov MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 330f496e675SAndrey Smirnov MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 331f496e675SAndrey Smirnov >; 332f496e675SAndrey Smirnov }; 333f496e675SAndrey Smirnov 334f496e675SAndrey Smirnov pinctrl_usdhc3: usdhc3grp { 335f496e675SAndrey Smirnov fsl,pins = < 336f496e675SAndrey Smirnov MX7D_PAD_SD3_CMD__SD3_CMD 0x59 337f496e675SAndrey Smirnov MX7D_PAD_SD3_CLK__SD3_CLK 0x19 338f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 339f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 340f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 341f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 342f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 343f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 344f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 345f496e675SAndrey Smirnov MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 346f496e675SAndrey Smirnov MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 347f496e675SAndrey Smirnov >; 348f496e675SAndrey Smirnov }; 349f496e675SAndrey Smirnov}; 350f496e675SAndrey Smirnov 351f496e675SAndrey Smirnov&iomuxc_lpsr { 352f496e675SAndrey Smirnov pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp { 3530e49cfe3SKrzysztof Kozlowski fsl,pins = < 354f496e675SAndrey Smirnov MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 355f496e675SAndrey Smirnov >; 356f496e675SAndrey Smirnov }; 357f496e675SAndrey Smirnov}; 358