1*d3af422cSYunus Bas// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*d3af422cSYunus Bas/* 3*d3af422cSYunus Bas * Copyright (C) 2018 PHYTEC Messtechnik 4*d3af422cSYunus Bas * Author: Christian Hemp <c.hemp@phytec.de> 5*d3af422cSYunus Bas */ 6*d3af422cSYunus Bas 7*d3af422cSYunus Bas/ { 8*d3af422cSYunus Bas display: display0 { 9*d3af422cSYunus Bas #address-cells = <1>; 10*d3af422cSYunus Bas #size-cells = <0>; 11*d3af422cSYunus Bas compatible = "fsl,imx-parallel-display"; 12*d3af422cSYunus Bas pinctrl-names = "default"; 13*d3af422cSYunus Bas pinctrl-0 = <&pinctrl_disp0>; 14*d3af422cSYunus Bas interface-pix-fmt = "rgb24"; 15*d3af422cSYunus Bas status = "disabled"; 16*d3af422cSYunus Bas 17*d3af422cSYunus Bas port@0 { 18*d3af422cSYunus Bas reg = <0>; 19*d3af422cSYunus Bas 20*d3af422cSYunus Bas display0_in: endpoint { 21*d3af422cSYunus Bas remote-endpoint = <&ipu1_di0_disp0>; 22*d3af422cSYunus Bas }; 23*d3af422cSYunus Bas }; 24*d3af422cSYunus Bas 25*d3af422cSYunus Bas port@1 { 26*d3af422cSYunus Bas reg = <1>; 27*d3af422cSYunus Bas 28*d3af422cSYunus Bas display0_out: endpoint { 29*d3af422cSYunus Bas remote-endpoint = <&peb_panel_lcd_in>; 30*d3af422cSYunus Bas }; 31*d3af422cSYunus Bas }; 32*d3af422cSYunus Bas }; 33*d3af422cSYunus Bas 34*d3af422cSYunus Bas panel-lcd { 35*d3af422cSYunus Bas compatible = "edt,etm0700g0edh6"; 36*d3af422cSYunus Bas pinctrl-names = "default"; 37*d3af422cSYunus Bas pinctrl-0 = <&pinctrl_disp0_pwr>; 38*d3af422cSYunus Bas power-supply = <®_display>; 39*d3af422cSYunus Bas enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 40*d3af422cSYunus Bas backlight = <&backlight>; 41*d3af422cSYunus Bas status = "disabled"; 42*d3af422cSYunus Bas 43*d3af422cSYunus Bas port { 44*d3af422cSYunus Bas peb_panel_lcd_in: endpoint { 45*d3af422cSYunus Bas remote-endpoint = <&display0_out>; 46*d3af422cSYunus Bas }; 47*d3af422cSYunus Bas }; 48*d3af422cSYunus Bas }; 49*d3af422cSYunus Bas 50*d3af422cSYunus Bas reg_display: regulator-peb-display { 51*d3af422cSYunus Bas compatible = "regulator-fixed"; 52*d3af422cSYunus Bas regulator-name = "peb-display"; 53*d3af422cSYunus Bas regulator-min-microvolt = <3300000>; 54*d3af422cSYunus Bas regulator-max-microvolt = <3300000>; 55*d3af422cSYunus Bas }; 56*d3af422cSYunus Bas}; 57*d3af422cSYunus Bas 58*d3af422cSYunus Bas&i2c1 { 59*d3af422cSYunus Bas edt_ft5x06: touchscreen@38 { 60*d3af422cSYunus Bas compatible = "edt,edt-ft5406"; 61*d3af422cSYunus Bas pinctrl-names = "default"; 62*d3af422cSYunus Bas pinctrl-0 = <&pinctrl_edt_ft5x06>; 63*d3af422cSYunus Bas reg = <0x38>; 64*d3af422cSYunus Bas interrupt-parent = <&gpio3>; 65*d3af422cSYunus Bas interrupts = <2 IRQ_TYPE_NONE>; 66*d3af422cSYunus Bas status = "disabled"; 67*d3af422cSYunus Bas }; 68*d3af422cSYunus Bas}; 69*d3af422cSYunus Bas 70*d3af422cSYunus Bas&ipu1_di0_disp0 { 71*d3af422cSYunus Bas remote-endpoint = <&display0_in>; 72*d3af422cSYunus Bas}; 73*d3af422cSYunus Bas 74*d3af422cSYunus Bas&iomuxc { 75*d3af422cSYunus Bas pinctrl_disp0: disp0grp { 76*d3af422cSYunus Bas fsl,pins = < 77*d3af422cSYunus Bas MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 78*d3af422cSYunus Bas MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 79*d3af422cSYunus Bas MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 80*d3af422cSYunus Bas MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 81*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 82*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 83*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 84*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 85*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 86*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 87*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 88*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 89*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 90*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 91*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 92*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 93*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 94*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 95*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 96*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 97*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 98*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 99*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 100*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 101*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 102*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 103*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 104*d3af422cSYunus Bas MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 105*d3af422cSYunus Bas >; 106*d3af422cSYunus Bas }; 107*d3af422cSYunus Bas 108*d3af422cSYunus Bas pinctrl_disp0_pwr: disp0pwrgrp { 109*d3af422cSYunus Bas fsl,pins = < 110*d3af422cSYunus Bas MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 111*d3af422cSYunus Bas >; 112*d3af422cSYunus Bas }; 113*d3af422cSYunus Bas 114*d3af422cSYunus Bas pinctrl_edt_ft5x06: edtft5x06grp { 115*d3af422cSYunus Bas fsl,pins = < 116*d3af422cSYunus Bas MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0xb0b1 117*d3af422cSYunus Bas >; 118*d3af422cSYunus Bas }; 119*d3af422cSYunus Bas}; 120