12bf399deSPawel Dembicki// SPDX-License-Identifier: GPL-2.0 22bf399deSPawel Dembicki/* 32bf399deSPawel Dembicki * Check Point L-50 Board Description 42bf399deSPawel Dembicki * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com> 52bf399deSPawel Dembicki */ 62bf399deSPawel Dembicki 72bf399deSPawel Dembicki/dts-v1/; 82bf399deSPawel Dembicki 92bf399deSPawel Dembicki#include "kirkwood.dtsi" 102bf399deSPawel Dembicki#include "kirkwood-6281.dtsi" 112bf399deSPawel Dembicki 122bf399deSPawel Dembicki/ { 132bf399deSPawel Dembicki model = "Check Point L-50"; 142bf399deSPawel Dembicki compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 152bf399deSPawel Dembicki 162bf399deSPawel Dembicki memory { 172bf399deSPawel Dembicki device_type = "memory"; 182bf399deSPawel Dembicki reg = <0x00000000 0x20000000>; 192bf399deSPawel Dembicki }; 202bf399deSPawel Dembicki 212bf399deSPawel Dembicki chosen { 222bf399deSPawel Dembicki bootargs = "console=ttyS0,115200n8"; 232bf399deSPawel Dembicki stdout-path = &uart0; 242bf399deSPawel Dembicki }; 252bf399deSPawel Dembicki 262bf399deSPawel Dembicki ocp@f1000000 { 272bf399deSPawel Dembicki pinctrl: pin-controller@10000 { 282bf399deSPawel Dembicki pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; 292bf399deSPawel Dembicki pinctrl-names = "default"; 302bf399deSPawel Dembicki 312bf399deSPawel Dembicki pmx_sysrst: pmx-sysrst { 322bf399deSPawel Dembicki marvell,pins = "mpp6"; 332bf399deSPawel Dembicki marvell,function = "sysrst"; 342bf399deSPawel Dembicki }; 352bf399deSPawel Dembicki 362bf399deSPawel Dembicki pmx_button29: pmx_button29 { 372bf399deSPawel Dembicki marvell,pins = "mpp29"; 382bf399deSPawel Dembicki marvell,function = "gpio"; 392bf399deSPawel Dembicki }; 402bf399deSPawel Dembicki 412bf399deSPawel Dembicki pmx_led38: pmx_led38 { 422bf399deSPawel Dembicki marvell,pins = "mpp38"; 432bf399deSPawel Dembicki marvell,function = "gpio"; 442bf399deSPawel Dembicki }; 452bf399deSPawel Dembicki 462bf399deSPawel Dembicki pmx_sdio_cd: pmx-sdio-cd { 472bf399deSPawel Dembicki marvell,pins = "mpp46"; 482bf399deSPawel Dembicki marvell,function = "gpio"; 492bf399deSPawel Dembicki }; 502bf399deSPawel Dembicki }; 512bf399deSPawel Dembicki 522bf399deSPawel Dembicki serial@12000 { 532bf399deSPawel Dembicki status = "okay"; 542bf399deSPawel Dembicki }; 552bf399deSPawel Dembicki 562bf399deSPawel Dembicki mvsdio@90000 { 572bf399deSPawel Dembicki status = "okay"; 582bf399deSPawel Dembicki cd-gpios = <&gpio1 14 9>; 592bf399deSPawel Dembicki }; 602bf399deSPawel Dembicki 612bf399deSPawel Dembicki i2c@11000 { 622bf399deSPawel Dembicki status = "okay"; 632bf399deSPawel Dembicki clock-frequency = <400000>; 642bf399deSPawel Dembicki 652bf399deSPawel Dembicki gpio2: gpio-expander@20 { 662bf399deSPawel Dembicki #gpio-cells = <2>; 672bf399deSPawel Dembicki #interrupt-cells = <2>; 6896fd598eSRob Herring interrupt-controller; 692bf399deSPawel Dembicki compatible = "semtech,sx1505q"; 702bf399deSPawel Dembicki reg = <0x20>; 712bf399deSPawel Dembicki 722bf399deSPawel Dembicki gpio-controller; 732bf399deSPawel Dembicki }; 742bf399deSPawel Dembicki 752bf399deSPawel Dembicki /* Three GPIOs from 0x21 exp. are undescribed in dts: 762bf399deSPawel Dembicki * 1: DSL module reset (active low) 772bf399deSPawel Dembicki * 5: mPCIE reset (active low) 782bf399deSPawel Dembicki * 6: Express card reset (active low) 792bf399deSPawel Dembicki */ 802bf399deSPawel Dembicki gpio3: gpio-expander@21 { 812bf399deSPawel Dembicki #gpio-cells = <2>; 822bf399deSPawel Dembicki #interrupt-cells = <2>; 8396fd598eSRob Herring interrupt-controller; 842bf399deSPawel Dembicki compatible = "semtech,sx1505q"; 852bf399deSPawel Dembicki reg = <0x21>; 862bf399deSPawel Dembicki 872bf399deSPawel Dembicki gpio-controller; 882bf399deSPawel Dembicki }; 892bf399deSPawel Dembicki 902bf399deSPawel Dembicki rtc@30 { 912bf399deSPawel Dembicki compatible = "s35390a"; 922bf399deSPawel Dembicki reg = <0x30>; 932bf399deSPawel Dembicki }; 942bf399deSPawel Dembicki }; 952bf399deSPawel Dembicki }; 962bf399deSPawel Dembicki 972bf399deSPawel Dembicki leds { 982bf399deSPawel Dembicki compatible = "gpio-leds"; 992bf399deSPawel Dembicki 1009d0120b7SKrzysztof Kozlowski led-status-green { 1012bf399deSPawel Dembicki label = "l-50:green:status"; 1022bf399deSPawel Dembicki gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 1032bf399deSPawel Dembicki }; 1042bf399deSPawel Dembicki 1059d0120b7SKrzysztof Kozlowski led-status-red { 1062bf399deSPawel Dembicki label = "l-50:red:status"; 1072bf399deSPawel Dembicki gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; 1082bf399deSPawel Dembicki }; 1092bf399deSPawel Dembicki 1109d0120b7SKrzysztof Kozlowski led-wifi { 1112bf399deSPawel Dembicki label = "l-50:green:wifi"; 1122bf399deSPawel Dembicki gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 1132bf399deSPawel Dembicki linux,default-trigger = "phy0tpt"; 1142bf399deSPawel Dembicki }; 1152bf399deSPawel Dembicki 1169d0120b7SKrzysztof Kozlowski led-internet-green { 1172bf399deSPawel Dembicki label = "l-50:green:internet"; 1182bf399deSPawel Dembicki gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 1192bf399deSPawel Dembicki }; 1202bf399deSPawel Dembicki 1219d0120b7SKrzysztof Kozlowski led-internet-red { 1222bf399deSPawel Dembicki label = "l-50:red:internet"; 1232bf399deSPawel Dembicki gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 1242bf399deSPawel Dembicki }; 1252bf399deSPawel Dembicki 1269d0120b7SKrzysztof Kozlowski led-usb1-green { 1272bf399deSPawel Dembicki label = "l-50:green:usb1"; 1282bf399deSPawel Dembicki gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 1292bf399deSPawel Dembicki linux,default-trigger = "usbport"; 1302bf399deSPawel Dembicki trigger-sources = <&hub_port3>; 1312bf399deSPawel Dembicki }; 1322bf399deSPawel Dembicki 1339d0120b7SKrzysztof Kozlowski led-usb1-red { 1342bf399deSPawel Dembicki label = "l-50:red:usb1"; 1352bf399deSPawel Dembicki gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 1362bf399deSPawel Dembicki }; 1372bf399deSPawel Dembicki 1389d0120b7SKrzysztof Kozlowski led-usb2-green { 1392bf399deSPawel Dembicki label = "l-50:green:usb2"; 1402bf399deSPawel Dembicki gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 1412bf399deSPawel Dembicki linux,default-trigger = "usbport"; 1422bf399deSPawel Dembicki trigger-sources = <&hub_port1>; 1432bf399deSPawel Dembicki }; 1442bf399deSPawel Dembicki 1459d0120b7SKrzysztof Kozlowski led-usb2-red { 1462bf399deSPawel Dembicki label = "l-50:red:usb2"; 1472bf399deSPawel Dembicki gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 1482bf399deSPawel Dembicki }; 1492bf399deSPawel Dembicki }; 1502bf399deSPawel Dembicki 1512bf399deSPawel Dembicki usb2_pwr { 1522bf399deSPawel Dembicki compatible = "regulator-fixed"; 1532bf399deSPawel Dembicki regulator-name = "usb2_pwr"; 1542bf399deSPawel Dembicki 1552bf399deSPawel Dembicki regulator-min-microvolt = <5000000>; 1562bf399deSPawel Dembicki regulator-max-microvolt = <5000000>; 1572bf399deSPawel Dembicki gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; 1582bf399deSPawel Dembicki regulator-always-on; 1592bf399deSPawel Dembicki }; 1602bf399deSPawel Dembicki 1612bf399deSPawel Dembicki usb1_pwr { 1622bf399deSPawel Dembicki compatible = "regulator-fixed"; 1632bf399deSPawel Dembicki regulator-name = "usb1_pwr"; 1642bf399deSPawel Dembicki 1652bf399deSPawel Dembicki regulator-min-microvolt = <5000000>; 1662bf399deSPawel Dembicki regulator-max-microvolt = <5000000>; 1672bf399deSPawel Dembicki gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 1682bf399deSPawel Dembicki regulator-always-on; 1692bf399deSPawel Dembicki }; 1702bf399deSPawel Dembicki 1712bf399deSPawel Dembicki mpcie_pwr { 1722bf399deSPawel Dembicki compatible = "regulator-fixed"; 1732bf399deSPawel Dembicki regulator-name = "mpcie_pwr"; 1742bf399deSPawel Dembicki 1752bf399deSPawel Dembicki regulator-min-microvolt = <3300000>; 1762bf399deSPawel Dembicki regulator-max-microvolt = <3300000>; 1772bf399deSPawel Dembicki gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 1782bf399deSPawel Dembicki enable-active-high; 1792bf399deSPawel Dembicki regulator-always-on; 1802bf399deSPawel Dembicki }; 1812bf399deSPawel Dembicki 1822bf399deSPawel Dembicki express_card_pwr { 1832bf399deSPawel Dembicki compatible = "regulator-fixed"; 1842bf399deSPawel Dembicki regulator-name = "express_card_pwr"; 1852bf399deSPawel Dembicki 1862bf399deSPawel Dembicki regulator-min-microvolt = <3300000>; 1872bf399deSPawel Dembicki regulator-max-microvolt = <3300000>; 1882bf399deSPawel Dembicki gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 1892bf399deSPawel Dembicki enable-active-high; 1902bf399deSPawel Dembicki regulator-always-on; 1912bf399deSPawel Dembicki }; 1922bf399deSPawel Dembicki 1932bf399deSPawel Dembicki keys { 1942bf399deSPawel Dembicki compatible = "gpio-keys"; 1952bf399deSPawel Dembicki 196b98a9191SKrzysztof Kozlowski button-factory-defaults { 1972bf399deSPawel Dembicki label = "factory_defaults"; 1982bf399deSPawel Dembicki gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 1992bf399deSPawel Dembicki linux,code = <KEY_RESTART>; 2002bf399deSPawel Dembicki }; 2012bf399deSPawel Dembicki }; 2022bf399deSPawel Dembicki}; 2032bf399deSPawel Dembicki 2042bf399deSPawel Dembicki&mdio { 2052bf399deSPawel Dembicki status = "okay"; 2062bf399deSPawel Dembicki 2072bf399deSPawel Dembicki ethphy8: ethernet-phy@8 { 2082bf399deSPawel Dembicki reg = <0x08>; 2092bf399deSPawel Dembicki }; 2102bf399deSPawel Dembicki 2112bf399deSPawel Dembicki switch0: switch@10 { 2122bf399deSPawel Dembicki compatible = "marvell,mv88e6085"; 2132bf399deSPawel Dembicki #address-cells = <1>; 2142bf399deSPawel Dembicki #size-cells = <0>; 2152bf399deSPawel Dembicki reg = <0x10>; 2162bf399deSPawel Dembicki dsa,member = <0 0>; 2172bf399deSPawel Dembicki 2182bf399deSPawel Dembicki ports { 2192bf399deSPawel Dembicki #address-cells = <1>; 2202bf399deSPawel Dembicki #size-cells = <0>; 2212bf399deSPawel Dembicki 2222bf399deSPawel Dembicki port@0 { 2232bf399deSPawel Dembicki reg = <0>; 2242bf399deSPawel Dembicki label = "lan5"; 2252bf399deSPawel Dembicki }; 2262bf399deSPawel Dembicki 2272bf399deSPawel Dembicki port@1 { 2282bf399deSPawel Dembicki reg = <1>; 2292bf399deSPawel Dembicki label = "lan1"; 2302bf399deSPawel Dembicki }; 2312bf399deSPawel Dembicki 2322bf399deSPawel Dembicki port@2 { 2332bf399deSPawel Dembicki reg = <2>; 2342bf399deSPawel Dembicki label = "lan6"; 2352bf399deSPawel Dembicki }; 2362bf399deSPawel Dembicki 2372bf399deSPawel Dembicki port@3 { 2382bf399deSPawel Dembicki reg = <3>; 2392bf399deSPawel Dembicki label = "lan2"; 2402bf399deSPawel Dembicki }; 2412bf399deSPawel Dembicki 2422bf399deSPawel Dembicki port@4 { 2432bf399deSPawel Dembicki reg = <4>; 2442bf399deSPawel Dembicki label = "lan7"; 2452bf399deSPawel Dembicki }; 2462bf399deSPawel Dembicki 2472bf399deSPawel Dembicki switch0port5: port@5 { 2482bf399deSPawel Dembicki reg = <5>; 2492bf399deSPawel Dembicki phy-mode = "rgmii-txid"; 2502bf399deSPawel Dembicki link = <&switch1port5>; 2512bf399deSPawel Dembicki fixed-link { 2522bf399deSPawel Dembicki speed = <1000>; 2532bf399deSPawel Dembicki full-duplex; 2542bf399deSPawel Dembicki }; 2552bf399deSPawel Dembicki }; 2562bf399deSPawel Dembicki 2572bf399deSPawel Dembicki port@6 { 2582bf399deSPawel Dembicki reg = <6>; 2592bf399deSPawel Dembicki phy-mode = "rgmii-id"; 2602bf399deSPawel Dembicki ethernet = <ð1port>; 2612bf399deSPawel Dembicki fixed-link { 2622bf399deSPawel Dembicki speed = <1000>; 2632bf399deSPawel Dembicki full-duplex; 2642bf399deSPawel Dembicki }; 2652bf399deSPawel Dembicki }; 2662bf399deSPawel Dembicki }; 2672bf399deSPawel Dembicki }; 2682bf399deSPawel Dembicki 2692bf399deSPawel Dembicki switch@11 { 2702bf399deSPawel Dembicki compatible = "marvell,mv88e6085"; 2712bf399deSPawel Dembicki #address-cells = <1>; 2722bf399deSPawel Dembicki #size-cells = <0>; 2732bf399deSPawel Dembicki reg = <0x11>; 2742bf399deSPawel Dembicki dsa,member = <0 1>; 2752bf399deSPawel Dembicki 2762bf399deSPawel Dembicki ports { 2772bf399deSPawel Dembicki #address-cells = <1>; 2782bf399deSPawel Dembicki #size-cells = <0>; 2792bf399deSPawel Dembicki 2802bf399deSPawel Dembicki port@0 { 2812bf399deSPawel Dembicki reg = <0>; 2822bf399deSPawel Dembicki label = "lan3"; 2832bf399deSPawel Dembicki }; 2842bf399deSPawel Dembicki 2852bf399deSPawel Dembicki port@1 { 2862bf399deSPawel Dembicki reg = <1>; 2872bf399deSPawel Dembicki label = "lan8"; 2882bf399deSPawel Dembicki }; 2892bf399deSPawel Dembicki 2902bf399deSPawel Dembicki port@2 { 2912bf399deSPawel Dembicki reg = <2>; 2922bf399deSPawel Dembicki label = "lan4"; 2932bf399deSPawel Dembicki }; 2942bf399deSPawel Dembicki 2952bf399deSPawel Dembicki port@3 { 2962bf399deSPawel Dembicki reg = <3>; 2972bf399deSPawel Dembicki label = "dmz"; 2982bf399deSPawel Dembicki }; 2992bf399deSPawel Dembicki 3002bf399deSPawel Dembicki switch1port5: port@5 { 3012bf399deSPawel Dembicki reg = <5>; 3022bf399deSPawel Dembicki phy-mode = "rgmii-txid"; 3032bf399deSPawel Dembicki link = <&switch0port5>; 3042bf399deSPawel Dembicki fixed-link { 3052bf399deSPawel Dembicki speed = <1000>; 3062bf399deSPawel Dembicki full-duplex; 3072bf399deSPawel Dembicki }; 3082bf399deSPawel Dembicki }; 3092bf399deSPawel Dembicki 3102bf399deSPawel Dembicki port@6 { 3112bf399deSPawel Dembicki reg = <6>; 3122bf399deSPawel Dembicki label = "dsl"; 3132bf399deSPawel Dembicki fixed-link { 3142bf399deSPawel Dembicki speed = <100>; 3152bf399deSPawel Dembicki full-duplex; 3162bf399deSPawel Dembicki }; 3172bf399deSPawel Dembicki }; 3182bf399deSPawel Dembicki }; 3192bf399deSPawel Dembicki }; 3202bf399deSPawel Dembicki}; 3212bf399deSPawel Dembicki 3222bf399deSPawel Dembickið0 { 3232bf399deSPawel Dembicki status = "okay"; 3242bf399deSPawel Dembicki ethernet0-port@0 { 3252bf399deSPawel Dembicki phy-handle = <ðphy8>; 3262bf399deSPawel Dembicki }; 3272bf399deSPawel Dembicki}; 3282bf399deSPawel Dembicki 3292bf399deSPawel Dembickið1 { 3302bf399deSPawel Dembicki status = "okay"; 3312bf399deSPawel Dembicki ethernet1-port@0 { 3322bf399deSPawel Dembicki speed = <1000>; 3332bf399deSPawel Dembicki duplex = <1>; 3348aea8659SAndrew Lunn phy-mode = "rgmii"; 3352bf399deSPawel Dembicki }; 3362bf399deSPawel Dembicki}; 3372bf399deSPawel Dembicki 3382bf399deSPawel Dembicki&nand { 3392bf399deSPawel Dembicki status = "okay"; 3402bf399deSPawel Dembicki pinctrl-0 = <&pmx_nand>; 3412bf399deSPawel Dembicki pinctrl-names = "default"; 3422bf399deSPawel Dembicki 3432bf399deSPawel Dembicki partition@0 { 3442bf399deSPawel Dembicki label = "u-boot"; 3452bf399deSPawel Dembicki reg = <0x00000000 0x000c0000>; 3462bf399deSPawel Dembicki }; 3472bf399deSPawel Dembicki 3482bf399deSPawel Dembicki partition@a0000 { 3492bf399deSPawel Dembicki label = "bootldr-env"; 3502bf399deSPawel Dembicki reg = <0x000c0000 0x00040000>; 3512bf399deSPawel Dembicki }; 3522bf399deSPawel Dembicki 3532bf399deSPawel Dembicki partition@100000 { 3542bf399deSPawel Dembicki label = "kernel-1"; 3552bf399deSPawel Dembicki reg = <0x00100000 0x00800000>; 3562bf399deSPawel Dembicki }; 3572bf399deSPawel Dembicki 3582bf399deSPawel Dembicki partition@900000 { 3592bf399deSPawel Dembicki label = "rootfs-1"; 3602bf399deSPawel Dembicki reg = <0x00900000 0x07100000>; 3612bf399deSPawel Dembicki }; 3622bf399deSPawel Dembicki 3632bf399deSPawel Dembicki partition@7a00000 { 3642bf399deSPawel Dembicki label = "kernel-2"; 3652bf399deSPawel Dembicki reg = <0x07a00000 0x00800000>; 3662bf399deSPawel Dembicki }; 3672bf399deSPawel Dembicki 3682bf399deSPawel Dembicki partition@8200000 { 3692bf399deSPawel Dembicki label = "rootfs-2"; 3702bf399deSPawel Dembicki reg = <0x08200000 0x07100000>; 3712bf399deSPawel Dembicki }; 3722bf399deSPawel Dembicki 3732bf399deSPawel Dembicki partition@f300000 { 3742bf399deSPawel Dembicki label = "default_sw"; 3752bf399deSPawel Dembicki reg = <0x0f300000 0x07900000>; 3762bf399deSPawel Dembicki }; 3772bf399deSPawel Dembicki 3782bf399deSPawel Dembicki partition@16c00000 { 3792bf399deSPawel Dembicki label = "logs"; 3802bf399deSPawel Dembicki reg = <0x16c00000 0x01800000>; 3812bf399deSPawel Dembicki }; 3822bf399deSPawel Dembicki 3832bf399deSPawel Dembicki partition@18400000 { 3842bf399deSPawel Dembicki label = "preset_cfg"; 3852bf399deSPawel Dembicki reg = <0x18400000 0x00100000>; 3862bf399deSPawel Dembicki }; 3872bf399deSPawel Dembicki 3882bf399deSPawel Dembicki partition@18500000 { 3892bf399deSPawel Dembicki label = "adsl"; 3902bf399deSPawel Dembicki reg = <0x18500000 0x00100000>; 3912bf399deSPawel Dembicki }; 3922bf399deSPawel Dembicki 3932bf399deSPawel Dembicki partition@18600000 { 3942bf399deSPawel Dembicki label = "storage"; 3952bf399deSPawel Dembicki reg = <0x18600000 0x07a00000>; 3962bf399deSPawel Dembicki }; 3972bf399deSPawel Dembicki}; 3982bf399deSPawel Dembicki 3992bf399deSPawel Dembicki&rtc { 4002bf399deSPawel Dembicki status = "disabled"; 4012bf399deSPawel Dembicki}; 4022bf399deSPawel Dembicki 4032bf399deSPawel Dembicki&pciec { 4042bf399deSPawel Dembicki status = "okay"; 4052bf399deSPawel Dembicki}; 4062bf399deSPawel Dembicki 4072bf399deSPawel Dembicki&pcie0 { 4082bf399deSPawel Dembicki status = "okay"; 4092bf399deSPawel Dembicki}; 4102bf399deSPawel Dembicki 4112bf399deSPawel Dembicki&sata_phy0 { 4122bf399deSPawel Dembicki status = "disabled"; 4132bf399deSPawel Dembicki}; 4142bf399deSPawel Dembicki 4152bf399deSPawel Dembicki&sata_phy1 { 4162bf399deSPawel Dembicki status = "disabled"; 4172bf399deSPawel Dembicki}; 4182bf399deSPawel Dembicki 4192bf399deSPawel Dembicki&usb0 { 4202bf399deSPawel Dembicki #address-cells = <1>; 4212bf399deSPawel Dembicki #size-cells = <0>; 4222bf399deSPawel Dembicki status = "okay"; 4232bf399deSPawel Dembicki 4242bf399deSPawel Dembicki port@1 { 4252bf399deSPawel Dembicki #address-cells = <1>; 4262bf399deSPawel Dembicki #size-cells = <0>; 4272bf399deSPawel Dembicki reg = <1>; 4282bf399deSPawel Dembicki #trigger-source-cells = <0>; 4292bf399deSPawel Dembicki 4302bf399deSPawel Dembicki hub_port1: port@1 { 4312bf399deSPawel Dembicki reg = <1>; 4322bf399deSPawel Dembicki #trigger-source-cells = <0>; 4332bf399deSPawel Dembicki }; 4342bf399deSPawel Dembicki 4352bf399deSPawel Dembicki hub_port3: port@3 { 4362bf399deSPawel Dembicki reg = <3>; 4372bf399deSPawel Dembicki #trigger-source-cells = <0>; 4382bf399deSPawel Dembicki }; 4392bf399deSPawel Dembicki }; 4402bf399deSPawel Dembicki}; 441