xref: /linux/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0
2e38cd3aeSMaxime Hadjinlian/ {
35d7fd656SAndrew Lunn	mbus@f1000000 {
428fbb9c5SRob Herring		pciec: pcie@82000000 {
5e38cd3aeSMaxime Hadjinlian			compatible = "marvell,kirkwood-pcie";
6e38cd3aeSMaxime Hadjinlian			status = "disabled";
7e38cd3aeSMaxime Hadjinlian			device_type = "pci";
8e38cd3aeSMaxime Hadjinlian
9e38cd3aeSMaxime Hadjinlian			#address-cells = <3>;
10e38cd3aeSMaxime Hadjinlian			#size-cells = <2>;
11e38cd3aeSMaxime Hadjinlian
12e38cd3aeSMaxime Hadjinlian			bus-range = <0x00 0xff>;
13e38cd3aeSMaxime Hadjinlian
14e38cd3aeSMaxime Hadjinlian			ranges =
15e38cd3aeSMaxime Hadjinlian			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16e38cd3aeSMaxime Hadjinlian				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
17e38cd3aeSMaxime Hadjinlian				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
18e38cd3aeSMaxime Hadjinlian
197b36efd0SSebastian Hesselbarth			pcie0: pcie@1,0 {
20e38cd3aeSMaxime Hadjinlian				device_type = "pci";
21e38cd3aeSMaxime Hadjinlian				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22e38cd3aeSMaxime Hadjinlian				reg = <0x0800 0 0 0 0>;
23e38cd3aeSMaxime Hadjinlian				#address-cells = <3>;
24e38cd3aeSMaxime Hadjinlian				#size-cells = <2>;
25e38cd3aeSMaxime Hadjinlian				#interrupt-cells = <1>;
26e38cd3aeSMaxime Hadjinlian				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27e38cd3aeSMaxime Hadjinlian					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
2828fbb9c5SRob Herring				bus-range = <0x00 0xff>;
29*b332ce1bSPali Rohár				interrupt-names = "intx", "error";
30*b332ce1bSPali Rohár				interrupts = <9>, <44>;
31217dc618SPali Rohár				interrupt-map-mask = <0 0 0 7>;
32217dc618SPali Rohár				interrupt-map = <0 0 0 1 &pcie_intc 0>,
33217dc618SPali Rohár						<0 0 0 2 &pcie_intc 1>,
34217dc618SPali Rohár						<0 0 0 3 &pcie_intc 2>,
35217dc618SPali Rohár						<0 0 0 4 &pcie_intc 3>;
36e38cd3aeSMaxime Hadjinlian				marvell,pcie-port = <0>;
37e38cd3aeSMaxime Hadjinlian				marvell,pcie-lane = <0>;
38e38cd3aeSMaxime Hadjinlian				clocks = <&gate_clk 2>;
39e38cd3aeSMaxime Hadjinlian				status = "disabled";
40217dc618SPali Rohár
41217dc618SPali Rohár				pcie_intc: interrupt-controller {
42217dc618SPali Rohár					interrupt-controller;
43217dc618SPali Rohár					#interrupt-cells = <1>;
44217dc618SPali Rohár				};
45e38cd3aeSMaxime Hadjinlian			};
46e38cd3aeSMaxime Hadjinlian		};
47e38cd3aeSMaxime Hadjinlian	};
48e38cd3aeSMaxime Hadjinlian
49e38cd3aeSMaxime Hadjinlian	ocp@f1000000 {
50a9483969SSebastian Hesselbarth		pinctrl: pin-controller@10000 {
51e38cd3aeSMaxime Hadjinlian			compatible = "marvell,88f6192-pinctrl";
52e38cd3aeSMaxime Hadjinlian
53e38cd3aeSMaxime Hadjinlian			pmx_sata0: pmx-sata0 {
54e38cd3aeSMaxime Hadjinlian				marvell,pins = "mpp5", "mpp21", "mpp23";
55e38cd3aeSMaxime Hadjinlian				marvell,function = "sata0";
56e38cd3aeSMaxime Hadjinlian			};
57e38cd3aeSMaxime Hadjinlian			pmx_sata1: pmx-sata1 {
58e38cd3aeSMaxime Hadjinlian				marvell,pins = "mpp4", "mpp20", "mpp22";
59e38cd3aeSMaxime Hadjinlian				marvell,function = "sata1";
60e38cd3aeSMaxime Hadjinlian			};
61e38cd3aeSMaxime Hadjinlian			pmx_sdio: pmx-sdio {
62e38cd3aeSMaxime Hadjinlian				marvell,pins = "mpp12", "mpp13", "mpp14",
63e38cd3aeSMaxime Hadjinlian					       "mpp15", "mpp16", "mpp17";
64e38cd3aeSMaxime Hadjinlian				marvell,function = "sdio";
65e38cd3aeSMaxime Hadjinlian			};
66e38cd3aeSMaxime Hadjinlian		};
67e38cd3aeSMaxime Hadjinlian
687b36efd0SSebastian Hesselbarth		rtc: rtc@10300 {
69e38cd3aeSMaxime Hadjinlian			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
70e38cd3aeSMaxime Hadjinlian			reg = <0x10300 0x20>;
71e38cd3aeSMaxime Hadjinlian			interrupts = <53>;
72e38cd3aeSMaxime Hadjinlian			clocks = <&gate_clk 7>;
73e38cd3aeSMaxime Hadjinlian		};
74e38cd3aeSMaxime Hadjinlian
757b36efd0SSebastian Hesselbarth		sata: sata@80000 {
76e38cd3aeSMaxime Hadjinlian			compatible = "marvell,orion-sata";
77e38cd3aeSMaxime Hadjinlian			reg = <0x80000 0x5000>;
78e38cd3aeSMaxime Hadjinlian			interrupts = <21>;
79e38cd3aeSMaxime Hadjinlian			clocks = <&gate_clk 14>, <&gate_clk 15>;
80e38cd3aeSMaxime Hadjinlian			clock-names = "0", "1";
819c569b39SEvgeni Dobrev			phys = <&sata_phy0>, <&sata_phy1>;
829c569b39SEvgeni Dobrev			phy-names = "port0", "port1";
83e38cd3aeSMaxime Hadjinlian			status = "disabled";
84e38cd3aeSMaxime Hadjinlian		};
85e38cd3aeSMaxime Hadjinlian
867b36efd0SSebastian Hesselbarth		sdio: mvsdio@90000 {
87e38cd3aeSMaxime Hadjinlian			compatible = "marvell,orion-sdio";
88e38cd3aeSMaxime Hadjinlian			reg = <0x90000 0x200>;
89e38cd3aeSMaxime Hadjinlian			interrupts = <28>;
90e38cd3aeSMaxime Hadjinlian			clocks = <&gate_clk 4>;
91e38cd3aeSMaxime Hadjinlian			bus-width = <4>;
92e38cd3aeSMaxime Hadjinlian			cap-sdio-irq;
93e38cd3aeSMaxime Hadjinlian			cap-sd-highspeed;
94e38cd3aeSMaxime Hadjinlian			cap-mmc-highspeed;
95e38cd3aeSMaxime Hadjinlian			status = "disabled";
96e38cd3aeSMaxime Hadjinlian		};
97e38cd3aeSMaxime Hadjinlian	};
98e38cd3aeSMaxime Hadjinlian};
99