xref: /linux/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1ec038402SLinus Walleij// SPDX-License-Identifier: ISC
2ec038402SLinus Walleij/*
3ec038402SLinus Walleij * Device Tree include file for Intel reference designs for the
4ec038402SLinus Walleij * XScale Network Processors in the IXP 4xx series. Common device
5ec038402SLinus Walleij * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
6ec038402SLinus Walleij */
7ec038402SLinus Walleij
8ec038402SLinus Walleij/ {
9ec038402SLinus Walleij	memory@0 {
10ec038402SLinus Walleij		/*
11ec038402SLinus Walleij		 * The board supports up to 256 MB of memory. Here we put in
12ec038402SLinus Walleij		 * 64 MB and this may be modified by the boot loader.
13ec038402SLinus Walleij		 */
14ec038402SLinus Walleij		device_type = "memory";
15ec038402SLinus Walleij		reg = <0x00000000 0x4000000>;
16ec038402SLinus Walleij	};
17ec038402SLinus Walleij
18ec038402SLinus Walleij	chosen {
19ec038402SLinus Walleij		bootargs = "console=ttyS0,115200n8";
20ec038402SLinus Walleij		stdout-path = "uart0:115200n8";
21ec038402SLinus Walleij	};
22ec038402SLinus Walleij
23ec038402SLinus Walleij	aliases {
24ec038402SLinus Walleij		serial0 = &uart0;
25ec038402SLinus Walleij	};
26ec038402SLinus Walleij
27ec038402SLinus Walleij	i2c {
28ec038402SLinus Walleij		compatible = "i2c-gpio";
29ec038402SLinus Walleij		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
30ec038402SLinus Walleij		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
31ec038402SLinus Walleij		#address-cells = <1>;
32ec038402SLinus Walleij		#size-cells = <0>;
33ec038402SLinus Walleij
34ec038402SLinus Walleij		eeprom@50 {
35ec038402SLinus Walleij			/*
36ec038402SLinus Walleij			 * Philips PCF8582C-2T/03 512byte I2C EEPROM
37ec038402SLinus Walleij			 * should behave like an Atmel 24c04.
38ec038402SLinus Walleij			 */
39ec038402SLinus Walleij			compatible = "atmel,24c04";
40ec038402SLinus Walleij			reg = <0x50>;
41ec038402SLinus Walleij			pagesize = <16>;
42ec038402SLinus Walleij			size = <512>;
43ec038402SLinus Walleij			read-only;
44ec038402SLinus Walleij		};
45ec038402SLinus Walleij	};
46ec038402SLinus Walleij
47ec038402SLinus Walleij	soc {
48ec038402SLinus Walleij		bus@c4000000 {
49ec038402SLinus Walleij			/* Flash memory defined per-variant */
50ec038402SLinus Walleij			nand-controller@3,0 {
51ec038402SLinus Walleij				/* Some designs have a NAND on CS3 enable it here if present */
52ec038402SLinus Walleij				status = "disabled";
53ec038402SLinus Walleij
54ec038402SLinus Walleij				/*
55ec038402SLinus Walleij				 * gen_nand needs to be extended and documented to get
56ec038402SLinus Walleij				 * command byte = 1 and address byte = 2 from the device
57ec038402SLinus Walleij				 * tree.
58ec038402SLinus Walleij				 */
59ec038402SLinus Walleij				compatible = "gen_nand";
60ec038402SLinus Walleij
61ec038402SLinus Walleij				/* Expansion bus set-up */
62ec038402SLinus Walleij				intel,ixp4xx-eb-t1 = <0>;
63ec038402SLinus Walleij				intel,ixp4xx-eb-t2 = <0>;
64ec038402SLinus Walleij				intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
65ec038402SLinus Walleij				intel,ixp4xx-eb-t4 = <0>;
66ec038402SLinus Walleij				intel,ixp4xx-eb-t5 = <0>;
67ec038402SLinus Walleij				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
68ec038402SLinus Walleij				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
69ec038402SLinus Walleij				intel,ixp4xx-eb-mux-address-and-data = <0>;
70ec038402SLinus Walleij				intel,ixp4xx-eb-ahb-split-transfers = <0>;
71ec038402SLinus Walleij				intel,ixp4xx-eb-write-enable = <1>;
72ec038402SLinus Walleij				intel,ixp4xx-eb-byte-access = <1>;
73ec038402SLinus Walleij
74ec038402SLinus Walleij				/* 512 bytes memory window */
75ec038402SLinus Walleij				reg = <3 0x00000000 0x200>;
76ec038402SLinus Walleij				nand-on-flash-bbt;
77ec038402SLinus Walleij				nand-ecc-mode = "soft_bch";
78ec038402SLinus Walleij				nand-ecc-step-size = <512>;
79ec038402SLinus Walleij				nand-ecc-strength = <4>;
80ec038402SLinus Walleij				nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
81ec038402SLinus Walleij
82ec038402SLinus Walleij				label = "ixp400 NAND";
83ec038402SLinus Walleij
84ec038402SLinus Walleij				partitions {
85ec038402SLinus Walleij					compatible = "fixed-partitions";
86ec038402SLinus Walleij					#address-cells = <1>;
87ec038402SLinus Walleij					#size-cells = <1>;
88ec038402SLinus Walleij
89ec038402SLinus Walleij					fs@0 {
90ec038402SLinus Walleij						label = "ixp400 NAND FS 0";
91ec038402SLinus Walleij						reg = <0x0 0x800000>;
92ec038402SLinus Walleij					};
93ec038402SLinus Walleij					fs@800000 {
94ec038402SLinus Walleij						label = "ixp400 NAND FS 1";
95ec038402SLinus Walleij						reg = <0x800000 0x0>;
96ec038402SLinus Walleij					};
97ec038402SLinus Walleij				};
98ec038402SLinus Walleij			};
99ec038402SLinus Walleij		};
100ec038402SLinus Walleij
101ec038402SLinus Walleij		pci@c0000000 {
102*129469c4SKrzysztof Kozlowski			status = "okay";
103ec038402SLinus Walleij
104ec038402SLinus Walleij			/*
105ec038402SLinus Walleij			 * Taken from IXDP425 PCI boardfile.
106ec038402SLinus Walleij			 * PCI slots on the BIXMB425BD base card.
107ec038402SLinus Walleij			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
108ec038402SLinus Walleij			 */
1093e70cee4SRob Herring			#interrupt-cells = <1>;
1103e70cee4SRob Herring			interrupt-map-mask = <0xf800 0 0 7>;
111ec038402SLinus Walleij			interrupt-map =
112ec038402SLinus Walleij			/* IDSEL 1 */
113ec038402SLinus Walleij			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
114ec038402SLinus Walleij			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
115ec038402SLinus Walleij			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
116ec038402SLinus Walleij			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
117ec038402SLinus Walleij			/* IDSEL 2 */
118ec038402SLinus Walleij			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
119ec038402SLinus Walleij			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
120ec038402SLinus Walleij			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
121ec038402SLinus Walleij			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
122ec038402SLinus Walleij			/* IDSEL 3 */
123ec038402SLinus Walleij			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
124ec038402SLinus Walleij			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
125ec038402SLinus Walleij			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
126ec038402SLinus Walleij			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
127ec038402SLinus Walleij			/* IDSEL 4 */
128ec038402SLinus Walleij			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
129ec038402SLinus Walleij			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
130ec038402SLinus Walleij			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
131ec038402SLinus Walleij			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
132ec038402SLinus Walleij		};
133ec038402SLinus Walleij	};
134ec038402SLinus Walleij};
135