1.. SPDX-License-Identifier: GPL-2.0 2 3================================= 4Intel Touch Host Controller (THC) 5================================= 6 7Touch Host Controller is the name of the IP block in PCH that interface with Touch Devices (ex: 8touchscreen, touchpad etc.). It is comprised of 3 key functional blocks: 9 10- A natively half-duplex Quad I/O capable SPI master 11- Low latency I2C interface to support HIDI2C compliant devices 12- A HW sequencer with RW DMA capability to system memory 13 14It has a single root space IOSF Primary interface that supports transactions to/from touch devices. 15Host driver configures and controls the touch devices over THC interface. THC provides high 16bandwidth DMA services to the touch driver and transfers the HID report to host system main memory. 17 18Hardware sequencer within the THC is responsible for transferring (via DMA) data from touch devices 19into system memory. A ring buffer is used to avoid data loss due to asynchronous nature of data 20consumption (by host) in relation to data production (by touch device via DMA). 21 22Unlike other common SPI/I2C controllers, THC handles the HID device data interrupt and reset 23signals directly. 24 251. Overview 26=========== 27 281.1 THC software/hardware stack 29------------------------------- 30 31Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully 32capable of supporting HIDSPI/HIDI2C protocol in Linux OS. 33 34:: 35 36 ---------------------------------------------- 37 | +-----------------------------------+ | 38 | | Input Device | | 39 | +-----------------------------------+ | 40 | +-----------------------------------+ | 41 | | HID Multi-touch Driver | | 42 | +-----------------------------------+ | 43 | +-----------------------------------+ | 44 | | HID Core | | 45 | +-----------------------------------+ | 46 | +-----------------------------------+ | 47 | | THC QuickSPI/QuickI2C Driver | | 48 | +-----------------------------------+ | 49 | +-----------------------------------+ | 50 | | THC Hardware Driver | | 51 | +-----------------------------------+ | 52 | +----------------+ +----------------+ | 53 | SW | PCI Bus Driver | | ACPI Resource | | 54 | +----------------+ +----------------+ | 55 ---------------------------------------------- 56 ---------------------------------------------- 57 | +-----------------------------------+ | 58 | HW | PCI Bus | | 59 | +-----------------------------------+ | 60 | +-----------------------------------+ | 61 | | THC Controller | | 62 | +-----------------------------------+ | 63 | +-----------------------------------+ | 64 | | Touch IC | | 65 | +-----------------------------------+ | 66 ---------------------------------------------- 67 68Touch IC (TIC), also as known as the Touch devices (touchscreen or touchpad). The discrete analog 69components that sense and transfer either discrete touch data or heatmap data in the form of HID 70reports over the SPI/I2C bus to the THC Controller on the host. 71 72THC Host Controller, which is a PCI device HBA (host bus adapter), integrated into the PCH, that 73serves as a bridge between the Touch ICs and the host. 74 75THC Hardware Driver, provides THC hardware operation APIs for above QuickSPI/QuickI2C driver, it 76accesses THC MMIO registers to configure and control THC hardware. 77 78THC QuickSPI/QuickI2C driver, also as known as HIDSPI/HIDI2C driver, is registered as a HID 79low-level driver that manages the THC Controller and implements HIDSPI/HIDI2C protocol. 80 81 821.2 THC hardware diagram 83------------------------ 84Below diagram shows THC hardware components:: 85 86 --------------------------------- 87 | THC Controller | 88 | +---------------------------+ | 89 | | PCI Config Space | | 90 | +---------------------------+ | 91 | +---------------------------+ | 92 | + MMIO Registers | | 93 | +---------------------------+ | 94 +---------------+ | +------------+ +------------+ | 95 | System Memory +---+--+ DMA | | PIO | | 96 +---------------+ | +------------+ +------------+ | 97 | +---------------------------+ | 98 | | HW Sequencer | | 99 | +---------------------------+ | 100 | +------------+ +------------+ | 101 | | SPI/I2C | | GPIO | | 102 | | Controller | | Controller | | 103 | +------------+ +------------+ | 104 --------------------------------- 105 106As THC is exposed as a PCI devices, so it has standard PCI config space registers for PCI 107enumeration and configuration. 108 109MMIO Registers, which provide registers access for driver to configure and control THC hardware, 110the registers include several categories: Interrupt status and control, DMA configure, 111PIO (Programmed I/O, defined in section 3.2) status and control, SPI bus configure, I2C subIP 112status and control, reset status and control... 113 114THC provides two ways for driver to communicate with external Touch ICs: PIO and DMA. 115PIO can let driver manually write/read data to/from Touch ICs, instead, THC DMA can 116automatically write/read data without driver involved. 117 118HW Sequencer includes THC major logic, it gets instruction from MMIO registers to control 119SPI bus and I2C bus to finish a bus data transaction, it also can automatically handle 120Touch ICs interrupt and start DMA receive/send data from/to Touch ICs according to interrupt 121type. That means THC HW Sequencer understands HIDSPI/HIDI2C transfer protocol, and handle 122the communication without driver involved, what driver needs to do is just configure the THC 123properly, and prepare the formatted data packet or handle received data packet. 124 125As THC supports HIDSPI/HIDI2C protocols, it has SPI controller and I2C subIP in it to expose 126SPI bus and I2C bus. THC also integrates a GPIO controller to provide interrupt line support 127and reset line support. 128 1292. THC Hardware Interface 130========================= 131 1322.1 Host Interface 133------------------ 134 135THC is exposed as "PCI Digitizer device" to the host. The PCI product and device IDs are 136changed from different generations of processors. So the source code which enumerates drivers 137needs to update from generation to generation. 138 139 1402.2 Device Interface 141-------------------- 142 143THC supports two types of bus for Touch IC connection: Enhanced SPI bus and I2C bus. 144 1452.2.1 SPI Port 146~~~~~~~~~~~~~~ 147 148When PORT_TYPE = 00b in MMIO registers, THC uses SPI interfaces to communicate with external 149Touch IC. THC enhanced SPI Bus supports different SPI modes: standard Single IO mode, 150Dual IO mode and Quad IO mode. 151 152In Single IO mode, THC drives MOSI line to send data to Touch ICs, and receives data from Touch 153ICs data from MISO line. In Dual IO mode, THC drivers MOSI and MISO both for data sending, and 154also receives the data on both line. In Quad IO mode, there are other two lines (IO2 and IO3) 155are added, THC drives MOSI (IO0), MISO (IO1), IO2 and IO3 at the same time for data sending, and 156also receives the data on those 4 lines. Driver needs to configure THC in different mode by 157setting different opcode. 158 159Beside IO mode, driver also needs to configure SPI bus speed. THC supports up to 42MHz SPI clock 160on Intel Lunar Lake platform. 161 162For THC sending data to Touch IC, the data flow on SPI bus:: 163 164 | --------------------THC sends---------------------------------| 165 <8Bits OPCode><24Bits Slave Address><Data><Data><Data>........... 166 167For THC receiving data from Touch IC, the data flow on SPI bus:: 168 169 | ---------THC Sends---------------||-----Touch IC sends--------| 170 <8Bits OPCode><24Bits Slave Address><Data><Data><Data>........... 171 1722.2.2 I2C Port 173~~~~~~~~~~~~~~ 174 175THC also integrates I2C controller in it, it's called I2C SubSystem. When PORT_TYPE = 01, THC 176is configured to I2C mode. Comparing to SPI mode which can be configured through MMIO registers 177directly, THC needs to use PIO read (by setting SubIP read opcode) to I2C subIP APB registers' 178value and use PIO write (by setting SubIP write opcode) to do a write operation. 179 1802.2.3 GPIO interface 181~~~~~~~~~~~~~~~~~~~~ 182 183THC also includes two GPIO pins, one for interrupt and the other for device reset control. 184 185Interrupt line can be configured to either level triggered or edge triggered by setting MMIO 186Control register. 187 188Reset line is controlled by BIOS (or EFI) through ACPI _RST method, driver needs to call this 189device ACPI _RST method to reset touch IC during initialization. 190 1912.3 Max input size control 192-------------------------- 193 194This is a new feature introduced in Panther Lake platform, THC hardware allows driver to set 195a max input size for RxDMA. After this max size gets set and enabled, for every input report 196packet reading, THC hardware sequencer will first read incoming input packet size, then compare 197input packet size with the given max size: 198 199- if input packet size <= max size, THC continues using input packet size to finish the reading 200- if input packet size > max size, there is potential input data crash risk during 201 transferring, THC will use max size instead of input packet size for reading 202 203This feature is used to avoid data corruption which will cause RxDMA buffer overrun issue for 204I2C bus, and enhance whole system stability. 205 2062.4 Interrupt delay 207------------------- 208 209Because of MCU performance limitation, some touch devices cannot de-assert interrupt pin 210immediately after input data is transferred, which cause an interrupt toggle delay. But THC 211always detects next interrupt immediately after last input interrupt is handled. In this 212case, the delayed interrupt de-assertion will be recognized as a new interrupt signal by THC, 213and causes THC to start an input report reading spuriously. 214 215In order to avoid this situation, THC introduced interrupt delay new feature in Panther Lake 216platform, where THC allows driver to set an interrupt delay. After this feature is enabled, 217THC will delay this given time for next interrupt detection. 218 2193. High level concept 220===================== 221 2223.1 Opcode 223---------- 224 225Opcode (operation code) is used to tell THC or Touch IC what the operation will be, such as PIO 226read or PIO write. 227 228When THC is configured to SPI mode, opcodes are used for determining the read/write IO mode. 229There are some OPCode examples for SPI IO mode: 230 231======= ============================== 232opcode Corresponding SPI command 233======= ============================== 2340x0B Read Single I/O 2350x02 Write Single I/O 2360xBB Read Dual I/O 2370xB2 Write Dual I/O 2380xEB Read Quad I/O 2390xE2 Write Quad I/O 240======= ============================== 241 242In general, different touch IC has different OPCode definition. According to HIDSPI 243protocol whitepaper, those OPCodes are defined in device ACPI table, and driver needs to 244query those information through OS ACPI APIs during driver initialization, then configures 245THC MMIO OPCode registers with correct setting. 246 247When THC is working in I2C mode, opcodes are used to tell THC what's the next PIO type: 248I2C SubIP APB register read, I2C SubIP APB register write, I2C touch IC device read, 249I2C touch IC device write, I2C touch IC device write followed by read. 250 251Here are the THC pre-defined opcodes for I2C mode: 252 253======= =================================================== =========== 254opcode Corresponding I2C command Address 255======= =================================================== =========== 2560x12 Read I2C SubIP APB internal registers 0h - FFh 2570x13 Write I2C SubIP APB internal registers 0h - FFh 2580x14 Read external Touch IC through I2C bus N/A 2590x18 Write external Touch IC through I2C bus N/A 2600x1C Write then read external Touch IC through I2C bus N/A 261======= =================================================== =========== 262 2633.2 PIO 264------- 265 266THC provides a programmed I/O (PIO) access interface for the driver to access the touch IC's 267configuration registers, or access I2C subIP's configuration registers. To use PIO to perform 268I/O operations, driver should pre-program PIO control registers and PIO data registers and kick 269off the sequencing cycle. THC uses different PIO opcodes to distinguish different PIO 270operations (PIO read/write/write followed by read). 271 272If there is a Sequencing Cycle In Progress and an attempt is made to program any of the control, 273address, or data register the cycle is blocked and a sequence error will be encountered. 274 275A status bit indicates when the cycle has completed allowing the driver to know when read results 276can be checked and/or when to initiate a new command. If enabled, the cycle done assertion can 277interrupt driver with an interrupt. 278 279Because THC only has 16 FIFO registers for PIO, so all the data transfer through PIO shouldn't 280exceed 64 bytes. 281 282As DMA needs max packet size for transferring configuration, and the max packet size information 283always in HID device descriptor which needs THC driver to read it out from HID Device (Touch IC). 284So PIO typical use case is, before DMA initialization, write RESET command (PIO write), read 285RESET response (PIO read or PIO write followed by read), write Power ON command (PIO write), read 286device descriptor (PIO read). 287 288For how to issue a PIO operation, here is the steps which driver needs follow: 289 290- Program read/write data size in THC_SS_BC. 291- Program I/O target address in THC_SW_SEQ_DATA0_ADDR. 292- If write, program the write data in THC_SW_SEQ_DATA0..THC_SW_SEQ_DATAn. 293- Program the PIO opcode in THC_SS_CMD. 294- Set TSSGO = 1 to start the PIO write sequence. 295- If THC_SS_CD_IE = 1, SW will receives a MSI when the PIO is completed. 296- If read, read out the data in THC_SW_SEQ_DATA0..THC_SW_SEQ_DATAn. 297 2983.3 DMA 299------- 300 301THC has 4 DMA channels: Read DMA1, Read DMA2, Write DMA and Software DMA. 302 3033.3.1 Read DMA Channel 304~~~~~~~~~~~~~~~~~~~~~~ 305 306THC has two Read DMA engines: 1st RxDMA (RxDMA1) and 2nd RxDMA (RxDMA2). RxDMA1 is reserved for 307raw data mode. RxDMA2 is used for HID data mode and it is the RxDMA engine currently driver uses 308for HID input report data retrieval. 309 310RxDMA's typical use case is auto receiving the data from Touch IC. Once RxDMA is enabled by 311software, THC will start auto-handling receiving logic. 312 313For SPI mode, THC RxDMA sequence is: when Touch IC triggers a interrupt to THC, THC reads out 314report header to identify what's the report type, and what's the report length, according to 315above information, THC reads out report body to internal FIFO and start RxDMA coping the data 316to system memory. After that, THC update interrupt cause register with report type, and update 317RxDMA PRD table read pointer, then trigger a MSI interrupt to notify driver RxDMA finishing 318data receiving. 319 320For I2C mode, THC RxDMA's behavior is a little bit different, because of HIDI2C protocol difference 321with HIDSPI protocol, RxDMA only be used to receive input report. The sequence is, when Touch IC 322triggers a interrupt to THC, THC first reads out 2 bytes from input report address to determine the 323packet length, then use this packet length to start a DMA reading from input report address for 324input report data. After that, THC update RxDMA PRD table read pointer, then trigger a MSI interrupt 325to notify driver input report data is ready in system memory. 326 327All above sequence is hardware automatically handled, all driver needs to do is configure RxDMA and 328waiting for interrupt ready then read out the data from system memory. 329 3303.3.2 Software DMA channel 331~~~~~~~~~~~~~~~~~~~~~~~~~~ 332 333THC supports a software triggered RxDMA mode to read the touch data from touch IC. This SW RxDMA 334is the 3rd THC RxDMA engine with the similar functionalities as the existing two RxDMAs, the only 335difference is this SW RxDMA is triggered by software, and RxDMA2 is triggered by external Touch IC 336interrupt. It gives a flexibility to software driver to use RxDMA read Touch IC data in any time. 337 338Before software starts a SW RxDMA, it shall stop the 1st and 2nd RxDMA, clear PRD read/write pointer 339and quiesce the device interrupt (THC_DEVINT_QUIESCE_HW_STS = 1), other operations are the same with 340RxDMA. 341 3423.3.3 Write DMA Channel 343~~~~~~~~~~~~~~~~~~~~~~~ 344 345THC has one write DMA engine, which can be used for sending data to Touch IC automatically. 346According to HIDSPI and HIDI2C protocol, every time only one command can be sent to touch IC, and 347before last command is completely handled, next command cannot be sent, THC write DMA engine only 348supports single PRD table. 349 350What driver needs to do is, preparing PRD table and DMA buffer, then copy data to DMA buffer and 351update PRD table with buffer address and buffer length, then start write DMA. THC will 352automatically send the data to touch IC, and trigger a DMA completion interrupt once transferring 353is done. 354 3553.4 PRD 356------- 357 358Physical Region Descriptor (PRD) provides the memory mapping description for THC DMAs. 359 3603.4.1 PRD table and entry 361~~~~~~~~~~~~~~~~~~~~~~~~~ 362 363In order to improve physical DMA memory usage, modern drivers trend to allocate a virtually 364contiguous, but physically fragmented buffer of memory for each data buffer. Linux OS also 365provide SGL (scatter gather list) APIs to support this usage. 366 367THC uses PRD table (physical region descriptor) to support the corresponding OS kernel 368SGL that describes the virtual to physical buffer mapping. 369 370:: 371 372 ------------------------ -------------- -------------- 373 | PRD table base address +----+ PRD table #1 +-----+ PRD Entry #1 | 374 ------------------------ -------------- -------------- 375 -------------- 376 | PRD Entry #2 | 377 -------------- 378 -------------- 379 | PRD Entry #n | 380 -------------- 381 382The read DMA engine supports multiple PRD tables held within a circular buffer that allow the THC 383to support multiple data buffers from the Touch IC. This allows host SW to arm the Read DMA engine 384with multiple buffers, allowing the Touch IC to send multiple data frames to the THC without SW 385interaction. This capability is required when the CPU processes touch frames slower than the 386Touch IC can send them. 387 388To simplify the design, SW assumes worst-case memory fragmentation. Therefore,each PRD table shall 389contain the same number of PRD entries, allowing for a global register (per Touch IC) to hold the 390number of PRD-entries per PRD table. 391 392SW allocates up to 128 PRD tables per Read DMA engine as specified in the THC_M_PRT_RPRD_CNTRL.PCD 393register field. The number of PRD tables should equal the number of data buffers. 394 395Max OS memory fragmentation will be at a 4KB boundary, thus to address 1MB of virtually contiguous 396memory 256 PRD entries are required for a single PRD Table. SW writes the number of PRD entries 397for each PRD table in the THC_M_PRT_RPRD_CNTRL.PTEC register field. The PRD entry's length must be 398multiple of 4KB except for the last entry in a PRD table. 399 400SW allocates all the data buffers and PRD tables only once at host initialization. 401 4023.4.2 PRD Write pointer and read pointer 403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 404 405As PRD tables are organized as a Circular Buffer (CB), a read pointer and a write pointer for a CB 406are needed. 407 408DMA HW consumes the PRD tables in the CB, one PRD entry at a time until the EOP bit is found set 409in a PRD entry. At this point HW increments the PRD read pointer. Thus, the read pointer points 410to the PRD which the DMA engine is currently processing. This pointer rolls over once the circular 411buffer's depth has been traversed with bit[7] the Rollover bit. E.g. if the DMA CB depth is equal 412to 4 entries (0011b), then the read pointers will follow this pattern (HW is required to honor 413this behavior): 00h 01h 02h 03h 80h 81h 82h 83h 00h 01h ... 414 415The write pointer is updated by SW. The write pointer points to location in the DMA CB, where the 416next PRD table is going to be stored. SW needs to ensure that this pointer rolls over once the 417circular buffer's depth has been traversed with Bit[7] as the rollover bit. E.g. if the DMA CB 418depth is equal to 5 entries (0100b), then the write pointers will follow this pattern (SW is 419required to honor this behavior): 00h 01h 02h 03h 04h 80h 81h 82h 83h 84h 00h 01h .. 420 4213.4.3 PRD descriptor structure 422~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 423 424Intel THC uses PRD entry descriptor for every PRD entry. Every PRD entry descriptor occupies 425128 bits memories: 426 427=================== ======== =============================================== 428struct field bit(s) description 429=================== ======== =============================================== 430dest_addr 53..0 destination memory address, as every entry 431 is 4KB, ignore lowest 10 bits of address. 432reserved1 54..62 reserved 433int_on_completion 63 completion interrupt enable bit, if this bit 434 set it means THC will trigger a completion 435 interrupt. This bit is set by SW driver. 436len 87..64 how many bytes of data in this entry. 437end_of_prd 88 end of PRD table bit, if this bit is set, 438 it means this entry is last entry in this PRD 439 table. This bit is set by SW driver. 440hw_status 90..89 HW status bits 441reserved2 127..91 reserved 442=================== ======== =============================================== 443 444And one PRD table can include up to 256 PRD entries, as every entries is 4K bytes, so every 445PRD table can describe 1M bytes memory. 446 447.. code-block:: c 448 449 struct thc_prd_table { 450 struct thc_prd_entry entries[PRD_ENTRIES_NUM]; 451 }; 452 453In general, every PRD table means one HID touch data packet. Every DMA engine can support 454up to 128 PRD tables (except write DMA, write DMA only has one PRD table). SW driver is responsible 455to get max packet length from touch IC, and use this max packet length to create PRD entries for 456each PRD table. 457 4584. HIDSPI support (QuickSPI) 459============================ 460 461Intel THC is total compatible with HIDSPI protocol, THC HW sequenser can accelerate HIDSPI 462protocol transferring. 463 4644.1 Reset Flow 465-------------- 466 467- Call ACPI _RST method to reset Touch IC device. 468- Read the reset response from TIC through PIO read. 469- Issue a command to retrieve device descriptor from Touch IC through PIO write. 470- Read the device descriptor from Touch IC through PIO read. 471- If the device descriptor is valid, allocate DMA buffers and configure all DMA channels. 472- Issue a command to retrieve report descriptor from Touch IC through DMA. 473 4744.2 Input Report Data Flow 475-------------------------- 476 477Basic Flow: 478 479- Touch IC interrupts the THC Controller using an in-band THC interrupt. 480- THC Sequencer reads the input report header by transmitting read approval as a signal 481 to the Touch IC to prepare for host to read from the device. 482- THC Sequencer executes a Input Report Body Read operation corresponding to the value 483 reflected in “Input Report Length” field of the Input Report Header. 484- THC DMA engine begins fetching data from the THC Sequencer and writes to host memory 485 at PRD entry 0 for the current CB PRD table entry. This process continues until the 486 THC Sequencer signals all data has been read or the THC DMA Read Engine reaches the 487 end of it's last PRD entry (or both). 488- The THC Sequencer checks for the “Last Fragment Flag” bit in the Input Report Header. 489 If it is clear, the THC Sequencer enters an idle state. 490- If the “Last Fragment Flag” bit is enabled the THC Sequencer enters End-of-Frame Processing. 491 492THC Sequencer End of Frame Processing: 493 494- THC DMA engine increments the read pointer of the Read PRD CB, sets EOF interrupt status 495 in RxDMA2 register (THC_M_PRT_READ_DMA_INT_STS_2). 496- If THC EOF interrupt is enabled by the driver in the control register (THC_M_PRT_READ_DMA_CNTRL_2), 497 generates interrupt to software. 498 499Sequence of steps to read data from RX DMA buffer: 500 501- THC QuickSPI driver checks CB write Ptr and CB read Ptr to identify if any data frame in DMA 502 circular buffers. 503- THC QuickSPI driver gets first unprocessed PRD table. 504- THC QuickSPI driver scans all PRD entries in this PRD table to calculate the total frame size. 505- THC QuickSPI driver copies all frame data out. 506- THC QuickSPI driver checks the data type according to input report body, and calls related 507 callbacks to process the data. 508- THC QuickSPI driver updates write Ptr. 509 5104.3 Output Report Data Flow 511--------------------------- 512 513Generic Output Report Flow: 514 515- HID core calls raw_request callback with a request to THC QuickSPI driver. 516- THC QuickSPI Driver converts request provided data into the output report packet and copies it 517 to THC's write DMA buffer. 518- Start TxDMA to complete the write operation. 519 5205. HIDI2C support (QuickI2C) 521============================ 522 5235.1 Reset Flow 524-------------- 525 526- Read device descriptor from Touch IC device through PIO write followed by read. 527- If the device descriptor is valid, allocate DMA buffers and configure all DMA channels. 528- Use PIO or TxDMA to write a SET_POWER request to TIC's command register, and check if the 529 write operation is successfully completed. 530- Use PIO or TxDMA to write a RESET request to TIC's command register. If the write operation 531 is successfully completed, wait for reset response from TIC. 532- Use SWDMA to read report descriptor through TIC's report descriptor register. 533 5345.2 Input Report Data Flow 535-------------------------- 536 537Basic Flow: 538 539- Touch IC asserts the interrupt indicating that it has an interrupt to send to HOST. 540 THC Sequencer issues a READ request over the I2C bus. The HIDI2C device returns the 541 first 2 bytes from the HIDI2C device which contains the length of the received data. 542- THC Sequencer continues the Read operation as per the size of data indicated in the 543 length field. 544- THC DMA engine begins fetching data from the THC Sequencer and writes to host memory 545 at PRD entry 0 for the current CB PRD table entry. THC writes 2Bytes for length field 546 plus the remaining data to RxDMA buffer. This process continues until the THC Sequencer 547 signals all data has been read or the THC DMA Read Engine reaches the end of it's last 548 PRD entry (or both). 549- THC Sequencer enters End-of-Input Report Processing. 550- If the device has no more input reports to send to the host, it de-asserts the interrupt 551 line. For any additional input reports, device keeps the interrupt line asserted and 552 steps 1 through 4 in the flow are repeated. 553 554THC Sequencer End of Input Report Processing: 555 556- THC DMA engine increments the read pointer of the Read PRD CB, sets EOF interrupt status 557 in RxDMA 2 register (THC_M_PRT_READ_DMA_INT_STS_2). 558- If THC EOF interrupt is enabled by the driver in the control register 559 (THC_M_PRT_READ_DMA_CNTRL_2), generates interrupt to software. 560 561Sequence of steps to read data from RX DMA buffer: 562 563- THC QuickI2C driver checks CB write Ptr and CB read Ptr to identify if any data frame in DMA 564 circular buffers. 565- THC QuickI2C driver gets first unprocessed PRD table. 566- THC QuickI2C driver scans all PRD entries in this PRD table to calculate the total frame size. 567- THC QuickI2C driver copies all frame data out. 568- THC QuickI2C driver call hid_input_report to send the input report content to HID core, which 569 includes Report ID + Report Data Content (remove the length field from the original report 570 data). 571- THC QuickI2C driver updates write Ptr. 572 5735.3 Output Report Data Flow 574--------------------------- 575 576Generic Output Report Flow: 577 578- HID core call THC QuickI2C raw_request callback. 579- THC QuickI2C uses PIO or TXDMA to write a SET_REPORT request to TIC's command register. Report 580 type in SET_REPORT should be set to Output. 581- THC QuickI2C programs TxDMA buffer with TX Data to be written to TIC's data register. The first 582 2 bytes should indicate the length of the report followed by the report contents including 583 Report ID. 584 5856. THC Debugging 586================ 587 588To debug THC, event tracing mechanism is used. To enable debug logs:: 589 590 echo 1 > /sys/kernel/debug/tracing/events/intel_thc/enable 591 cat /sys/kernel/debug/tracing/trace 592 5937. Reference 594============ 595- HIDSPI: https://download.microsoft.com/download/c/a/0/ca07aef3-3e10-4022-b1e9-c98cea99465d/HidSpiProtocolSpec.pdf 596- HIDI2C: https://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx 597