xref: /linux/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml (revision 6315d93541f8a5f77c5ef5c4f25233e66d189603)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC Multi Core Timer (MCT)
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14  global timer and CPU local timers. The global timer is a 64-bit free running
15  up-counter and can generate 4 interrupts when the counter reaches one of the
16  four preset counter values. The CPU local timers are 32-bit free running
17  down-counters and generate an interrupt when the counter expires. There is
18  one CPU local timer instantiated in MCT for every CPU in the system.
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - samsung,exynos4210-mct
25          - samsung,exynos4412-mct
26      - items:
27          - enum:
28              - axis,artpec8-mct
29              - google,gs101-mct
30              - samsung,exynos2200-mct-peris
31              - samsung,exynos3250-mct
32              - samsung,exynos5250-mct
33              - samsung,exynos5260-mct
34              - samsung,exynos5420-mct
35              - samsung,exynos5433-mct
36              - samsung,exynos850-mct
37              - samsung,exynos8895-mct
38              - samsung,exynos990-mct
39              - tesla,fsd-mct
40          - const: samsung,exynos4210-mct
41
42  clocks:
43    maxItems: 2
44
45  clock-names:
46    items:
47      - const: fin_pll
48      - const: mct
49
50  reg:
51    maxItems: 1
52
53  samsung,frc-shared:
54    type: boolean
55    description: |
56      Indicates that the hardware requires that this processor share the
57      free-running counter with a different (main) processor.
58
59  samsung,local-timers:
60    $ref: /schemas/types.yaml#/definitions/uint32-array
61    minItems: 1
62    maxItems: 16
63    description: |
64      List of indices of local timers usable from this processor.
65
66  interrupts:
67    description: |
68      Interrupts should be put in specific order. This is, the local timer
69      interrupts should be specified after the four global timer interrupts
70      have been specified:
71      0: Global Timer Interrupt 0
72      1: Global Timer Interrupt 1
73      2: Global Timer Interrupt 2
74      3: Global Timer Interrupt 3
75      4: Local Timer Interrupt 0
76      5: Local Timer Interrupt 1
77      6: ..
78      7: ..
79      i: Local Timer Interrupt n
80      For MCT block that uses a per-processor interrupt for local timers, such
81      as ones compatible with "samsung,exynos4412-mct", only one local timer
82      interrupt might be specified, meaning that all local timers use the same
83      per processor interrupt.
84    minItems: 5               # 4 Global + 1 local
85    maxItems: 20              # 4 Global + 16 local
86
87required:
88  - compatible
89  - clock-names
90  - clocks
91  - interrupts
92  - reg
93
94allOf:
95  - if:
96      not:
97        properties:
98          compatible:
99            contains:
100              enum:
101                - axis,artpec8-mct
102    then:
103      properties:
104        samsung,local-timers: false
105        samsung,frc-shared: false
106  - if:
107      properties:
108        compatible:
109          contains:
110            const: samsung,exynos3250-mct
111    then:
112      properties:
113        interrupts:
114          minItems: 8
115          maxItems: 8
116
117  - if:
118      properties:
119        compatible:
120          contains:
121            const: samsung,exynos5250-mct
122    then:
123      properties:
124        interrupts:
125          minItems: 6
126          maxItems: 6
127
128  - if:
129      properties:
130        compatible:
131          contains:
132            enum:
133              - axis,artpec8-mct
134              - google,gs101-mct
135              - samsung,exynos2200-mct-peris
136              - samsung,exynos5260-mct
137              - samsung,exynos5420-mct
138              - samsung,exynos5433-mct
139              - samsung,exynos850-mct
140              - samsung,exynos8895-mct
141              - samsung,exynos990-mct
142    then:
143      properties:
144        interrupts:
145          minItems: 12
146          maxItems: 12
147
148  - if:
149      properties:
150        compatible:
151          contains:
152            enum:
153              - tesla,fsd-mct
154    then:
155      properties:
156        interrupts:
157          minItems: 16
158          maxItems: 16
159
160additionalProperties: false
161
162examples:
163  - |
164    // In this example, the IP contains two local timers, using separate
165    // interrupts, so two local timer interrupts have been specified,
166    // in addition to four global timer interrupts.
167    #include <dt-bindings/clock/exynos4.h>
168    #include <dt-bindings/interrupt-controller/arm-gic.h>
169
170    timer@10050000 {
171        compatible = "samsung,exynos4210-mct";
172        reg = <0x10050000 0x800>;
173        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
174        clock-names = "fin_pll", "mct";
175
176        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
177                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
178                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
179                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
180                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
181                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
182    };
183
184  - |
185    // In this example, the timer interrupts are connected to two separate
186    // interrupt controllers. Hence, an interrupts-extended is needed.
187    #include <dt-bindings/clock/exynos4.h>
188    #include <dt-bindings/interrupt-controller/arm-gic.h>
189
190    timer@101c0000 {
191        compatible = "samsung,exynos4210-mct";
192        reg = <0x101C0000 0x800>;
193        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
194        clock-names = "fin_pll", "mct";
195
196        interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
197                              <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
198                              <&combiner 12 6>,
199                              <&combiner 12 7>,
200                              <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
201                              <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
202    };
203
204  - |
205    // In this example, the IP contains four local timers, but using
206    // a per-processor interrupt to handle them. Only one first local
207    // interrupt is specified.
208    #include <dt-bindings/clock/exynos4.h>
209    #include <dt-bindings/interrupt-controller/arm-gic.h>
210
211    timer@10050000 {
212        compatible = "samsung,exynos4412-mct";
213        reg = <0x10050000 0x800>;
214        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
215        clock-names = "fin_pll", "mct";
216
217        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
218                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
219                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
220                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
221                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
222    };
223
224  - |
225    // In this example, the IP contains four local timers, but using
226    // a per-processor interrupt to handle them. All the local timer
227    // interrupts are specified.
228    #include <dt-bindings/clock/exynos4.h>
229    #include <dt-bindings/interrupt-controller/arm-gic.h>
230
231    timer@10050000 {
232        compatible = "samsung,exynos4412-mct";
233        reg = <0x10050000 0x800>;
234        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
235        clock-names = "fin_pll", "mct";
236
237        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
238                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
239                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
240                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
241                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
242                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
243                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
244                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
245    };
246