1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/xlnx,spdif.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx SPDIF IP 8 9description: 10 The IP supports playback and capture of SPDIF audio. 11 12maintainers: 13 - Vincenzo Frascino <vincenzo.frascino@arm.com> 14 15allOf: 16 - $ref: dai-common.yaml# 17 18properties: 19 compatible: 20 enum: 21 - xlnx,spdif-2.0 22 23 reg: 24 maxItems: 1 25 26 interrupts: 27 items: 28 - description: SPDIF audio interrupt 29 30 clock-names: 31 items: 32 - const: aud_clk_i 33 - const: s_axi_aclk 34 35 clocks: 36 minItems: 1 37 items: 38 - description: input audio clock 39 - description: clock for the AXI data stream 40 41 xlnx,spdif-mode: 42 $ref: /schemas/types.yaml#/definitions/uint32 43 enum: 44 - 0 45 - 1 46 description: | 47 0 - receiver 48 1 - transmitter 49 50 xlnx,aud_clk_i: 51 $ref: /schemas/types.yaml#/definitions/uint32 52 description: 53 Input audio clock frequency. It affects the sampling rate. 54 55required: 56 - compatible 57 - reg 58 - interrupts 59 - clock-names 60 - clocks 61 62additionalProperties: false 63 64examples: 65 - | 66 spdif@80010000 { 67 compatible = "xlnx,spdif-2.0"; 68 reg = <0x80010000 0x10000>; 69 clock-names = "aud_clk_i", "s_axi_aclk"; 70 clocks = <&misc_clk_0>, <&clk 71>; 71 interrupt-parent = <&gic>; 72 interrupts = <0 91 4>; 73 xlnx,spdif-mode = <1>; 74 xlnx,aud_clk_i = <49152913>; 75 }; 76 77... 78