1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/xlnx,audio-formatter.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx PL audio formatter 8 9description: 10 The IP core supports DMA, data formatting(AES<->PCM conversion) 11 of audio samples. 12 13maintainers: 14 - Vincenzo Frascino <vincenzo.frascino@arm.com> 15 16allOf: 17 - $ref: dai-common.yaml# 18 19properties: 20 compatible: 21 enum: 22 - xlnx,audio-formatter-1.0 23 24 reg: 25 maxItems: 1 26 27 interrupt-names: 28 minItems: 1 29 items: 30 - const: irq_mm2s 31 - const: irq_s2mm 32 33 interrupts: 34 minItems: 1 35 items: 36 - description: interrupt from MM2S block 37 - description: interrupt from S2MM block 38 39 clock-names: 40 minItems: 1 41 items: 42 - const: s_axi_lite_aclk 43 - const: aud_mclk 44 45 clocks: 46 minItems: 1 47 items: 48 - description: clock for the axi data stream 49 - description: clock for the MEMS microphone data stream 50 51required: 52 - compatible 53 - reg 54 - interrupt-names 55 - interrupts 56 - clock-names 57 - clocks 58 59additionalProperties: false 60 61examples: 62 - | 63 audio_formatter@80010000 { 64 compatible = "xlnx,audio-formatter-1.0"; 65 reg = <0x80010000 0x1000>; 66 interrupt-names = "irq_mm2s", "irq_s2mm"; 67 interrupt-parent = <&gic>; 68 interrupts = <0 104 4>, <0 105 4>; 69 clock-names = "s_axi_lite_aclk", "aud_mclk"; 70 clocks = <&clk 71>, <&clk_wiz_1 0>; 71 }; 72... 73