1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2) 8 9maintainers: 10 - Biju Das <biju.das.jz@bp.renesas.com> 11 12allOf: 13 - $ref: dai-common.yaml# 14 15properties: 16 compatible: 17 items: 18 - enum: 19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five 20 - renesas,r9a07g044-ssi # RZ/G2{L,LC} 21 - renesas,r9a07g054-ssi # RZ/V2L 22 - renesas,r9a08g045-ssi # RZ/G3S 23 - const: renesas,rz-ssi 24 25 reg: 26 maxItems: 1 27 28 interrupts: 29 minItems: 2 30 maxItems: 3 31 32 interrupt-names: 33 oneOf: 34 - items: 35 - const: int_req 36 - const: dma_rx 37 - const: dma_tx 38 - items: 39 - const: int_req 40 - const: dma_rt 41 42 clocks: 43 maxItems: 4 44 45 clock-names: 46 items: 47 - const: ssi 48 - const: ssi_sfr 49 - const: audio_clk1 50 - const: audio_clk2 51 52 power-domains: 53 maxItems: 1 54 55 resets: 56 maxItems: 1 57 58 dmas: 59 minItems: 1 60 maxItems: 2 61 62 dma-names: 63 oneOf: 64 - items: 65 - const: tx 66 - const: rx 67 - items: 68 - const: rt 69 70 '#sound-dai-cells': 71 const: 0 72 73 port: 74 $ref: audio-graph-port.yaml#/definitions/port-base 75 description: Connection to controller providing I2S signals 76 77required: 78 - compatible 79 - reg 80 - interrupts 81 - interrupt-names 82 - clocks 83 - clock-names 84 - resets 85 - '#sound-dai-cells' 86 87unevaluatedProperties: false 88 89examples: 90 - | 91 #include <dt-bindings/interrupt-controller/arm-gic.h> 92 #include <dt-bindings/clock/r9a07g044-cpg.h> 93 94 ssi0: ssi@10049c00 { 95 compatible = "renesas,r9a07g044-ssi", 96 "renesas,rz-ssi"; 97 reg = <0x10049c00 0x400>; 98 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 100 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; 101 interrupt-names = "int_req", "dma_rx", "dma_tx"; 102 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 103 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 104 <&audio_clk1>, 105 <&audio_clk2>; 106 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 107 power-domains = <&cpg>; 108 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 109 dmas = <&dmac 0x2655>, 110 <&dmac 0x2656>; 111 dma-names = "tx", "rx"; 112 #sound-dai-cells = <0>; 113 }; 114